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Title: First look at BFL's ASIC hardware (PCB & enclosure renders) Post by: enmaku on September 25, 2012, 06:10:22 PM http://codinginmysleep.com/first-look-at-bfls-asic-hardware/
Title: Re: First look at BFL's ASIC hardware (PCB & enclosure renders) Post by: Desolator on September 25, 2012, 06:21:36 PM isn't that their old bitforce single which is also called a bitforce single? I've never seen the PCB on the FPGA one but that exterior is identical. If it's the real one, it does beg the question, how did you get your hands on it? Does BFL just love you so much? :P It doesn't make sense that they'd launch it to a blog instead of the main bitcoin forums where everyone is. not to mention, their own facebook page or their own website.
Speaking of that, this is the jalapeno chassis: http://i129.photobucket.com/albums/p227/wizzerd911/jalapeno_zps24159a66.jpg Title: Re: First look at BFL's ASIC hardware (PCB & enclosure renders) Post by: enmaku on September 25, 2012, 06:37:07 PM how did you get your hands on it? Does BFL just love you so much? :P It doesn't make sense that they'd launch it to a blog instead of the main bitcoin forums where everyone is. not to mention, their own facebook page or their own website. It basically boils down to this: There was some controversy over one of BFL's execs, Sonny Vleisides that was casting doubts on the company itself and whether the ASICs even existed. I had an interview with Sonny in which this and bunch of other still-secret stuff was shown to me. While no single piece of info was conclusive, the combined weight of the bits I was shown convinced me pretty thoroughly that they did exist and I published something to that effect. The levels of bile and vitriol that resulted were absolutely insane, with people calling me a "paid shill" and even accusing me of being Sonny himself. So why did I get to publish this first? Basically because Sonny felt bad about the treatment I'd received for giving them a public thumbs-up. I also suspect that I may just be better at driving traffic, though that's one secret I'm sure BFL will never confirm or deny. ;D Title: Re: First look at BFL's ASIC hardware (PCB & enclosure renders) Post by: P_Shep on September 25, 2012, 06:58:18 PM isn't that their old bitforce single which is also called a bitforce single? I've never seen the PCB on the FPGA one but that exterior is identical. That'll be the single SC alright, very nice. The single, most identifiably, would have just two large FPGA pads taking up most of the PCB. so if the single uses 8 chips, and Jally (presubably) one, then I guess the chip must work at half speed in the Jally. (40/8=5GH/s per chip) Title: Re: First look at BFL's ASIC hardware (PCB & enclosure renders) Post by: dlasher on September 25, 2012, 07:36:13 PM Archived just in case : http://imgur.com/a/TW0Tt https://i.imgur.com/LkTEW.png https://i.imgur.com/GDIjbh.png Title: Re: First look at BFL's ASIC hardware (PCB & enclosure renders) Post by: enmaku on September 25, 2012, 07:42:01 PM so if the single uses 8 chips, and Jally (presubably) one, then I guess the chip must work at half speed in the Jally. I don't think I'd be giving too much away or violating any trust to say that BFL's primary goal with the Jalapeno is power consumption, so lowered clock speed and less chips wouldn't be too far-fetched of an assumption. Title: Re: First look at BFL's ASIC hardware (PCB & enclosure renders) Post by: Desolator on September 25, 2012, 07:47:34 PM That'll be the single SC alright, very nice. The single, most identifiably, would have just two large FPGA pads taking up most of the PCB. so if the single uses 8 chips, and Jally (presubably) one, then I guess the chip must work at half speed in the Jally. (40/8=5GH/s per chip) Oh, I see. I have indeed seen photos of it then: http://i129.photobucket.com/albums/p227/wizzerd911/bfl2_zpsabbc1f05.png That is significantly different. SO SHINY and decentralized heat :D btw I found another picture of a butterfly lab lol http://i129.photobucket.com/albums/p227/wizzerd911/butterflylab.jpg Title: Re: First look at BFL's ASIC hardware (PCB & enclosure renders) Post by: dlasher on September 25, 2012, 11:20:48 PM isn't that their old bitforce single which is also called a bitforce single? I've never seen the PCB on the FPGA one but that exterior is identical. That'll be the single SC alright, very nice. The single, most identifiably, would have just two large FPGA pads taking up most of the PCB. so if the single uses 8 chips, and Jally (presubably) one, then I guess the chip must work at half speed in the Jally. (40/8=5GH/s per chip) Or they're using a higher version of a chip in the SC than the Jally. Title: Re: First look at BFL's ASIC hardware (PCB & enclosure renders) Post by: Desolator on September 29, 2012, 03:39:19 PM But they're really, really fast at any level! Asics' own website even claims that when you add asics, it makes you run really, really fast lol.
http://www.asicsamerica.com/sports/running/ |
