Bitcoin Forum

Update 11-Nov: bounty is closed, thanks to BFL for posting a photo from a dead chip!


Hi, I'll give 5 BTC to whoever can figure out the die size for the Altera EP3SL150F780.  This is the chip used in the BFL Single (https://bitcointalk.org/index.php?topic=79825.0).  You have to present evidence that would convince a reasonable person that your answer is correct, so please don't post guesses.

Finding this number in Altera documentation would be perfect, but it's unlikely that they publish it (Xilinx doesn't).  Grinding the top off of a dead chip, pulling out a ruler, and taking a photo will work too.  I searched for a while on the interwebs but couldn't find it -- if you're better with teh googles than I am, step up and get paid.

I need this figure in order to compute the η-factor (https://bitcointalk.org/index.php?topic=119668.0) for the BFL Single.

I have offered bounties like this in the past and have a history of paying promptly (https://bitcointalk.org/index.php?topic=79825.msg886359#msg886359).

http://www.altera.com/download/board-layout-test/bsdl/stratix3/stx3-index.jsp
780-pin FineLine BGA    EP3SL150F780    1.01
>>>ftp://ftp.altera.com/outgoing/download/bsdl/EP3SL150F780.bsd (ftp://ftp.altera.com/outgoing/download/bsdl/EP3SL150F780.bsd)<<<


Package       : 29 mm 780FBGA


-- Copyright (C) 1998-2009 Altera Corporation
--
-- File Name     : EP3SL150F780
-- Device        : EP3SL150F780
-- Package       : 29 mm 780FBGA
-- BSDL Version  : 1.01
-- Date Created  : 01/12/2009
-- Created by    : Altera BSDL Generation Program Ver. 2.0
-- Documentation : STRATIX III Family Datasheet
--                 STRATIX III Handbook Chapter: IEEE 1149.1 (JTAG)
--                 Boundary Scan Testing in STRATIX III Devices

He asked for die size, the silicon inside, not for package size.

 ::) I guess I had a brain fart, I read *nm* for some reason, I double check and instead I see *mm*

Yep.

If I remember, the silicon is 17x17mm.  The package is 29x29mm.  I'll measure it and confirm when I get into the office today.

Hey cool.  If you can post something from Altera, or a photo, I'd appreciate it (and will send you 5 BTC, of course).

This has to be unobtanium info unless you call Altera or pop the heat spreader on the chip. There is no indication of the physical TMSC-made die. For all we know, they could be the same die throughout the entire Stratix III line or parts of it, with yield-disabled LEs, they could even have two or three base die masks where all can potentially be smaller products but only one or two of them could be SL150..., there could be different mask or process revisions throughout time affecting die size, etc.

"Stratix III, Cyclone III and Cyclone IV products are fabricated on a 65/60 nm process technology that
supports up to 9 layers of Cu metallization and Low-k with one layer of Salicided polysilicon. Stratix
III devices are available in FlipChip FBGA packages with logic density ranging from 47.5K to 337.5K
LEs and 2,430 to 20,491 Kbits of total memory. Cyclone III and Cyclone IV devices are available in
QFP, QFN, FBGA and UBGA packages with logic density ranging from 5,136 to 149,760 LEs and 414
to 6,480 Kbits of memory. The Stratix III product families operate with a 1.1V supply. Cyclone III and
Cyclone IV product families operate with a 1.2V supply. Lifetest is conducted at 1.32V and 1.44V
respectively, which is a 20% overvoltage. Lifetest uses dynamic life with a real clocked configuration
and was run at junction temperature of 125°C to keep it below absolute maximum ratings.

Stratix III EP3SL150 (DE3-150)
•142,000 logic elements (LEs)
•5,499K total memory Kbits
•384 18x18-bit multipliers blocks
•736 user I/Os"

http://www.butterflylabs.com/wp-content/uploads/2012/11/AlteraST3150.jpg

You can send the 5btc to the Freenet project   ( https://freenetproject.org/ )
Their wallet is:  1966U1pjj15tLxPXZ19U48c99EJDkdXeqb

For more information:  https://freenetproject.org/donate.html

On the other hand, if subSTRATA qualified for it first.  That's fine too...  I haven't looked at the document he provided.

Thx

I think, this circuit board is one of a Minirig.
It's labeled with Bitforce 2.0!

Or the device they tested there wasn't a EP3SL150F780 but was some other F780 device.

Single and Minirig have different chip.
And Bitforce 2.0 is definitely from a Mini Rig.
We see for the first time the die from a mini Rig board!
This board run with 1.5GH/s and need 71Watt!

It doesn't work like this in the FPGA business. You just cannot sell the chips with eg. half of the cache disabled, like CPU. The exact planar routing structure of any FPGA is discoverable.

About the only permanent defect that can make a chip still sellable is in some of the I/O pads: the same chips are packaged in various carriers with different pinout counts.

It is possible to market chips with various parts of the circuitry significantly derated. But those chips receive a different catalog number and internal identification number readable by eg. JTAG. Brand protection of the manufecturer demands such measures.

Actually, this photo was of a one off board that was played with in the Lab...   The PCB is Mini Rig and the Processors are from the Single.  It's not meant to work for mining, it was for other tests.  Those are the Altera STIII chips with the heat spreader removed.

Where?

Awesome, thanks!



Very noble of you.  I'll send the BTC tomorrow morning and post the transaction ID in this thread.

Thanks again!

Out of curiosity, does anybody know why Blockchain.info displays this "public note" for the address above?

  Public Note: Yes, I'm fraudster and I make money by scamming idiots around the world, so I have decided to share some of my money with you, losers. :D

My guess is that this is some sort of ill-concieved tainting scheme gone haywire (as tainting schemes inevitably do…)

http://www.tricone-mining.com/images/freenet.project.public.note.png

Since that address is not transaction-specific and appears to receive 5BTC donations from time to time, I will distinguish my send by using the amount 5.20288651 BTC.  This amount is derived from the shasum of my username:


  $ (echo 16i; (echo -n eldentyrell | shasum | tr a-z A-Z | cut -b1-8); echo f) | dc
  202886511

Sent: 594d45fc70621d6c23b27b2b40800f1e2e78cd63ab6dcf4f331dd88ca9e1af56 (http://blockchain.info/tx/594d45fc70621d6c23b27b2b40800f1e2e78cd63ab6dcf4f331dd88ca9e1af56)

You aren't reading that report correctly (or you aren't convincing anyone you found an answer). That particular part of the report is detailing the solder reliability of the different BGA packages, and each line is a report of a specific test case. It doesn't list the model of die core or the FPGA series tested (or if it is even an FPGA) - it merely lists the die size of the particular chip tested in the reliability trial. This is why there are multiple die sizes for each package type listed, because many different FPGAs can go in a particular package, just like many different CPU cores can go in an AMD socket AM2 package.

Both, in fact!

That document gives the reliability figures for the solder joints on Altera packages.  The column with the heading "die size" is probably the maximum die size or else the size of the die that was in the package when they tested the package's reliability.  Either way there are two rows for "F780" with wildly different numbers in the "die size" column, so interpreting the column to mean "every chip in this package has this die size" is obviously incorrect.