Bitcoin Forum

   [match_work_count1] => 33
   [match_work_count2] => 29
   [match_work_count3] => 42
   [match_work_count4] => 42
   [match_work_count5] => 23
   [match_work_count6] => 30
   [match_work_count7] => 39
   [match_work_count8] => 41
   [match_work_count9] => 0 остальные все 0 (я только одну плату подцепил для удобства)

bit[20:16] clock input divider R
bit[27:21] clock feedback divider F
bit[29:28] clock output divider OD
hash unit working clock frequency = XCLKIN frequency * (F+1)/((R+1)*(2^OD)).
F, R and OD configuration should satisfy the following three conditions:
10MHz <= XCLKIN/(R+1) <= 50MHz
500MHz <= XCLKIN*(F+1)/(R+1) <= 1000MHz
62.5MHz <= XCLKIN*(F+1)/((R+1)*(2^OD)) <= 1000MHz

bit[28:18]:clock main divider N
bit[34:29]:clock input divider R
hash unit working clock frequency = XCLKIN frequency * N/(2*R).
N and R configuration should satisfy the following two conditions:
0.2MHz < XCLKIN/(2*R) < 6MHz 500MHz < XCLKIN*N/R < 900MHz

struct avalon_task {
	uint8_t reset		:1;
	uint8_t flush_fifo	:1;
	uint8_t fan_eft		:1;
	uint8_t timer_eft	:1;
	uint8_t asic_num	:4;
	uint8_t fan_pwm_data;
	uint8_t timeout_data;
	uint8_t miner_num;

	uint8_t nonce_elf		:1;
	uint8_t gate_miner_elf		:1;
	uint8_t asic_pll		:1;
	uint8_t gate_miner		:1;
	uint8_t _pad0			:4;
	uint8_t _pad1[3];
	uint32_t _pad2;

	uint8_t midstate[32];
	uint8_t data[12];
} __attribute__((packed, aligned(4)));