Bitcoin Forum

Open Source Vanitygen for FPGAs

Source on Github (https://github.com/fpgaminer/fpgaminer-vanitygen)

Animated Github Log (http://starlogs.net/#fpgaminer/fpgaminer-vanitygen)



April 13th, 2013
The first Open Source Vanity Address Generation for FPGAs firmware is now available on Github!  This first release targets the Altera Cyclone III C120 Development Board, and is more a proof of concept than anything else.  It's functional, but only runs at ~40Kk/s.  Feel free to dive in and port to your own FPGA boards.

I have more performant code under development (unrolled/pipelined).

See the OP for links to the source code and such.




Original Post, March 12th, 2013. (https://bitcointalk.org/index.php?topic=152444.msg1827226#msg1827226)

source is always welcome :)

For an FPGA, the numbers are low, but I guess as more work is put into it, you may be able to get it done faster than say a GPU which can typically do 30 million/s or more.

I certainly like the idea. My FPGA's will eventually need an alternative purpose, once I moved onto ASIC.
Most likely FPGA's would do it a lot faster, than trying to use the GPU in my Laptop.

Would these work on Spartan 6 based boards?

Damn, this is really awesome. Hell of a job, fpgaminer!

Copy of OP from March 12th, 2013 - Copied, since the OP has been replaced with something more useful.

I just finished testing my implementation of vanitygen on an Altera Cyclone 3 development kit.  It got lucky and generated 1fpgaw5jo9aS1JB8uAw5rRcnM2QiTAVhQ after only ~66million attempts.

It operates off my usual virtual_wire development setup right now; I can feed it a starting public key, and the hash range to look for.  It will report back the private key offset when a match is found.

Current performance using one vanity core is ~40Kk/s.  I expect initial performance once the number of cores is cranked up to be about 400Kk/s on this devkit.  I haven't done any optimizations.  Power consumption is 300mW right now.

Here is a screenshot of my second session, where I was double checking the results of the first test.
https://i.imgur.com/ic34BD3.png


Let me know if there's any interest in me releasing the source code.  On a cursory glance I didn't see any open source FPGA solutions for Bitcoin's ECDSA curve, nor RIPEMD-160.  It would be cool to see the ECDSA code rolled into an SoC like Milkymist, and act as a low-running-cost, high-performance Bitcoin node.

In the meantime, I'll probably concentrate on getting performance up and porting over to the X6500.

The first Open Source Vanity Address Generation for FPGAs firmware is now available on Github!  This first release targets the Altera Cyclone III C120 Development Board, and is more a proof of concept than anything else.  It's functional, but only runs at ~40Kk/s.  Feel free to dive in and port to your own FPGA boards.

I have more performant code under development (unrolled/pipelined).

See the OP for links to the source code and such.

Would be nice if it generated compressed public keys instead. Doing so shouldn't take any longer, may even be faster— the compressed key is just the x part of the public key with the initial byte set based on Y being even/odd. The uncompressed forms result in keys that take up almost twice the space when spending.

It only generates compressed public keys.

I managed to get this running on a DE0-Nano without modifications.

How did you determine the hash rate?

So today I've spent a few hours digging int bitcoin addres generation and fpgas.

Now I have a decent looking pipline for the address generation scetched on my whiteboard.

As I have no expierience in writing cryptographically secure applications (only scientifical computing so far) it is going to be a pure vanity miner with absolutly no security. Lets see how well a fpga noob will do.

Cant wait

Bump! @fpgaminer, did you do much further work on the fgpa vanity miner? (even over Christmas holiday season maybe?)

I'm really interested in parallellising it more as you said could be done, but I have no electronics experience since a little at university over 15yrs ago (did some vhdl/verilog/microprocessor stuff in my Computer-science degree but only basic stuff, I was more of a software programmer so picked a course that was more focussed on that). Maybe I wish I'd remembered more/cared more now...

I am however a good (even if I say so myself) C/C++/Python developer who works on performance-critical apps in the regular (non-btc, corporate) finance world. OpenCL is more C-like and easier for me to get into I'm guessing (from what I've seen of examples) and seems to be picking up a lot of interest but I'm not sure if I can run the ocl miner intended mostly for GPU's on an fpga, say an Altera or Ztex one - not found any opencl compiler kits after a bit of a cursory look so guessing no chance for now.

I'm also curious how that 40Kh/s vanity-mining compares to the regular bitcoin mining rate you get on the same hardware - what's the hash-rate ratio? Am trying to work out estimates.

Is there anything I can do to help? Even if its just donations to motivate you :) , but if there's code or (with lots of reading & learning on my part) some fpga logic designing or optimising I might be able to learn enough about to assist with, I'll give it a good go (to learn enough to help).

Is anyone running the fpga vanity miner at the moment or are you all doing other types of mining with them/using GPUs only? (and if not using fpgaminer-vanitygen, is it just cos its more profitable?/other reason?)

Is it easy to use vanitygen with an r280 and the latest drivers?  I can't seem to find much information and cpu generation isn't very feasible for strings with length 7+.

What is the goal with porting to FPGA?  (in terms of feasible string length within ~1 day)

HASH RATES for GPU's
 (https://en.bitcoin.it/wiki/Mining_hardware_comparison)
Hash Rates listed above ^^

So you generate thousands of key pairs to win one with bitcoins inside?

No.  That would require enough compute power to drain all the Sun's energy.

Hello.
How run this vanitygen on amazon insance F1?
https://aws.amazon.com/ec2/instance-types/f1/?nc1=h_ls
FPGA Xilinx UltraScale+ VU9P