Title: s9 > batch 16 and Auto-Tune Issues
Post by: NotFuzzyWarm on October 13, 2016, 11:08:18 PM
Just got a s9 batch-17 and... Bitmain has changed the firmware. I will post in detail tomorrow but for a summary of changes: - They have changed the board channels used and so the temp reporting channels. Now using channels 6, 7, and 8.
- Looks like changing the frequency may be gone. There is no longer a GUI option to change it. On startup, the firmware goes through several checks per-board and sets the best freq and possibly Vcore as well per-board. When all is done, the boards report different frequencies. This could turn out to be rather -- interesting.
- Looking at the Kernel Log it shows several lists of freq and voltage it tries for each board. A note at the beginning of each list says that freq is now stored in the PIC. Now does that mean that a warm boot bypasses the testing -- dunna know but hope so.
I'll post the Kernel Log tomorrow. Also fan speed no longer has a setting on the BMminer GUI. Log says is set as needed starting at 40% Oh, the fans are on different channels as well. Think fans are now reported in position 6 an 8. I'll verify tomorrow. edit: Fans in positions 3 and 6 Due to the time it takes for the new booting process -- around 4 min or more -- better set dead miner/offline/etc monitoring to wait at least that 4 maybe even 5 min before trying to issue another reboot call to the miner... Frankly, during the setup process for miner name and pool assignments the reboots needed were taking so long that I thought the miner was going to be a DOA! :o Folks, keep in mind that much longer time needed to come to life before you start to get miffed/worried like I was. A couple times when it was taking A LOT longer than was normal with the earlier batches I forced reboots trying to get the miner to respond. thankfully it didn't brick.
Title: Re: s9 batch 17 (and 16?) changes
Post by: Xircom on October 14, 2016, 09:20:46 AM
Fuzzy,
Point taken... ;)
Title: Re: s9 batch 17 (and 16?) changes
Post by: hhumaidan on October 14, 2016, 10:20:05 AM
Please inform us if it is better than the previous batches because I am really considering to buy one that is reliable
Title: Re: s9 batch 17 (and 16?) changes
Post by: NotFuzzyWarm on October 14, 2016, 02:25:06 PM
Please inform us if it is better than the previous batches because I am really considering to buy one that is reliable
For the most part with the S9's it seems it is a crap shoot. I have 8 of the s9 miners spanning batch 1 through 17 and most run fine. Yes 2 of them, a batch-1 and a batch-11 had a hash board die (which were repaired by Bitmain Warranty) but so far it looks like no single batch is better than another.
Title: Re: s9 batch 17 (and 16?) changes
Post by: GrumpyBear2 on October 14, 2016, 06:56:30 PM
Just got mine today, thanks for the warning. It took over five minutes to start hashing after a reboot with my pool settings.
Yep the panel settings have been changed as noted above. But hashing at 11.6 ish.
Title: Re: s9 batch 17 (and 16?) changes
Post by: tntdgcr on October 14, 2016, 06:59:55 PM
Just got mine today, thanks for the warning. It took over five minutes to start hashing after a reboot with my pool settings.
Yep the panel settings have been changed as noted above. But hashing at 11.6 ish.
we got a large batch in yesterday of the 12 Evens. Most work as advertised ( only one is 11.2 TH ) . They definitely take longer to boot / mine , up to 20 Min of Uptime before mining, and I think it's due to the mixed Boards in the unit. They are clocking up / down to what they can work on, and I feel this is probably why they use BM Miner over CG Miner. After a while the units work fine. You can no longer tinker with Freq.
Title: Re: s9 batch 17 (and 16?) changes
Post by: NotFuzzyWarm on October 14, 2016, 07:19:41 PM
The Kernel Log from s9 b17 after finishing its's boot checks: [ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.14.0-xilinx-gf387dab-dirty (lzq@armdev01) (gcc version 4.8.3 20140320 (prerelease) (Sourcery CodeBench Lite 2014.05-23) ) #38 SMP PREEMPT Fri Jun 17 20:02:51 CST 2016
[ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine model: Xilinx Zynq
[ 0.000000] cma: CMA: reserved 128 MiB at 27800000
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] On node 0 totalpages: 258048
[ 0.000000] free_area_init_node: node 0, pgdat c06e4600, node_mem_map e6fd8000
[ 0.000000] Normal zone: 1520 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 194560 pages, LIFO batch:31
[ 0.000000] HighMem zone: 496 pages used for memmap
[ 0.000000] HighMem zone: 63488 pages, LIFO batch:15
[ 0.000000] PERCPU: Embedded 8 pages/cpu @e6fc0000 s9088 r8192 d15488 u32768
[ 0.000000] pcpu-alloc: s9088 r8192 d15488 u32768 alloc=8*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 256528
[ 0.000000] Kernel command line: noinitrd mem=1008M console=ttyPS0,115200 root=/dev/mtdblock1 rootfstype=jffs2 rw rootwait
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 884528K/1032192K available (4764K kernel code, 271K rwdata, 1816K rodata, 200K init, 257K bss, 147664K reserved, 253952K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xef800000 ( 760 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc06752f8 (6581 kB)
[ 0.000000] .init : 0xc0676000 - 0xc06a8380 ( 201 kB)
[ 0.000000] .data : 0xc06aa000 - 0xc06edd00 ( 272 kB)
[ 0.000000] .bss : 0xc06edd0c - 0xc072e4fc ( 258 kB)
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] Dump stacks of tasks blocking RCU-preempt GP.
[ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] ps7-slcr mapped to f0004000
[ 0.000000] zynq_clock_init: clkc starts at f0004100
[ 0.000000] Zynq clock init
[ 0.000015] sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 3298534883328ns
[ 0.000301] ps7-ttc #0 at f0006000, irq=43
[ 0.000605] Console: colour dummy device 80x30
[ 0.000641] Calibrating delay loop... 1325.46 BogoMIPS (lpj=6627328)
[ 0.040204] pid_max: default: 32768 minimum: 301
[ 0.040412] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.040434] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.042525] CPU: Testing write buffer coherency: ok
[ 0.042869] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.042929] Setting up static identity map for 0x482448 - 0x4824a0
[ 0.043144] L310 cache controller enabled
[ 0.043165] l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72760000, Cache size: 512 kB
[ 0.121023] CPU1: Booted secondary processor
[ 0.210224] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.210355] Brought up 2 CPUs
[ 0.210374] SMP: Total of 2 processors activated.
[ 0.210382] CPU: All CPU(s) started in SVC mode.
[ 0.211039] devtmpfs: initialized
[ 0.213416] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[ 0.214628] regulator-dummy: no parameters
[ 0.221873] NET: Registered protocol family 16
[ 0.224089] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.226379] cpuidle: using governor ladder
[ 0.226392] cpuidle: using governor menu
[ 0.233760] syscon f8000000.ps7-slcr: regmap [mem 0xf8000000-0xf8000fff] registered
[ 0.235261] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
[ 0.235274] hw-breakpoint: maximum watchpoint size is 4 bytes.
[ 0.235380] zynq-ocm f800c000.ps7-ocmc: ZYNQ OCM pool: 256 KiB @ 0xf0080000
[ 0.256941] bio: create slab <bio-0> at 0
[ 0.258373] vgaarb: loaded
[ 0.259073] SCSI subsystem initialized
[ 0.259949] usbcore: registered new interface driver usbfs
[ 0.260121] usbcore: registered new interface driver hub
[ 0.260496] usbcore: registered new device driver usb
[ 0.261023] media: Linux media interface: v0.10
[ 0.261213] Linux video capture interface: v2.00
[ 0.261453] pps_core: LinuxPPS API ver. 1 registered
[ 0.261465] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.261587] PTP clock support registered
[ 0.261959] EDAC MC: Ver: 3.0.0
[ 0.263013] Advanced Linux Sound Architecture Driver Initialized.
[ 0.265839] DMA-API: preallocated 4096 debug entries
[ 0.265854] DMA-API: debugging enabled by kernel config
[ 0.265934] Switched to clocksource arm_global_timer
[ 0.286919] NET: Registered protocol family 2
[ 0.287557] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.287652] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.287812] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.287873] TCP: reno registered
[ 0.287891] UDP hash table entries: 512 (order: 2, 16384 bytes)
[ 0.287944] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[ 0.288205] NET: Registered protocol family 1
[ 0.288560] RPC: Registered named UNIX socket transport module.
[ 0.288572] RPC: Registered udp transport module.
[ 0.288580] RPC: Registered tcp transport module.
[ 0.288588] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.288601] PCI: CLS 0 bytes, default 64
[ 0.289028] hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
[ 0.291033] futex hash table entries: 512 (order: 3, 32768 bytes)
[ 0.292461] bounce pool size: 64 pages
[ 0.293336] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[ 0.293541] msgmni has been set to 1487
[ 0.294002] io scheduler noop registered
[ 0.294014] io scheduler deadline registered
[ 0.294050] io scheduler cfq registered (default)
[ 0.308117] dma-pl330 f8003000.ps7-dma: Loaded driver for PL330 DMAC-2364208
[ 0.308138] dma-pl330 f8003000.ps7-dma: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
[ 0.430891] e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 82, base_baud = 3124999) is a xuartps
[ 1.002723] console [ttyPS0] enabled
[ 1.007012] xdevcfg f8007000.ps7-dev-cfg: ioremap 0xf8007000 to f0068000
[ 1.014638] [drm] Initialized drm 1.1.0 20060810
[ 1.031685] brd: module loaded
[ 1.041071] loop: module loaded
[ 1.050648] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 1.056479] e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
[ 1.064203] libphy: XEMACPS mii bus: probed
[ 1.068742] ------------- phy_id = 0x3625e62
[ 1.073490] xemacps e000b000.ps7-ethernet: pdev->id -1, baseaddr 0xe000b000, irq 54
[ 1.082191] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 1.088852] ehci-pci: EHCI PCI platform driver
[ 1.096091] zynq-dr e0002000.ps7-usb: Unable to init USB phy, missing?
[ 1.102897] usbcore: registered new interface driver usb-storage
[ 1.109783] mousedev: PS/2 mouse device common for all mice
[ 1.115866] i2c /dev entries driver
[ 1.122759] zynq-edac f8006000.ps7-ddrc: ecc not enabled
[ 1.128354] cpufreq_cpu0: failed to get cpu0 regulator: -19
[ 1.134235] Xilinx Zynq CpuIdle Driver started
[ 1.139113] sdhci: Secure Digital Host Controller Interface driver
[ 1.145204] sdhci: Copyright(c) Pierre Ossman
[ 1.149621] sdhci-pltfm: SDHCI platform and OF driver helper
[ 1.156376] mmc0: no vqmmc regulator found
[ 1.160390] mmc0: no vmmc regulator found
[ 1.195953] mmc0: SDHCI controller on e0100000.ps7-sdio [e0100000.ps7-sdio] using ADMA
[ 1.204636] usbcore: registered new interface driver usbhid
[ 1.210146] usbhid: USB HID core driver
[ 1.214863] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
[ 1.221159] nand: Micron MT29F2G08ABAEAWP
[ 1.225125] nand: 256MiB, SLC, page size: 2048, OOB size: 64
[ 1.231164] Bad block table found at page 131008, version 0x01
[ 1.237557] Bad block table found at page 130944, version 0x01
[ 1.243693] 4 ofpart partitions found on MTD device pl353-nand
[ 1.249478] Creating 4 MTD partitions on "pl353-nand":
[ 1.254562] 0x000000000000-0x000002000000 : "BOOT.bin-env-dts-kernel"
[ 1.262620] 0x000002000000-0x00000b000000 : "angstram-rootfs"
[ 1.269928] 0x00000b000000-0x00000ec00000 : "upgrade-rootfs"
[ 1.277015] 0x00000ec00000-0x000010000000 : "upgrade-tmp"
[ 1.285633] TCP: cubic registered
[ 1.288907] NET: Registered protocol family 17
[ 1.293543] Registering SWP/SWPB emulation handler
[ 1.299182] regulator-dummy: disabling
[ 1.302958] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 1.313226] ALSA device list:
[ 1.316190] No soundcards found.
[ 4.547906] jffs2: Empty flash at 0x023f600c ends at 0x023f6800
[ 4.599355] jffs2: jffs2_scan_inode_node(): CRC failed on node at 0x02937fc8: Read 0xffffffff, calculated 0xe89f3896
[ 4.614768] jffs2: Empty flash at 0x02938030 ends at 0x02938800
[ 5.367971] VFS: Mounted root (jffs2 filesystem) on device 31:1.
[ 5.376969] devtmpfs: mounted
[ 5.380078] Freeing unused kernel memory: 200K (c0676000 - c06a8000)
[ 7.099695] random: dd urandom read with 1 bits of entropy available
[ 7.525956]
[ 7.525956] bcm54xx_config_init
[ 8.135957]
[ 8.135957] bcm54xx_config_init
[ 12.136790] xemacps e000b000.ps7-ethernet: Set clk to 124999998 Hz
[ 12.142897] xemacps e000b000.ps7-ethernet: link up (1000/FULL)
[ 28.638592] In axi fpga driver!
[ 28.641659] request_mem_region OK!
[ 28.645049] AXI fpga dev virtual address is 0xf0112000
[ 28.650195] *base_vir_addr = 0x8c504
[ 28.661345] In fpga mem driver!
[ 28.664418] request_mem_region OK!
[ 28.668045] fpga mem virtual address is 0xf3000000
[ 30.895159]
[ 30.895159] bcm54xx_config_init
[ 31.675104]
[ 31.675104] bcm54xx_config_init
[ 36.675419] xemacps e000b000.ps7-ethernet: Set clk to 124999998 Hz
[ 36.681523] xemacps e000b000.ps7-ethernet: link up (1000/FULL)
[ 85.994692] jffs2: warning: (1095) jffs2_do_read_inode_internal: Truncating ino #2089 to 46292 bytes failed because it only had 27394 bytes to start with!
[ 332.299897] random: nonblocking pool is initialized
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[5]
Find hashboard on Chain[6]
Find hashboard on Chain[7]
has freq in PIC, will disable freq setting.
chain[5] has freq in PIC and will jump over...
has freq in PIC, will disable freq setting.
chain[6] has freq in PIC and will jump over...
has freq in PIC, will disable freq setting.
chain[7] has freq in PIC and will jump over...
set command mode to VIL
singleBoardTest: AsicType = 1387
singleBoardTest: asicNum = 64
singleBoardTest: real AsicNum = 63
--- check asic number
set_baud=1
The min freq=700
set real timeout 224, need sleep=1634304
disable_pic_dac on chain[5] testDone[5]=1
disable_pic_dac on chain[6] testDone[6]=1
disable_pic_dac on chain[7] testDone[7]=1
search freq for 1 times, completed chain = 3, total chain num = 3
do 12 8xPatten test for 1 times
Find hashboard on Chain[5]
Find hashboard on Chain[6]
Find hashboard on Chain[7]
Test Patten on Chain[5] use PIC freq
Test Patten on Chain[5] use PIC freq
Freq[00]=470 Freq[01]=568 Freq[02]=606 Freq[03]=470 Freq[04]=575 Freq[05]=606 Freq[06]=481 Freq[07]=575
Freq[08]=606 Freq[09]=500 Freq[10]=581 Freq[11]=606 Freq[12]=500 Freq[13]=581 Freq[14]=612 Freq[15]=537
Freq[16]=543 Freq[17]=504 Freq[18]=537 Freq[19]=593 Freq[20]=537 Freq[21]=537 Freq[22]=593 Freq[23]=537
Freq[24]=543 Freq[25]=600 Freq[26]=568 Freq[27]=543 Freq[28]=600 Freq[29]=543 Freq[30]=550 Freq[31]=543
Freq[32]=612 Freq[33]=543 Freq[34]=537 Freq[35]=612 Freq[36]=556 Freq[37]=587 Freq[38]=531 Freq[39]=556
Freq[40]=606 Freq[41]=550 Freq[42]=543 Freq[43]=550 Freq[44]=618 Freq[45]=556 Freq[46]=606 Freq[47]=537
Freq[48]=500 Freq[49]=470 Freq[50]=618 Freq[51]=562 Freq[52]=606 Freq[53]=612 Freq[54]=562 Freq[55]=556
Freq[56]=618 Freq[57]=568 Freq[58]=606 Freq[59]=618 Freq[60]=568 Freq[61]=606 Freq[62]=606
Test Patten on Chain[6] use PIC freq
Test Patten on Chain[6] use PIC freq
Freq[00]=600 Freq[01]=650 Freq[02]=650 Freq[03]=618 Freq[04]=650 Freq[05]=650 Freq[06]=625 Freq[07]=650
Freq[08]=650 Freq[09]=650 Freq[10]=650 Freq[11]=650 Freq[12]=587 Freq[13]=650 Freq[14]=650 Freq[15]=650
Freq[16]=650 Freq[17]=575 Freq[18]=650 Freq[19]=568 Freq[20]=650 Freq[21]=650 Freq[22]=637 Freq[23]=650
Freq[24]=650 Freq[25]=650 Freq[26]=618 Freq[27]=650 Freq[28]=650 Freq[29]=637 Freq[30]=650 Freq[31]=650
Freq[32]=650 Freq[33]=650 Freq[34]=650 Freq[35]=625 Freq[36]=650 Freq[37]=631 Freq[38]=650 Freq[39]=643
Freq[40]=650 Freq[41]=650 Freq[42]=650 Freq[43]=650 Freq[44]=650 Freq[45]=650 Freq[46]=650 Freq[47]=643
Freq[48]=618 Freq[49]=650 Freq[50]=650 Freq[51]=650 Freq[52]=631 Freq[53]=650 Freq[54]=650 Freq[55]=650
Freq[56]=650 Freq[57]=650 Freq[58]=568 Freq[59]=650 Freq[60]=568 Freq[61]=650 Freq[62]=650
Test Patten on Chain[7] use PIC freq
Test Patten on Chain[7] use PIC freq
Freq[00]=575 Freq[01]=656 Freq[02]=625 Freq[03]=575 Freq[04]=656 Freq[05]=656 Freq[06]=575 Freq[07]=656
Freq[08]=656 Freq[09]=581 Freq[10]=656 Freq[11]=656 Freq[12]=593 Freq[13]=656 Freq[14]=656 Freq[15]=656
Freq[16]=656 Freq[17]=650 Freq[18]=656 Freq[19]=650 Freq[20]=656 Freq[21]=656 Freq[22]=656 Freq[23]=537
Freq[24]=656 Freq[25]=656 Freq[26]=581 Freq[27]=656 Freq[28]=656 Freq[29]=650 Freq[30]=656 Freq[31]=550
Freq[32]=656 Freq[33]=631 Freq[34]=656 Freq[35]=656 Freq[36]=656 Freq[37]=537 Freq[38]=656 Freq[39]=656
Freq[40]=643 Freq[41]=656 Freq[42]=656 Freq[43]=643 Freq[44]=562 Freq[45]=656 Freq[46]=656 Freq[47]=650
Freq[48]=656 Freq[49]=656 Freq[50]=656 Freq[51]=656 Freq[52]=568 Freq[53]=656 Freq[54]=631 Freq[55]=625
Freq[56]=656 Freq[57]=656 Freq[58]=556 Freq[59]=656 Freq[60]=575 Freq[61]=656 Freq[62]=656
use PIC voltage=870 on chain[5]
now set pic voltage=125 on chain[5]
use PIC voltage=870 on chain[6]
now set pic voltage=125 on chain[6]
use PIC voltage=870 on chain[7]
now set pic voltage=125 on chain[7]
enable_pic_dac on chain[5]
enable_pic_dac on chain[6]
enable_pic_dac on chain[7]
set command mode to VIL
doHeatBoard: AsicType = 1387
doHeatBoard: asicNum = 64
doHeatBoard: real AsicNum = 63
--- check asic number
check chain[5]: asicNum = 63
check chain[6]: asicNum = 63
check chain[7]: asicNum = 63
Set Freq of PIC for Test Patten on Chain[5]
Set Freq of PIC for Test Patten on Chain[6]
Set Freq of PIC for Test Patten on Chain[7]
set_baud=2
The min freq=470
set real timeout 334, need sleep=2436864
start send works on chain[5]
start send works on chain[6]
start send works on chain[7]
wait send works done on chain[5]
get send work num :57456 on Chain[5]
get send work num :57456 on Chain[7]
get send work num :57456 on Chain[6]
wait send works done on chain[6]
wait send works done on chain[7]
wait recv nonce on chain[5]
wait recv nonce on chain[6]
wait recv nonce on chain[7]
get nonces on chain[5]
require nonce number:912
require validnonce number:57456
freq[00]=470 freq[01]=568 freq[02]=606 freq[03]=470 freq[04]=575 freq[05]=606 freq[06]=481 freq[07]=575
freq[08]=606 freq[09]=500 freq[10]=581 freq[11]=606 freq[12]=500 freq[13]=581 freq[14]=612 freq[15]=537
freq[16]=543 freq[17]=504 freq[18]=537 freq[19]=593 freq[20]=537 freq[21]=537 freq[22]=593 freq[23]=537
freq[24]=543 freq[25]=600 freq[26]=568 freq[27]=543 freq[28]=600 freq[29]=543 freq[30]=550 freq[31]=543
freq[32]=612 freq[33]=543 freq[34]=537 freq[35]=612 freq[36]=556 freq[37]=587 freq[38]=531 freq[39]=556
freq[40]=606 freq[41]=550 freq[42]=543 freq[43]=550 freq[44]=618 freq[45]=556 freq[46]=606 freq[47]=537
freq[48]=500 freq[49]=470 freq[50]=618 freq[51]=562 freq[52]=606 freq[53]=612 freq[54]=562 freq[55]=556
freq[56]=618 freq[57]=568 freq[58]=606 freq[59]=618 freq[60]=568 freq[61]=606 freq[62]=606
total valid nonce number:57456
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:0
err_nonce_num:34998
last_nonce_num:0
get nonces on chain[6]
require nonce number:912
require validnonce number:57456
freq[00]=600 freq[01]=650 freq[02]=650 freq[03]=618 freq[04]=650 freq[05]=650 freq[06]=625 freq[07]=650
freq[08]=650 freq[09]=650 freq[10]=650 freq[11]=650 freq[12]=587 freq[13]=650 freq[14]=650 freq[15]=650
freq[16]=650 freq[17]=575 freq[18]=650 freq[19]=568 freq[20]=650 freq[21]=650 freq[22]=637 freq[23]=650
freq[24]=650 freq[25]=650 freq[26]=618 freq[27]=650 freq[28]=650 freq[29]=637 freq[30]=650 freq[31]=650
freq[32]=650 freq[33]=650 freq[34]=650 freq[35]=625 freq[36]=650 freq[37]=631 freq[38]=650 freq[39]=643
freq[40]=650 freq[41]=650 freq[42]=650 freq[43]=650 freq[44]=650 freq[45]=650 freq[46]=650 freq[47]=643
freq[48]=618 freq[49]=650 freq[50]=650 freq[51]=650 freq[52]=631 freq[53]=650 freq[54]=650 freq[55]=650
freq[56]=650 freq[57]=650 freq[58]=568 freq[59]=650 freq[60]=568 freq[61]=650 freq[62]=650
total valid nonce number:57456
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:0
err_nonce_num:39562
last_nonce_num:0
get nonces on chain[7]
require nonce number:912
require validnonce number:57456
freq[00]=575 freq[01]=656 freq[02]=625 freq[03]=575 freq[04]=656 freq[05]=656 freq[06]=575 freq[07]=656
freq[08]=656 freq[09]=581 freq[10]=656 freq[11]=656 freq[12]=593 freq[13]=656 freq[14]=656 freq[15]=656
freq[16]=656 freq[17]=650 freq[18]=656 freq[19]=650 freq[20]=656 freq[21]=656 freq[22]=656 freq[23]=537
freq[24]=656 freq[25]=656 freq[26]=581 freq[27]=656 freq[28]=656 freq[29]=650 freq[30]=656 freq[31]=550
freq[32]=656 freq[33]=631 freq[34]=656 freq[35]=656 freq[36]=656 freq[37]=537 freq[38]=656 freq[39]=656
freq[40]=643 freq[41]=656 freq[42]=656 freq[43]=643 freq[44]=562 freq[45]=656 freq[46]=656 freq[47]=650
freq[48]=656 freq[49]=656 freq[50]=656 freq[51]=656 freq[52]=568 freq[53]=656 freq[54]=631 freq[55]=625
freq[56]=656 freq[57]=656 freq[58]=556 freq[59]=656 freq[60]=575 freq[61]=656 freq[62]=656
total valid nonce number:57456
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:0
err_nonce_num:39372
last_nonce_num:57
Test Patten on chain[5]: OK!
Test Patten on chain[6]: OK!
Test Patten on chain[7]: OK!
disable_pic_dac on chain[5]
disable_pic_dac on chain[6]
disable_pic_dac on chain[7]
waiting for send_func to exit of chain[0]
waiting for send_func to exit of chain[1]
waiting for send_func to exit of chain[2]
waiting for send_func to exit of chain[3]
waiting for send_func to exit of chain[4]
waiting for send_func to exit of chain[5]
waiting for send_func to exit of chain[6]
waiting for send_func to exit of chain[7]
waiting for send_func to exit of chain[8]
waiting for send_func to exit of chain[9]
waiting for send_func to exit of chain[10]
waiting for send_func to exit of chain[11]
waiting for send_func to exit of chain[12]
waiting for send_func to exit of chain[13]
waiting for send_func to exit of chain[14]
waiting for send_func to exit of chain[15]
waiting for receive_func to exit!
waiting for pic heart to exit!
Start bmminer ...
miner total rate=13203GH/s fixed rate=13000GH/s
read PIC voltage=870 on chain[5]
Chain:5 chipnum=63
Chain[J6] voltage added=0.1V
OK: Chain[J6] is for this machine! [minerMAC: 00:13:f0:a4:b2:1b]
Chain:5 temp offset=-70
Chain:5 base freq=470
Asic[ 0]:470
Asic[ 1]:568 Asic[ 2]:606 Asic[ 3]:470 Asic[ 4]:575 Asic[ 5]:606 Asic[ 6]:481 Asic[ 7]:575 Asic[ 8]:606
Asic[ 9]:500 Asic[10]:581 Asic[11]:606 Asic[12]:500 Asic[13]:581 Asic[14]:612 Asic[15]:537 Asic[16]:543
Asic[17]:504 Asic[18]:537 Asic[19]:593 Asic[20]:537 Asic[21]:537 Asic[22]:593 Asic[23]:537 Asic[24]:543
Asic[25]:600 Asic[26]:568 Asic[27]:543 Asic[28]:600 Asic[29]:543 Asic[30]:550 Asic[31]:543 Asic[32]:612
Asic[33]:543 Asic[34]:537 Asic[35]:612 Asic[36]:556 Asic[37]:587 Asic[38]:531 Asic[39]:556 Asic[40]:606
Asic[41]:550 Asic[42]:543 Asic[43]:550 Asic[44]:618 Asic[45]:556 Asic[46]:606 Asic[47]:537 Asic[48]:500
Asic[49]:470 Asic[50]:618 Asic[51]:562 Asic[52]:606 Asic[53]:612 Asic[54]:562 Asic[55]:556 Asic[56]:618
Asic[57]:568 Asic[58]:606 Asic[59]:618 Asic[60]:568 Asic[61]:606 Asic[62]:606
Chain:5 max freq=618
Chain:5 min freq=470
read PIC voltage=870 on chain[6]
Chain:6 chipnum=63
Chain[J7] voltage added=0.1V
OK: Chain[J7] is for this machine! [minerMAC: 00:13:f0:a4:b2:1b]
Chain:6 temp offset=-70
Chain:6 base freq=568
Asic[ 0]:600
Asic[ 1]:650 Asic[ 2]:650 Asic[ 3]:618 Asic[ 4]:650 Asic[ 5]:650 Asic[ 6]:625 Asic[ 7]:650 Asic[ 8]:650
Asic[ 9]:650 Asic[10]:650 Asic[11]:650 Asic[12]:587 Asic[13]:650 Asic[14]:650 Asic[15]:650 Asic[16]:650
Asic[17]:575 Asic[18]:650 Asic[19]:568 Asic[20]:650 Asic[21]:650 Asic[22]:637 Asic[23]:650 Asic[24]:650
Asic[25]:650 Asic[26]:618 Asic[27]:650 Asic[28]:650 Asic[29]:637 Asic[30]:650 Asic[31]:650 Asic[32]:650
Asic[33]:650 Asic[34]:650 Asic[35]:625 Asic[36]:650 Asic[37]:631 Asic[38]:650 Asic[39]:643 Asic[40]:650
Asic[41]:650 Asic[42]:650 Asic[43]:650 Asic[44]:650 Asic[45]:650 Asic[46]:650 Asic[47]:643 Asic[48]:618
Asic[49]:650 Asic[50]:650 Asic[51]:650 Asic[52]:631 Asic[53]:650 Asic[54]:650 Asic[55]:650 Asic[56]:650
Asic[57]:650 Asic[58]:568 Asic[59]:650 Asic[60]:568 Asic[61]:650 Asic[62]:650
Chain:6 max freq=650
Chain:6 min freq=568
read PIC voltage=870 on chain[7]
Chain:7 chipnum=63
Chain[J8] voltage added=0.1V
OK: Chain[J8] is for this machine! [minerMAC: 00:13:f0:a4:b2:1b]
Chain:7 temp offset=-70
Chain:7 base freq=537
Asic[ 0]:575
Asic[ 1]:656 Asic[ 2]:625 Asic[ 3]:575 Asic[ 4]:656 Asic[ 5]:656 Asic[ 6]:575 Asic[ 7]:656 Asic[ 8]:656
Asic[ 9]:581 Asic[10]:656 Asic[11]:656 Asic[12]:593 Asic[13]:656 Asic[14]:656 Asic[15]:656 Asic[16]:656
Asic[17]:650 Asic[18]:656 Asic[19]:650 Asic[20]:656 Asic[21]:656 Asic[22]:656 Asic[23]:537 Asic[24]:656
Asic[25]:656 Asic[26]:581 Asic[27]:656 Asic[28]:656 Asic[29]:650 Asic[30]:656 Asic[31]:550 Asic[32]:656
Asic[33]:631 Asic[34]:656 Asic[35]:656 Asic[36]:656 Asic[37]:537 Asic[38]:656 Asic[39]:656 Asic[40]:643
Asic[41]:656 Asic[42]:656 Asic[43]:643 Asic[44]:562 Asic[45]:656 Asic[46]:656 Asic[47]:650 Asic[48]:656
Asic[49]:656 Asic[50]:656 Asic[51]:656 Asic[52]:568 Asic[53]:656 Asic[54]:631 Asic[55]:625 Asic[56]:656
Asic[57]:656 Asic[58]:556 Asic[59]:656 Asic[60]:575 Asic[61]:656 Asic[62]:656
Chain:7 max freq=656
Chain:7 min freq=537
Miner fix freq ...
read PIC voltage=870 on chain[5]
Chain:5 chipnum=63
Chain[J6] voltage added=0.1V
OK: Chain[J6] is for this machine! [minerMAC: 00:13:f0:a4:b2:1b]
Chain:5 temp offset=-70
Chain:5 base freq=470
Asic[ 0]:470
Asic[ 1]:568 Asic[ 2]:606 Asic[ 3]:470 Asic[ 4]:575 Asic[ 5]:606 Asic[ 6]:481 Asic[ 7]:575 Asic[ 8]:606
Asic[ 9]:500 Asic[10]:581 Asic[11]:606 Asic[12]:500 Asic[13]:581 Asic[14]:612 Asic[15]:537 Asic[16]:543
Asic[17]:504 Asic[18]:537 Asic[19]:593 Asic[20]:537 Asic[21]:537 Asic[22]:593 Asic[23]:537 Asic[24]:543
Asic[25]:600 Asic[26]:568 Asic[27]:543 Asic[28]:600 Asic[29]:543 Asic[30]:550 Asic[31]:543 Asic[32]:612
Asic[33]:543 Asic[34]:537 Asic[35]:612 Asic[36]:556 Asic[37]:587 Asic[38]:531 Asic[39]:556 Asic[40]:606
Asic[41]:550 Asic[42]:543 Asic[43]:550 Asic[44]:618 Asic[45]:556 Asic[46]:606 Asic[47]:537 Asic[48]:500
Asic[49]:470 Asic[50]:618 Asic[51]:562 Asic[52]:606 Asic[53]:612 Asic[54]:562 Asic[55]:556 Asic[56]:618
Asic[57]:568 Asic[58]:606 Asic[59]:618 Asic[60]:568 Asic[61]:606 Asic[62]:606
Chain:5 max freq=618
Chain:5 min freq=470
read PIC voltage=870 on chain[6]
Chain:6 chipnum=63
Chain[J7] voltage added=0.1V
OK: Chain[J7] is for this machine! [minerMAC: 00:13:f0:a4:b2:1b]
Chain:6 temp offset=-70
Chain:6 base freq=568
Asic[ 0]:600
Asic[ 1]:631 Asic[ 2]:631 Asic[ 3]:618 Asic[ 4]:631 Asic[ 5]:631 Asic[ 6]:625 Asic[ 7]:631 Asic[ 8]:631
Asic[ 9]:631 Asic[10]:631 Asic[11]:631 Asic[12]:587 Asic[13]:631 Asic[14]:631 Asic[15]:631 Asic[16]:631
Asic[17]:575 Asic[18]:631 Asic[19]:568 Asic[20]:631 Asic[21]:631 Asic[22]:631 Asic[23]:631 Asic[24]:631
Asic[25]:631 Asic[26]:618 Asic[27]:631 Asic[28]:631 Asic[29]:631 Asic[30]:631 Asic[31]:631 Asic[32]:631
Asic[33]:631 Asic[34]:631 Asic[35]:625 Asic[36]:631 Asic[37]:631 Asic[38]:631 Asic[39]:631 Asic[40]:631
Asic[41]:631 Asic[42]:631 Asic[43]:631 Asic[44]:631 Asic[45]:631 Asic[46]:631 Asic[47]:631 Asic[48]:618
Asic[49]:631 Asic[50]:631 Asic[51]:631 Asic[52]:631 Asic[53]:631 Asic[54]:631 Asic[55]:631 Asic[56]:631
Asic[57]:631 Asic[58]:568 Asic[59]:631 Asic[60]:568 Asic[61]:631 Asic[62]:631
Chain:6 max freq=631
Chain:6 min freq=568
read PIC voltage=870 on chain[7]
Chain:7 chipnum=63
Chain[J8] voltage added=0.1V
OK: Chain[J8] is for this machine! [minerMAC: 00:13:f0:a4:b2:1b]
Chain:7 temp offset=-70
Chain:7 base freq=537
Asic[ 0]:575
Asic[ 1]:631 Asic[ 2]:625 Asic[ 3]:575 Asic[ 4]:631 Asic[ 5]:631 Asic[ 6]:575 Asic[ 7]:631 Asic[ 8]:631
Asic[ 9]:581 Asic[10]:631 Asic[11]:637 Asic[12]:593 Asic[13]:637 Asic[14]:637 Asic[15]:637 Asic[16]:637
Asic[17]:637 Asic[18]:637 Asic[19]:637 Asic[20]:637 Asic[21]:637 Asic[22]:637 Asic[23]:537 Asic[24]:637
Asic[25]:637 Asic[26]:581 Asic[27]:637 Asic[28]:637 Asic[29]:637 Asic[30]:637 Asic[31]:550 Asic[32]:637
Asic[33]:631 Asic[34]:637 Asic[35]:637 Asic[36]:637 Asic[37]:537 Asic[38]:637 Asic[39]:637 Asic[40]:637
Asic[41]:637 Asic[42]:637 Asic[43]:637 Asic[44]:562 Asic[45]:637 Asic[46]:637 Asic[47]:637 Asic[48]:637
Asic[49]:637 Asic[50]:637 Asic[51]:637 Asic[52]:568 Asic[53]:637 Asic[54]:631 Asic[55]:625 Asic[56]:637
Asic[57]:637 Asic[58]:556 Asic[59]:637 Asic[60]:575 Asic[61]:637 Asic[62]:637
Chain:7 max freq=637
Chain:7 min freq=537
max freq = 637
Chain[5] Chip[62] local Temp=71
Chain[5] Chip[62] middle Temp=87
Chain[6] Chip[62] local Temp=71
Chain[6] Chip[62] middle Temp=90
Chain[7] Chip[62] local Temp=72
Chain[7] Chip[62] middle Temp=90
FAN PWM: 45
Frankly, I think the performance checks are a good solution to the fact that due to 16nm process variations the chips and therefore boards have a 'butter zone' that can be substantially different from one wafer to another. It also leads to an idea of looking over a stock of miners then taking the best boards and putting them in 1 'Super' miner... Wonder what a single 3-board miner could hit if all boards can run at top speed? mebe say >16THs? So far after nearly 24hrs the miner works great :)
Title: Re: s9 batch 17 (and 16?) changes
Post by: HagssFIN on October 14, 2016, 07:22:33 PM
Is there a fixed hash rate which is achieved by the miner setting up different freqs per board? (best working settings per board)
Title: Re: s9 batch 17 (and 16?) changes
Post by: sidehack on October 14, 2016, 07:26:50 PM
Auto-tuning is a good idea, but only if it's an option and not a mandate. There should be manual control of everything, with an automatic everything as an optional setting.
Course, I think the same thing about cars and nobody pays attention to that either.
Title: Re: s9 batch 17 (and 16?) changes
Post by: QuintLeo on October 14, 2016, 08:27:03 PM
Just got a s9 batch-17 and... Bitmain has changed the firmware.
Looks like changing the frequency may be gone. There is no longer a GUI option to change it. On startup, the firmware goes through several checks per-board and sets the best freq and possibly Vcore as well per-board. When all is done, the boards report different frequencies. This could turn out to be rather -- interesting.
How Spondoolies-ish - though without the voltage adjust feature from the SP20....
Title: Re: s9 batch 17 (and 16?) changes
Post by: not.you on October 15, 2016, 01:53:47 PM
I have a miner with a problematic board (an earlier batch, like 3 or something) and I have to reboot it many times to get a decent hashrate from the problem hashboard. If the reboot process took a lot longer, that sounds like a pain in the ass. Unless this process actually guaranteed a good boot from that board. I am skeptical though.
Supposedly new firmwares are going to be available on the website for download soon so I would guess they will be releasing this kind of thing to buyers of earlier batches.
Title: Re: s9 batch 17 (and 16?) changes
Post by: philipma1957 on October 15, 2016, 02:03:26 PM
I have two older miners with older firmware.
I also have one spare controller with older firmware.
I am waiting on a hashboard and one more controller.
Title: Re: s9 batch 17 (and 16?) changes
Post by: NotFuzzyWarm on October 16, 2016, 04:41:01 PM
Looking through the Kernel Log raises some questions for me. For one, just how granular is the Auto-tuning that Bitmain introduced? The end of the log shows many new things... read PIC voltage=870 on chain[6]
Chain:6 chipnum=63
Chain[J7] voltage added=0.1V
OK: Chain[J7] is for this machine! [minerMAC: 00:13:f0:a4:b2:1b]
Chain:6 temp offset=-70
Chain:6 base freq=568
Asic[ 0]:600
Asic[ 1]:650 Asic[ 2]:650 Asic[ 3]:618 Asic[ 4]:650 Asic[ 5]:650 Asic[ 6]:625 Asic[ 7]:650 Asic[ 8]:650
Asic[ 9]:650 Asic[10]:650 Asic[11]:650 Asic[12]:587 Asic[13]:650 Asic[14]:650 Asic[15]:650 Asic[16]:650
Asic[17]:575 Asic[18]:650 Asic[19]:568 Asic[20]:650 Asic[21]:650 Asic[22]:637 Asic[23]:650 Asic[24]:650
Asic[25]:650 Asic[26]:618 Asic[27]:650 Asic[28]:650 Asic[29]:637 Asic[30]:650 Asic[31]:650 Asic[32]:650
Asic[33]:650 Asic[34]:650 Asic[35]:625 Asic[36]:650 Asic[37]:631 Asic[38]:650 Asic[39]:643 Asic[40]:650
Asic[41]:650 Asic[42]:650 Asic[43]:650 Asic[44]:650 Asic[45]:650 Asic[46]:650 Asic[47]:643 Asic[48]:618
Asic[49]:650 Asic[50]:650 Asic[51]:650 Asic[52]:631 Asic[53]:650 Asic[54]:650 Asic[55]:650 Asic[56]:650
Asic[57]:650 Asic[58]:568 Asic[59]:650 Asic[60]:568 Asic[61]:650 Asic[62]:650
Chain:6 max freq=650
Chain:6 min freq=568
read PIC voltage=870 on chain[7]
Chain:7 chipnum=63
Chain[J8] voltage added=0.1V
OK: Chain[J8] is for this machine! [minerMAC: 00:13:f0:a4:b2:1b]
Chain:7 temp offset=-70
Chain:7 base freq=537
Asic[ 0]:575
Asic[ 1]:656 Asic[ 2]:625 Asic[ 3]:575 Asic[ 4]:656 Asic[ 5]:656 Asic[ 6]:575 Asic[ 7]:656 Asic[ 8]:656
Asic[ 9]:581 Asic[10]:656 Asic[11]:656 Asic[12]:593 Asic[13]:656 Asic[14]:656 Asic[15]:656 Asic[16]:656
Asic[17]:650 Asic[18]:656 Asic[19]:650 Asic[20]:656 Asic[21]:656 Asic[22]:656 Asic[23]:537 Asic[24]:656
Asic[25]:656 Asic[26]:581 Asic[27]:656 Asic[28]:656 Asic[29]:650 Asic[30]:656 Asic[31]:550 Asic[32]:656
Asic[33]:631 Asic[34]:656 Asic[35]:656 Asic[36]:656 Asic[37]:537 Asic[38]:656 Asic[39]:656 Asic[40]:643
Asic[41]:656 Asic[42]:656 Asic[43]:643 Asic[44]:562 Asic[45]:656 Asic[46]:656 Asic[47]:650 Asic[48]:656
Asic[49]:656 Asic[50]:656 Asic[51]:656 Asic[52]:568 Asic[53]:656 Asic[54]:631 Asic[55]:625 Asic[56]:656
Asic[57]:656 Asic[58]:556 Asic[59]:656 Asic[60]:575 Asic[61]:656 Asic[62]:656
Chain:7 max freq=656
Chain:7 min freq=537
Along with the ASIC strings on the board running different frequencies, the gods forbid, is EACH ASIC's speed different as well?? Sure looks like it to me otherwise what's the point of recording per-chip speeds? Is it even possible to do that (different speed per-ASIC)? I'd think that it would raise hell with timing the data xfrs... If this is the case then the boards reported speed is the average of all speeds being used on the board.
Title: Re: s9 batch 17 (and 16?) changes
Post by: goxed on October 17, 2016, 05:28:55 PM
I received my Antminer S9 Batch 17 today. It takes almost 30 minutes to start mining. Meanwhile the fans are running loud and produce a weird harmonic, which is irritating at best. I was snooping around a bit by sshing into the miner. Looks like at bootup, the miner writes fresh config files and then runs a process called single-board-test then runs scores of test possibly to characterise the ASIC chips; which was the output being seen in the Kernel log. Finally bmminer is instantiated to start mining. /usr/bin/bmminer --version-file /usr/bin/compile_time --api-listen --default-config /config/bmminer.conf bmminer, first sets fan PWM to 100 then reduces it to 30. It's still plenty loud at 30. It would be good to be able to manually control the fan speed.
Title: Re: s9 batch 17 (and 16?) changes
Post by: goxed on October 17, 2016, 05:30:53 PM
Here's my Config.ini [Config]
Name=S9 HASH board
TestDir=/etc/config/minertest64/minertest64_
DataCount=912
PassCount1=912
PassCount2=912
PassCount3=912
Freq=600
Timeout=0
OpenCoreGap=50000
# about temperature
CheckTemp=0
# GetTempFrom 0: get from LM75A through IIC, 1: get from ASIC
GetTempFrom=1
TempSel=0
TempSensor1=62
TempSensor2=0
TempSensor3=0
TempSensor4=0
DefaultTempOffset=-70
StartSensor=62
StartTemp=0
#AsicInterval can only changed by developer
CoreNum=114
AsicNum=63
TestMode=0
CheckChain=1
Open_Core_Num1=4294967295
Open_Core_Num2=4294967295
Open_Core_Num3=4294967295
Open_Core_Num4=262143
#CommandMode 0:vil 1:fil
CommandMode=0
AsicType=1387
ValidNonce1=57456
ValidNonce2=57456
ValidNonce3=57456
#Pic
Pic_VOLTAGE=1
#Pic_VOLTAGE=0
IICPic=1
DAC=1
UseConfigVol=1
Voltage1=860
Voltage2=860
Voltage3=860
Voltage4=0
Voltage_e=10
final_voltage1=910
final_voltage2=910
final_voltage3=910
#Time
year=2016
month=5
date=18
hour=10
minute=36
second=12
freq_gap=0
UseFreqPIC=1
freq_e=0
freq_m=5
freq_a=0
freq_t=1000
force_freq=0 Here's part of what's being tested head minertest64_01.txt
midstate 54f4143b58a1aa726126f05a0e139cc77c8704b0f964492c5dedc72c4bf2c295 data 08fb04182215d0573d3c794d nonce 00c11e80
midstate 23070884132238d15b9965654e70f12d0bc65b2397bac907a2a32e6a717b457f data 08fb04182215d057e4e72139 nonce 00bb2f81
midstate 834c5dc6b512794da705ec87e6e623ef39c1445282f697f21cfe67300374f14f data 08fb04182215d0573ed12131 nonce 0030cc82
midstate c04f66c8f6cb80da6da15a65fad6fd6bb251634191e1ed07d9f9604fb01e3197 data 08fb04182215d05743cdd12a nonce 0017e383
midstate d317ad116e4d7785789605513bad64c3ee657b420a80d7c8d397a2504dacad14 data 08fb04182215d0578bd858c5 nonce 005d1e84
midstate 3088e2a0ed8b9e5d3d62426006f8cccac0701bdae371272ed2374d20d9332e81 data 08fb04182215d057b9c4274e nonce 006cb205
midstate d3c85b944335e3ac7eb3843a3dab00aa9ce0705104e70d421442a91aeecddb78 data 08fb04182215d057956835fe nonce 00b48806
midstate 1bcd4b9fd2780d76a527576d3eb70f55e3522321e33eaf811127798afad88a3e data 08fb04182215d05744ce32b4 nonce 00000b87
midstate 176bf295a43209b74174466e12832c5609fa3cb317618e7a1279416c6e5891d5 data 08fb04185915d05715033365 nonce 002a4f08
midstate 3c2777dc334efbe51cf9c6f772ff8fc6e8e1725186ef16ed184b9d68eb1768f9 data 08fb04185915d05719c73399 nonce 00b7a409
Title: Re: s9 batch 17 (and 16?) changes
Post by: goxed on October 17, 2016, 05:37:01 PM
Can someone please post their Config.ini It's in /etc/config directory of the miner.
You can ssh in to the miner user:root password:admin
TIA
Title: Re: s9 batch 17 (and 16?) changes
Post by: not.you on October 17, 2016, 06:37:11 PM
Considering how long this autotune stuff takes, it would make a lot more sense if you could do it once and then re-use the conf file it created. Ideally you should be able to choose to use manual settings or use the autotune file and if the autotune file doesn't exist then you hit a button to go through the process and generate one. It shouldn't need to do this every single time. It would also make sense if you could at least raise the fan speed higher than the autotune level.
Title: Re: s9 batch 17 (and 16?) changes
Post by: sidehack on October 17, 2016, 07:49:57 PM
I wonder how much it would freak out if you used an external PWM fan driver and piped through the tach line so it would still see the fan spinning?
Title: Re: s9 batch 17 (and 16?) changes
Post by: goxed on October 17, 2016, 09:18:15 PM
I wonder how much it would freak out if you used an external PWM fan driver and piped through the tach line so it would still see the fan spinning?
Yup, I am thinking of something like that. Right now I have noticed that the tuning process can complete with only one fan online, while the other is unplugged. But bmminer stops immediately after tuning completes, and puts out an error message, when it detects a single fan.
Title: Re: s9 batch 17 (and 16?) changes
Post by: NotFuzzyWarm on October 18, 2016, 12:50:31 AM
I wonder how much it would freak out if you used an external PWM fan driver and piped through the tach line so it would still see the fan spinning?
Yup, I am thinking of something like that. Right now I have noticed that the tuning process can complete with only one fan online, while the other is unplugged. But bmminer stops immediately after tuning completes, and puts out an error message, when it detects a single fan. Since other folks have mentioned the fan speeds change from time to time, my thought is that the firmware might be trying to maintain a specific 'best' chip temp to keep it stable. IF so...
Title: Re: s9 batch 17 (and 16?) changes
Post by: QuintLeo on October 18, 2016, 03:40:41 AM
Has anyone tried the "bypass the fan pwm control line to give constant 100%" trick?
Title: Re: s9 batch 17 (and 16?) changes
Post by: Xircom on October 18, 2016, 09:17:51 PM
According to Bitmain support, this firmware is for all S9`s. look at the description of the file: Antminer-S9-all-201610180851-autofreq-user.tar Be very careful updating your S9`s some of mine went mental in chip temp and I had to flash with older bios, something is very wrong with this bios. http://i68.tinypic.com/2ntcpbq.jpg
Title: Re: s9 batch 17 (and 16?) changes
Post by: Ninetoe on October 18, 2016, 09:36:37 PM
stupid as i am i did the firmware upgrade and this is all that happens now. PS: its been like this for hours, ive done a few reboots too, and factory reset etc. http://i63.tinypic.com/2ez1vh1.pngBooting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.10.31-ltsi-00003-gcf03eb9 (lzq@armdev01) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #81 SMP Mon Apr 25 11:20:36 CST 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 258048
free_area_init_node: node 0, pgdat 806e5cc0, node_mem_map 8072a000
Normal zone: 2016 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 258048 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @80f17000 s11200 r8192 d13376 u32768
pcpu-alloc: s11200 r8192 d13376 u32768 alloc=8*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 256032
Kernel command line: mem=1008M console=ttyS0,115200 root=/dev/mtdblock3 rw rootfstype=jffs2
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1008MB = 1008MB total
Memory: 1015844k/1015844k available, 16348k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xbf800000 - 0xff000000 (1016 MB)
lowmem : 0x80000000 - 0xbf000000 (1008 MB)
modules : 0x7f000000 - 0x80000000 ( 16 MB)
.text : 0x80008000 - 0x8065a930 (6475 kB)
.init : 0x8065b000 - 0x806adbc0 ( 331 kB)
.data : 0x806ae000 - 0x806e9990 ( 239 kB)
.bss : 0x806e9990 - 0x80729384 ( 255 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17687 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804ab220 - 0x804ab278
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1196.85 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 524288 B
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab <bio-0> at 0
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
Switching to clocksource timer0
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled for 1 cores
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 1984
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
denali-nand-dt ff900000.nand: Dump timing register values:acc_clks: 4, re_2_we: 20, re_2_re: 20
we_2_re: 12, addr_2_data: 14, rdwr_en_lo_cnt: 2
rdwr_en_hi_cnt: 2, cs_setup_cnt: 2
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
5 ofpart partitions found on MTD device denali-nand
Creating 5 MTD partitions on "denali-nand":
0x000000000000-0x000001000000 : "NAND Flash Boot Area 16MB"
0x000001000000-0x000002000000 : "NAND Flash Boot Area backup1 16MB"
0x000002000000-0x000003000000 : "NAND Flash Boot Area backup2 16MB"
0x000003000000-0x00000b000000 : "NAND Flash jffs2 Root Filesystem 128MB"
0x00000b000000-0x000010000000 : "NAND Flash jffs2 Root Filesystem 80MB"
dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=bf8dc000, irq=163)
stmmac_hw_init: 1000M
stmmac - user ID: 0x10, Synopsys ID: 0x37
Ring mode enabled
DMA HW capability register supported
Enhanced/Alternate descriptors
Enabled extended descriptors
RX Checksum Offload Engine supported (type 2)
TX Checksum insertion supported
Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 0007c0f1 at 0 IRQ POLL (stmmac-0:00) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
jffs2: Empty flash at 0x01397ea4 ends at 0x01398000
VFS: Mounted root (jffs2 filesystem) on device 31:3.
devtmpfs: mounted
Freeing unused kernel memory: 328K (8065b000 - 806ad000)
eth0: device MAC address 56:d9:6b:09:dc:23
init phy ok
PHY DMA init OK
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
In axi fpga driver!
Original value in RESET_MANAGER_BASE_ADDR + BRGMODRST_ADDR is 0x0
request_mem_region OK!
AXI fpga dev virtual address is 0xbf942000
*base_vir_addr = 0xc504
In fpga mem driver!
request_mem_region OK!
fpga mem virtual address is 0xc0000000
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
chain[0] has no freq in PIC! Will use default freq=600 and jump over...
chain[2] has no freq in PIC! Will use default freq=600 and jump over...
chain[3] has no freq in PIC! Will use default freq=600 and jump over...
set command mode to VIL
singleBoardTest: AsicType = 1387
singleBoardTest: asicNum = 64
singleBoardTest: real AsicNum = 63
--- check asic number
set_baud=1
The min freq=700
set real timeout 52, need sleep=379392
disable_pic_dac on chain[0] testDone[0]=1
disable_pic_dac on chain[2] testDone[2]=1
disable_pic_dac on chain[3] testDone[3]=1
search freq for 1 times, completed chain = 3, total chain num = 3
restart Miner chance num=2
waiting for send_func to exit of chain[0]
waiting for send_func to exit of chain[1]
waiting for send_func to exit of chain[2]
waiting for send_func to exit of chain[3]
waiting for send_func to exit of chain[4]
waiting for send_func to exit of chain[5]
waiting for send_func to exit of chain[6]
waiting for send_func to exit of chain[7]
waiting for send_func to exit of chain[8]
waiting for send_func to exit of chain[9]
waiting for send_func to exit of chain[10]
waiting for send_func to exit of chain[11]
waiting for send_func to exit of chain[12]
waiting for send_func to exit of chain[13]
waiting for send_func to exit of chain[14]
waiting for send_func to exit of chain[15]
waiting for receive_func to exit!
waiting for pic heart to exit!
Start bmminer ...
Chain[J1] has no freq in PIC, set default freq=600M
Chain[J1] has no core num in PIC
Chain[J3] has no freq in PIC, set default freq=600M
Chain[J3] has no core num in PIC
Chain[J4] has no freq in PIC, set default freq=600M
Chain[J4] has no core num in PIC
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
Miner fix freq ...
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
max freq = 600
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
do 12 8xPatten test for 1 times
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
use PIC voltage=897 on chain[0]
now set pic voltage=79 on chain[0]
use PIC voltage=897 on chain[2]
now set pic voltage=79 on chain[2]
use PIC voltage=897 on chain[3]
now set pic voltage=79 on chain[3]
enable_pic_dac on chain[0]
enable_pic_dac on chain[2]
enable_pic_dac on chain[3]
set command mode to VIL
doHeatBoard: AsicType = 1387
doHeatBoard: asicNum = 64
doHeatBoard: real AsicNum = 63
--- check asic number
check chain[0]: asicNum = 63
check chain[2]: asicNum = 63
check chain[3]: asicNum = 62
Error: The AsicNum=62 on chain[3]!
Set Freq of PIC for Test Patten on Chain[0]
Set Freq of PIC for Test Patten on Chain[2]
Set Freq of PIC for Test Patten on Chain[3]
set_baud=1
anyone got a older firmware file for s9 b9 ?
Title: Re: s9 batch 17 (and 16?) changes
Post by: NotFuzzyWarm on October 19, 2016, 01:05:33 AM
Ouch!!!!
One trick I learned after munging a s9 Frimware: Unplug the PCI power to the hash boards and power only the controller.
Power up, wait several min and see if the Bitmain GUI reports life (socket connection error goes away).
If no go, still only with controller power, press the reset button for ~ 10sec then release it. Wait several more min to see if it lives. If it is alive you should be able to set pools, etc even without the hash boards working.
If it comes back to life, power down, reconnect power to hash boards and pray everything works....
Title: Re: s9 batch 17 (and 16?) changes
Post by: mindtrip on October 19, 2016, 03:07:32 PM
So it would seem like upgrading to the latest FW on the website on old miners is not advisable right now is that the general agreement here?
Title: Re: s9 batch 17 (and 16?) changes
Post by: NotFuzzyWarm on October 19, 2016, 03:47:22 PM
So it would seem like upgrading to the latest FW on the website on old miners is not advisable right now is that the general agreement here?
Grant you so far we have few data points but -- correct. For the old miners, if the original/older firmware works then I say do not upgrade. Most of my miners except the B1 (changed to low voltage version) are running the firmware they shipped with. As for applying the new firmware to the batch-16/17 miners, I am going to wait a bit to see any problems other folks have before *maybe* upgrading.
Title: Re: s9 batch 17 (and 16?) changes
Post by: sidehack on October 19, 2016, 04:04:32 PM
I know most folks don't really take stuff apart, but can someone confirm whether or not the new-batch S9 boards have the U2 digital potentiometer populated? The ones I've looked at from older batches don't, and I haven't seen any adjustments in voltage during startup so I wonder if these aren't made for a fixed core voltage. The new ones look to be adjusting voltage on the fly, like S7 boards should have been capable of, so either they're doing something unexpected or that dpot should be on there.
Title: Re: s9 batch 17 (and 16?) changes
Post by: goxed on October 19, 2016, 06:06:57 PM
I know most folks don't really take stuff apart, but can someone confirm whether or not the new-batch S9 boards have the U2 digital potentiometer populated? The ones I've looked at from older batches don't, and I haven't seen any adjustments in voltage during startup so I wonder if these aren't made for a fixed core voltage. The new ones look to be adjusting voltage on the fly, like S7 boards should have been capable of, so either they're doing something unexpected or that dpot should be on there.
Can you send a pic of the board and the part, so that it's easy to locate U2. Thanks
Title: Re: s9 batch 17 (and 16?) changes
Post by: sidehack on October 19, 2016, 06:08:46 PM
Far as I can tell, the buck circuit is basically the same as the S7. U2 is the part replaced by a trimpot in the Cheap and Easy S7 Repair thread from a few months ago that has a bunch of pictures already.
Title: Re: s9 batch 17 (and 16?) changes
Post by: mindtrip on October 19, 2016, 06:10:35 PM
So it would seem like upgrading to the latest FW on the website on old miners is not advisable right now is that the general agreement here?
Grant you so far we have few data points but -- correct. For the old miners, if the original/older firmware works then I say do not upgrade. Most of my miners except the B1 (changed to low voltage version) are running the firmware they shipped with. As for applying the new firmware to the batch-16/17 miners, I am going to wait a bit to see any problems other folks have before *maybe* upgrading. Ok so ill wait till the kinks in this FW transition process are resolved, my miners are pretty happy with the last stable FW most operating happy at higher clock speeds and very stable in a controlled data center so I think ill skip this update as I dont need added headaches right now
Title: Re: s9 batch 17 (and 16?) changes
Post by: NotFuzzyWarm on October 19, 2016, 06:10:38 PM
I know most folks don't really take stuff apart, but can someone confirm whether or not the new-batch S9 boards have the U2 digital potentiometer populated? The ones I've looked at from older batches don't, and I haven't seen any adjustments in voltage during startup so I wonder if these aren't made for a fixed core voltage. The new ones look to be adjusting voltage on the fly, like S7 boards should have been capable of, so either they're doing something unexpected or that dpot should be on there.
With the miner & fans running you kind of see the area where the U2 pads are but I couldn't really tell 'cause the fans blur things... Maybe a well-timed flash could catch it. A snippet from the kernel logs shows they definitely are doing something to control Vcore on-the-fly. use PIC voltage=870 on chain[5]
now set pic voltage=125 on chain[5]
use PIC voltage=870 on chain[6]
now set pic voltage=125 on chain[6]
use PIC voltage=870 on chain[7]
now set pic voltage=125 on chain[7]
enable_pic_dac on chain[5]
enable_pic_dac on chain[6]
enable_pic_dac on chain[7]
set command mode to VIL
Title: Re: s9 batch 17 (and 16?) changes
Post by: goxed on October 19, 2016, 06:41:54 PM
https://onlinedisassembler.com/odaweb/HP7GAkIN
Title: Re: s9 > and Auto-tune issues
Post by: NotFuzzyWarm on October 19, 2016, 06:58:14 PM
https://onlinedisassembler.com/odaweb/HP7GAkIN
Very cool.... looking through the index I see lots of v adjustment code. Now question is: does the PIC talk directly to the Vreg or to a DPOT?
Title: Re: s9 batch 17 (and 16?) changes
Post by: SEGMining on October 19, 2016, 08:12:48 PM
stupid as i am i did the firmware upgrade and this is all that happens now. PS: its been like this for hours, ive done a few reboots too, and factory reset etc. http://i63.tinypic.com/2ez1vh1.pngBooting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.10.31-ltsi-00003-gcf03eb9 (lzq@armdev01) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #81 SMP Mon Apr 25 11:20:36 CST 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 258048
free_area_init_node: node 0, pgdat 806e5cc0, node_mem_map 8072a000
Normal zone: 2016 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 258048 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @80f17000 s11200 r8192 d13376 u32768
pcpu-alloc: s11200 r8192 d13376 u32768 alloc=8*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 256032
Kernel command line: mem=1008M console=ttyS0,115200 root=/dev/mtdblock3 rw rootfstype=jffs2
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1008MB = 1008MB total
Memory: 1015844k/1015844k available, 16348k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xbf800000 - 0xff000000 (1016 MB)
lowmem : 0x80000000 - 0xbf000000 (1008 MB)
modules : 0x7f000000 - 0x80000000 ( 16 MB)
.text : 0x80008000 - 0x8065a930 (6475 kB)
.init : 0x8065b000 - 0x806adbc0 ( 331 kB)
.data : 0x806ae000 - 0x806e9990 ( 239 kB)
.bss : 0x806e9990 - 0x80729384 ( 255 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17687 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804ab220 - 0x804ab278
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1196.85 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 524288 B
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab <bio-0> at 0
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
Switching to clocksource timer0
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled for 1 cores
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 1984
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
denali-nand-dt ff900000.nand: Dump timing register values:acc_clks: 4, re_2_we: 20, re_2_re: 20
we_2_re: 12, addr_2_data: 14, rdwr_en_lo_cnt: 2
rdwr_en_hi_cnt: 2, cs_setup_cnt: 2
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
5 ofpart partitions found on MTD device denali-nand
Creating 5 MTD partitions on "denali-nand":
0x000000000000-0x000001000000 : "NAND Flash Boot Area 16MB"
0x000001000000-0x000002000000 : "NAND Flash Boot Area backup1 16MB"
0x000002000000-0x000003000000 : "NAND Flash Boot Area backup2 16MB"
0x000003000000-0x00000b000000 : "NAND Flash jffs2 Root Filesystem 128MB"
0x00000b000000-0x000010000000 : "NAND Flash jffs2 Root Filesystem 80MB"
dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=bf8dc000, irq=163)
stmmac_hw_init: 1000M
stmmac - user ID: 0x10, Synopsys ID: 0x37
Ring mode enabled
DMA HW capability register supported
Enhanced/Alternate descriptors
Enabled extended descriptors
RX Checksum Offload Engine supported (type 2)
TX Checksum insertion supported
Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 0007c0f1 at 0 IRQ POLL (stmmac-0:00) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
jffs2: Empty flash at 0x01397ea4 ends at 0x01398000
VFS: Mounted root (jffs2 filesystem) on device 31:3.
devtmpfs: mounted
Freeing unused kernel memory: 328K (8065b000 - 806ad000)
eth0: device MAC address 56:d9:6b:09:dc:23
init phy ok
PHY DMA init OK
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
In axi fpga driver!
Original value in RESET_MANAGER_BASE_ADDR + BRGMODRST_ADDR is 0x0
request_mem_region OK!
AXI fpga dev virtual address is 0xbf942000
*base_vir_addr = 0xc504
In fpga mem driver!
request_mem_region OK!
fpga mem virtual address is 0xc0000000
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
chain[0] has no freq in PIC! Will use default freq=600 and jump over...
chain[2] has no freq in PIC! Will use default freq=600 and jump over...
chain[3] has no freq in PIC! Will use default freq=600 and jump over...
set command mode to VIL
singleBoardTest: AsicType = 1387
singleBoardTest: asicNum = 64
singleBoardTest: real AsicNum = 63
--- check asic number
set_baud=1
The min freq=700
set real timeout 52, need sleep=379392
disable_pic_dac on chain[0] testDone[0]=1
disable_pic_dac on chain[2] testDone[2]=1
disable_pic_dac on chain[3] testDone[3]=1
search freq for 1 times, completed chain = 3, total chain num = 3
restart Miner chance num=2
waiting for send_func to exit of chain[0]
waiting for send_func to exit of chain[1]
waiting for send_func to exit of chain[2]
waiting for send_func to exit of chain[3]
waiting for send_func to exit of chain[4]
waiting for send_func to exit of chain[5]
waiting for send_func to exit of chain[6]
waiting for send_func to exit of chain[7]
waiting for send_func to exit of chain[8]
waiting for send_func to exit of chain[9]
waiting for send_func to exit of chain[10]
waiting for send_func to exit of chain[11]
waiting for send_func to exit of chain[12]
waiting for send_func to exit of chain[13]
waiting for send_func to exit of chain[14]
waiting for send_func to exit of chain[15]
waiting for receive_func to exit!
waiting for pic heart to exit!
Start bmminer ...
Chain[J1] has no freq in PIC, set default freq=600M
Chain[J1] has no core num in PIC
Chain[J3] has no freq in PIC, set default freq=600M
Chain[J3] has no core num in PIC
Chain[J4] has no freq in PIC, set default freq=600M
Chain[J4] has no core num in PIC
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
Miner fix freq ...
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
max freq = 600
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
do 12 8xPatten test for 1 times
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
use PIC voltage=897 on chain[0]
now set pic voltage=79 on chain[0]
use PIC voltage=897 on chain[2]
now set pic voltage=79 on chain[2]
use PIC voltage=897 on chain[3]
now set pic voltage=79 on chain[3]
enable_pic_dac on chain[0]
enable_pic_dac on chain[2]
enable_pic_dac on chain[3]
set command mode to VIL
doHeatBoard: AsicType = 1387
doHeatBoard: asicNum = 64
doHeatBoard: real AsicNum = 63
--- check asic number
check chain[0]: asicNum = 63
check chain[2]: asicNum = 63
check chain[3]: asicNum = 62
Error: The AsicNum=62 on chain[3]!
Set Freq of PIC for Test Patten on Chain[0]
Set Freq of PIC for Test Patten on Chain[2]
Set Freq of PIC for Test Patten on Chain[3]
set_baud=1
anyone got a older firmware file for s9 b9 ? I didn't read the entire log, but we had a similar situation at our mine. I don't know if this will work for you, but it worked for us. Go into your upgrade settings and click the reset button. After we reset and rebooted, this problem went away.
Title: Re: s9 batch 17 (and 16?) changes
Post by: Ninetoe on October 19, 2016, 10:25:19 PM
a little update.
after 18 hours it started hashing with no intervention from me, but was showing all temps as 0 and fans going crazy, but hashrate seems ok.
hope bitmain can get back to me with a earlier firmware
Title: Re: s9 batch 17 (and 16?) changes
Post by: sidehack on October 19, 2016, 10:57:16 PM
I haven't really probed but based on behavior I would guess the micro toggles the main buck's enable line. This was not on the S7. I would also guess but I haven't confirmed that the buck might be hardwired for a particular voltage. The one I looked at today, two adjacent boards had two different voltages. Since it's someone else's machines I'm not willing to poke around on 'em to see what goes where and does what, but if the buck is the same as S7 (looks like it at a glance) the DPOT is left unpopulated. I'd be interested to know if that's the case on the new version. If any of y'all have a board shoot craps and open it up it'd be great to get some high-res pictures of the regulator portion of the board.
Title: Re: s9 batch 17 (and 16?) changes
Post by: NotFuzzyWarm on October 20, 2016, 01:14:41 AM
I haven't really probed but based on behavior I would guess the micro toggles the main buck's enable line. This was not on the S7. I would also guess but I haven't confirmed that the buck might be hardwired for a particular voltage. The one I looked at today, two adjacent boards had two different voltages. Since it's someone else's machines I'm not willing to poke around on 'em to see what goes where and does what, but if the buck is the same as S7 (looks like it at a glance) the DPOT is left unpopulated. I'd be interested to know if that's the case on the new version. If any of y'all have a board shoot craps and open it up it'd be great to get some high-res pictures of the regulator portion of the board.
Tell ya what, considering that if a board in my b17 miner goes wonky I'll see what Bitmain Warranty can do about it vs sending to China, I'll look tomorrrow. Reason is this post in the Official s9 thread https://bitcointalk.org/index.php?topic=1493601.msg16620404#msg16620404 Leads me to wonder if the PIC/MCU/whatever now has a direct link to the Vcore regulator... From what I can tell on older s9's the regulator is identical to an s7. Even have a nice set of pins that can probably be used to program the voltage like an s7. edit: Have you had a chance to look at disassembled s9 (batch 17?) code at https://onlinedisassembler.com/odaweb/HP7GAkIN ? Way out of my league to dig into but the index points to many many interesting bits I don't recall seeing before... Damn that brings back memories! I haven't dealt with assembly code since the mid-1970-s through maybe 1982. Motorola 6800, Z80 and a few others. Trying to cram functional work-with-the-world code into maybe 128k leaving 32k of changeable user memory if you were lucky... Good way to make someone feel real old there...
Title: Re: s9 batch 17 (and 16?) changes
Post by: NotFuzzyWarm on October 20, 2016, 01:24:44 AM
Anyone here know how to ssh into the s9 and grab a copy of the on-board (part of the ARM based SOC) flash firmware aka the Factory Reset image that the controller uses when mounting the working partition(s)? Sadly, working knowledge of any 'UX is not one of the many hats I wear ;)
For 1 it would make for a damn fine way to have a real backup vs just a settings file the 'backup' function does for us. For 1 I suppose the resulting file should be a directly usable xxxx.tar.gz file.
Title: Re: s9 batch 17 (and 16?) changes
Post by: NotFuzzyWarm on October 20, 2016, 09:04:42 PM
I haven't really probed but based on behavior I would guess the micro toggles the main buck's enable line. This was not on the S7. I would also guess but I haven't confirmed that the buck might be hardwired for a particular voltage. The one I looked at today, two adjacent boards had two different voltages. Since it's someone else's machines I'm not willing to poke around on 'em to see what goes where and does what, but if the buck is the same as S7 (looks like it at a glance) the DPOT is left unpopulated. I'd be interested to know if that's the case on the new version. If any of y'all have a board shoot craps and open it up it'd be great to get some high-res pictures of the regulator portion of the board.
Pics of s9 b17 Vcore regulator section: Font side At least this looks near pristine!. That same area on many/most of my older s9's sorta look um, like someone spit on it and it dried... (seriously, doubt that is it ;) more likely flux residue from bad cleaning). Nasty looking and highly unprofessional. https://i.imgur.com/ZuNti02.jpgBack side showing no U2 DPOT. Also R17 coming from a bus of some sort going to U2's pin-6 along with R101 and R102 are missing as well. 101-102 run between the DPOT and programming plug P1 pins 1 & 2 that was used for Sidehacks s7 undervolting mod. To me, bottom line is that the PIC has direct coms with the Vcore regulator which from a design point makes perfect sense. I mean, since many/most regulators have internal EPROM or flash to store safe startup values and are quite happy to talk to a micro-controller once the uC wakes up, why add another layer (the DPOT) to things? Have all s9's been like this? Guess I gotta dig up pics of the bad s9 boards I sent to Bitmain Warranty... https://i.imgur.com/2kJMTvS.jpgNow to wait for the miner to finish playing with itself and get back to work.... edit: And 15min later -- back to full speed :)
Title: Re: s9 batch 17 (and 16?) changes
Post by: not.you on October 20, 2016, 11:17:33 PM
Anyone here know how to ssh into the s9 and grab a copy of the on-board (part of the ARM based SOC) flash firmware aka the Factory Reset image that the controller uses when mounting the working partition(s)? Sadly, working knowledge of any 'UX is not one of the many hats I wear ;)
For 1 it would make for a damn fine way to have a real backup vs just a settings file the 'backup' function does for us. For 1 I suppose the resulting file should be a directly usable xxxx.tar.gz file.
If you are a windows person then winscp is an easy option to connect to the miner and transfer files.
Title: Re: s9 batch 17 (and 16?) changes
Post by: NotFuzzyWarm on October 21, 2016, 03:25:12 PM
I compared pics of a s9 b11 hash board to the b17 and the Vcore regulator sections look identical.
Title: Re: s9 batch 17 (and 16?) changes
Post by: Gnome504 on October 22, 2016, 10:39:46 PM
I can confirm it's both batch 16 and 17 that shipped with this auto-freq update.
Can someone please tell me if it is possible to flash to an older firmware version on batch 16 and 17 S9's, because the fan setting is not configurable any longer! Nor can you over/under clock...
Does anyone have a copy of the 600 and 650mhz older firmware versions and could you post it on a free download site, preferably one in English. There is another post on here where someone posted it on a polish download site but the codes do not work and I can not figure it out even with google translate.
Thank you!
Title: Re: s9 batch 17 (and 16?) changes
Post by: Eshendia on February 26, 2017, 10:01:28 PM
a little update.
after 18 hours it started hashing with no intervention from me, but was showing all temps as 0 and fans going crazy, but hashrate seems ok.
hope bitmain can get back to me with a earlier firmware
Did you solve the problem? I have the same code, and situation, please help
Title: Re: s9 > batch 17 and Auto-Tune
Post by: NotFuzzyWarm on March 15, 2017, 10:31:21 PM
Bumping this up due to a virulent STD (Serious Topic Deviation) has sprung up on the main Bitmain s9 thread re: Auto-tune and Bitmain disabling any 'Eco-mode" fiddling.
To be continued...
Title: Re: s9 batch > 17 changes and Auto-Tune Issues
Post by: NotFuzzyWarm on March 15, 2017, 10:51:21 PM
Steering here posted. Now to see if works....
For those late to the party, my humble opinion as to Why Bitmain has forced Auto-tune factory speed only. No chance to underclock if desired. Let's call that Eco-modes.
In short the reason is Bitmain being able to use all possible chips produced using the 16nm Fin FET process. As ALL makers of 16/14nm node chips know - including the likes of Intel and IBM - that node is very unforgiving. Last I saw reported was that current initially 'usable' chips yield is ~70% for more complex but physically more spread out GPU's CPU's, Network Fabric switches and such. Note the word initially. Users of 14/16nm CPU's and GPU cards are reporting far higher time related failures as in a couple months when it happens.
BTW: That 70% yield is only because CPU's and GPU's can be easily binned per their performance and priced accordingly. Great ones costing more $$, meh ones $. Bitmain also bins to some extent but have a far narrower range as to what is usable while meeting advertised power usage. Ergo, I'd put their chip yield around 50-60% at best. BitFury, BW.com, Canaan, and others chose to sacrifice power efff for more stable operation by using higher Vcore. Odds are Bitmain's T9 are the same - higher Vcore, screw lowest on the planet eff.
Point is, Bitmain can populate hash boards with different 'speed' chips, test/bin the boards for several 'speed-grades' then build miners that reach the +/- 10% advertised rate and be done with it. Their firmware sorts out as-sold Target total hash rate needed, tests each board to see what they can do, and then sets them to give target speed.
Summary to date done.STD info starts.
Downside is, they threw out the baby with the bathwater. They allow no changes to what the miner decides is Best.
From Bitmains POV I can understand their reasoning: To get better chip yield we need Auto-tune. It solves problem of a miner performing poorly if Optimum (for that particular miner) is changed. Given that in all probability most large farms will not be changing things until much later in the product life cycle. Makes sense. I also bet that later on we WILL see Eco-modes from Bitmain in Firmware updates to come...
Auto-tune and it's 'why' should have no bearing on under clocking/volting the miners (and in turn fan speed would drop as well) if a user wants to do that. The testing part of Auto-tune already gathers extensive data on each hash board and the chips on it. Give users the option of reducing hash rate/power and apply as an offset to the miner hash rate. Consult performance data to new target hash rate and apply. Retest if desired and tweak as needed. Done.
Should be easy-peasy with very very minimal coding... Full tilt Factory as Default, Eco for those who don't care.
Title: Re: s9 > batch 16 and Auto-Tune Issues
Post by: NotFuzzyWarm on March 16, 2017, 08:42:42 PM
Ja. And to those who say it's more work for Bitmain's coders so Bitmain won't do it: Um, they just changed from using the Xilinx SOC to using one from Altera - pretty safe bet that the hardware change required significant re-coding of at a minimum the FPGA portion of it. Since the Cyclone-V still uses the same ARM-9 CPU as the Xilinx SOC did at least that bit would be mostly the same.
Implementing Eco modes is nothing compared to that ;)
Title: Re: s9 > batch 16 and Auto-Tune Issues
Post by: Dibblah on March 21, 2017, 11:07:54 AM
Ja. And to those who say it's more work for Bitmain's coders so Bitmain won't do it: Um, they just changed from using the Xilinx SOC to using one from Altera - pretty safe bet that the hardware change required significant re-coding of at a minimum the FPGA portion of it. Since the Cyclone-V still uses the same ARM-9 CPU as the Xilinx SOC did at least that bit would be mostly the same.
Implementing Eco modes is nothing compared to that ;)
Maybe, but their target market is the "from new, stick it in a rack until it dies" people. They don't care about hobby miners too much, since that's not where their profit is (R4 excluded). I find it quite interesting that they don't in fact appear to do any per-chip or per-board even tuning per-boot - it's just making sure that each board is as-shipped from factory, setting the ASIC speeds and expected core count, then trying all the boards. There is no variance in the picked speeds at all, as far as I can see - it just validates that everything is within expected ranges. When you do a new 'apply settings', it does some additional checks, but again, none of these appear to change the hashrate significantly. Cheers, Allan.
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