Bitcoin Forum

I'm inspired by the Bitfountain BE and Klondike drawings for USB thumb-drive form factor ASIC devices.  I'm wondering if there has been any discussion of the same thing for FPGA that anyone can point me to.

If not, I'm hopeful that those with like interests and more knowledge about it than I can theorize or point to information on suitable FPGA chips which meet the power requirements?

What kind of chipset support might be needed to make the thing brick-resistant (or hopefully brick-proof) or operate at all for that matter (aside from the obvious USB support)?

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My interest along these lines is stirred in part by Kaminski's comments at the 2013 conference, but I could imagine applications for various other goals than mining Bitcoin.

for the most part, an fpga is used as a stepping stone towards an asic... you would be very hard pressed to find any kind of fpga the size of a thumb-drive that is able to get a small percentage of a normal avalon chip (288 MH/s) (or even one that you can put the chip into the fpga).... for the most part, you just don't see fpga boards that small.

Maybe not thumb drive small, but there are still some that are definitely in that range of size.

... now, if the FPGA on the board is 'large' enough to hash, and at what speed if it can, that i dont know.

just one example, Mojo board (http://embeddedmicro.com/)

I should probably have clarified that what interests me is the ability to hop between multiple hashing algorithms, including currently unknown or undeveloped ones.  Performance is nice of course, but a secondary goal.  Obviously ASIC is not suitable for such an effort though of course the would hammer the shit out of FPGA in an 'application specific' role.

As I understand things, there are a multitude of FPGA's of different capabilities.  Many devices have them, and I figure that most of them could be programmed for a lot of different duties.  Some hashing algorithms are designed to be inefficient on such devices of course.

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I'll doubly-up this post and thank ~tabbek for the link to the 'mojo' board.  It's interesting and along the lines of what I was thinking.  I did not expect a spartan-6 to be applicable (powered by USB current at least.)  It does give some info on the type of support which a spartan-class chip might require.  A chart I found indicate to me that some spartan-3 might be in range from a power consumption perspective, but my knowledge of the stuff is only barely sufficient to make some rough guesses about this.

Well Xilinx does offer a wee USB board using a Spartan-6 LX9 - http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm
but it looks like that won't hold a candle to the LX150 (as seen in the Lancelot, etc)

Spartan-6 Family Overview - http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf

Even if you're not going for speed, not sure how/if the hashing process would scale down.

and yeah - thanks for linking to the mojo, tabbek.  looks like a fun platform to learn with.

Usb provide a maximum of 500mA
An rolled core at 50mhz in a ep4ce22F17c6 (Cylone 4 with 22kLUT) (4 rounds of 32 hashers) require around 480mA, and provide 50k / 4round = 12,5 MH/s ....

And count ppwer lost in regulation for 1.2V ... that 's not interesting

Thx for the info.  Looks like by simplistic linear extrapolation one would be lucky to get 5 MH/s out of an available cyclone or spartan-6 powered by a USB.  In the ball-park of CPU mining (though much more efficient at least.)  ...For sha256...

This kind of order of magnitude estimation is all I really need at this point.

Another potentially interesting device would be one powered by PoE.  It might be convenient in some applications.