Bitcoin Forum

It would be nice for someone to join me in developing bitstreams for Kintex-7 FPGAs.

I have used the open-source FPGA code with the 7K325T-2 device on KC705 board and have programmed it to hash at 600MH/s (600MHz) with ~30% device logic usage using fpmaminer's code that uses almost all the DSP blocks on this FPGA. Please PM me if you want this bitstream / source code.
https://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/KC705_experimental

The board costs ~1700 USD + tax from Avnet and has support for external DDR3 RAM which could potentially hash scrypt, though it's a speculation at this moment. The board also comes with a full seat of ISE + Vivado locked to this FPGA.


The chip and Vccint VRM of this board heats up a fair bit at that clock speed, but if kept near an AC vent the device runs stable for many days.
 
Another user has suggested using VGA memory heatsink blocks on the VCCint VRM inductor. I will try this as soon as the heatsinks arrive.

 
The first order of business would be to instantiate another set of hashers so that we can get towards full device usage and monitor power consumption, and heating issues if any.  

This way we can try to reach ~1GH/s and more on a 28nm FPGA board with good availability.


If you fulfill any one of the following, and have some spare time at hand, it would be great if you could join me in this project.

a) Ownership of a Xilinx KC705 board. This is a decent FPGA board with a 7k325 -2 FPGA

b) Xilinx Vivado tool / ISE tool running

c) Fluency with HDL code.


Some leads to start from

https://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/Kintex7_160T_experimental

https://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/VHDL_StratixIV_OrphanedGland/sha256/rtl

http://www.xilinx.com/images/product-images/kc705-base-board.jpg

PS. I am located in SW USA.

Since the board comes with an ethernet port, DDR, FLASH, etc., the next part of the project would be to instantiate a small Microblaze CPU and load Linux off it and make this board a stand alone miner. 

This sounds like a fun project.

I will forward this to a few persons.

I am interested! Good luck

Thanks!

Please let me know if you need any info or help. Thanks

And when you'll get a miscompare you won't know whether the fail was in the hasher or in the CPU.

Simulate the HDL to verify no functional errors. If issues persist even after that, drop in chipscope to take a closer look.

Ha, ha! I like this! Eyeball check invalid hashes with chipscope. His design starts failing when air-conditioning is off. So debugging all this with AC off in TX/NM summer heat will be a fitting punishment for not architecting the fault-tolerance properly.

 ;D

KC705 is a great educational toy, really is. I have nothing against learning when no innocent living creatures are harmed.

The CPU will be in a different clock domain, in which all timing specs are met.

Doing bitcoin in FPGAs is pointless at this point. Believe me I did financial modeling for Altera Cyclone V and Stratix V, Xilinx Kintex-7, Achronix Speedster22i HD

1. Time it takes to optimize for new FPGA is some amount of work. Not off the shelf kind of thing.
2. You can't get any decent quantity of FPGAs for 4+ month from when you order.
3. While I can get FPGAs at a lowest price of anyone (quotes up to 100,000 units), cost is still $100-200MH
4. FPGAs are not designed to work that hard and you will almost always will run into thermal limit before you use all the logic.
5. With current difficulty and new ASICs around the corner you will get about $60/GH returned while spending $200/GH around day 80-90 and then your cost of power will be more than it makes.
Bottom line is it's too risky to continue to do bitcoing projects on FPGAs for profit.

 Other virtual currencies may be worth it.

Good luck on alter currencies, if you need cheap FPGA source let me know.

Fair. I was thinking more along the lines of running a testnet, but yes if you want to debug a real block hash failure... More power to you I guess. ;)

edit: testnet probably isn't the right term. I was referring to injecting a previously solved block so you know what the output should be for a given input.

That said, what you're talking about sounds like a problem you should be monitoring through static timing analysis if your design is functional at ambient.

Or use a better cooling solution.  ;D

I've been following your progress on the Open Source Fpga Miner thread, and I'm impressed (i've only got a DE0-Nano myself).

However, this is just not an economical proposition. Have you considered the Structured ASIC route? (I've been posting on the KNCMiner threads recently, if you want to take a look), I reckon this is the only short-term opportunity left to turn a profit here.

And scrypt, OK potential, but I think Jasinlee has the jump on you there http://www.litecoinfpga.com/

But best of luck. Kudos!

1. Time it takes to optimize for new FPGA is some amount of work. Not off the shelf kind of thing.
Ans. Agree, it's going to be a learning experience for me and several other interested members.

2. You can't get any decent quantity of FPGAs for 4+ month from when you order.
Ans. Not decided to start a business here yet, just trying to make good use of an already available off the shelf development board in quantities of around 1-10. If some investor is interested they are most welcome.

3. While I can get FPGAs at a lowest price of anyone (quotes up to 100,000 units), cost is still $100-200MH
Ans. I agree FPGA is not cost competitive with ASICs, but I do-not learn much about hardware by buying and installing an ASIC. I think this board allows me to try a lot of different approaches,
including  unique approaches such as using an instantiated FPGA based CPU that can run Linux and linking it to the hashing core for a stand-alone device.

4. FPGAs are not designed to work that hard and you will almost always will run into thermal limit before you use all the logic.
Ans. Not sure about that, I used to use SGI RASC blade, a coprocessor blade for SGI Altix servers, and regularly used designs with > 90% FPGA (V4-LX200) utilization.
 
5. With current difficulty and new ASICs around the corner you will get about $60/GH returned while spending $200/GH around day 80-90 and then your cost of power will be more than it makes.
Bottom line is it's too risky to continue to do bitcoing projects on FPGAs for profit.
Ans. Hopefully the output of open-source projects could be used to make crowd-sourced ASICs or it could be useful for academic use. Who knows. But thanks for your insights, appreciated.

 

Thanks!
Is Structured ASIC economical at this moment? What would be NRE costs for lets say 32nm ASICS?  

Unfortunately I don't know. But I've been following the KNCMiner saga. 28nm process, claimed standard cell custom ASIC, but with no history of same, only Altera HardCopy (on same process node).

It just struck me that with Avalon, BFL, ASICMiner (I presume) all going the std cell route (with all its issues of NRE, long lead time, risk of rework), there might be an opportunity for a quick entrant into the market using FPGA to ASIC conversion (HardCopy or whatever the Xilinx equivalent is). But while much cheaper NRE than full custom, its still a significant business proposition.

Anyway, its way past my bedtime, so I'll just leave you with that thought.

I had understood that it was not profitable FPGAs. As long as there is for a draft ASIC

Bump! Any more interest?