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65nm Chip Specifications

BFL SHA2 ASIC
Product specifications are subject to change without notice. No responsibility is assumed for the use of information herein
1. Table of Contents
1. Table of Contents
2. ASIC Overview
3. Pin Diagram / Description
4. Application Circuit / Functional Block Diagram
5. Electrical Spec
6. SPI Interface
7. Normal Operating Modes and Description
8. Test Modes
9. IC Package Mechanical Drawing
10. System Operational Flow Charts
11. Revision History
12. Appendix A
13. Appendix B
14. Appendix C




2. ASIC Overview
BFL SHA2 ASIC
 SHA-2 hardware (integrated circuit) Hash engine
 65nm Technology
 BGA 10mm x 10mm, 144 ball package - solder bumps arranged in a 12 x 12 array, with a 0.8mm ball pitch
 Each Hash engine is comprised of 64 Unrolled or Pipelined stages x 2 (BFL architecture)
 16 engines per chip
 All Hash engine operations / instructions / data are transmitted via a single SPI bus (4 pins) plus additional Done_In and Done_Out daisy chained interrupt pins
 SPI addresses 128 HASH machines (-- 3 bit chip address, 4 bit engine address, plus 8 bit register address and R/W bit for each Hash machine)
 Uses only 5 MPU I/O pins
 No glue logic required
 No device polling required – each “done” hash engine provides an unique vector address
 Double buffered registers can pre-load registers with new values while hash engine is processing previous register values BFL SHA2 ASIC
65nm Chip Specifications  Each hash engine is capable of running at typically 274M-Hash / sec, with a total chip combined hash rate of 4.2 G-hash / sec. 12.0 Watts  At the rate of 4.2 G-Hash / sec, the ASIC dissipates approx
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