Bitcoin Forum

Anybody heard of bitfury.org?  It seems like they're designing custom LX150 racks.  Saw them doing like >170GH/s on deepbit.
Google bitfury.org shows http : // mc.zimdoorcraft.tk with some pictures of their rack.

Never heard of it and man those things are stinking expensive.

Looks really sweet though!

$90,000 for 110GH/s = $1.22 / MH/s
The BFL singles are $599 for 832GH/s = $1.39 / MH/s
So the BFL singles give you a little more speed, but since they use older fpga types, the BitFury costs probably less electricity.
Nice product!

/edit
BFL mini rig, $15,295 for 25.2GH/s = $1.65 / MH/s

Wow - someone has out-eldentyrelled eldentyrell...

lol $1.22/GH I'll take 500!


No proof as of yet.

Sorry, early in the morning here, not yet fully awake :P
Edited and corrected.

They are getting 305 mh/s per spartan6

It is their unverified claim. (Unverified, but plausible, given they overvolt and overclock the Spartan 6...)

Submitted to HN: http://news.ycombinator.com/item?id=4006650

That's what I thought as well when I saw this...

And what I understand, they don't use a fully unrolled hashing core, they use multiple rolled cores.
Very interesting idea, an idea I also had but can't really test because I don't have the tools to try.

Rear:
http://mc.zimdoorcraft.tk/bf110img/rackreart.jpg
Rear 2:
http://mc.zimdoorcraft.tk/bf110img/rackrearb.jpg
Open:
http://mc.zimdoorcraft.tk/bf110img/rackopen.jpg
Front:
http://mc.zimdoorcraft.tk/bf110img/rackfrontb.jpg
Motherboard:
http://mc.zimdoorcraft.tk/bf110img/mb.jpg
Power distr.:
http://mc.zimdoorcraft.tk/bf110img/powerdist.jpg
Power supply:
http://mc.zimdoorcraft.tk/bf110img/psubuild.jpg
Overview:
http://mc.zimdoorcraft.tk/bf110img/rackbuild.jpg

MAJOR FAIL! PLEASE ENROLL ON A MATHS COURSE!

$90000 per 110GHs means $0.81/Mhs (not $1.22)
$599 for 832Mhs means $0.72/Mhs (not $1.39)
$15295 for 25.2Ghs means $0.61/Mhs (not $1.65)

Butterfly is still by far the best.

I should stop posting when not fully wake up :S
But I don't think it is a major fail, I just calculated something else by accident :P

awesome design ;D

EDIT:

by review their design, i must say, they are real FPGA and arithmetic experts, well done.
with open mind too, they described their design method without reservation. i pay my tribute to them.

our new design is in very similar way, if we could solve the high-voltage-stabilized problem, we will share the method too.

 ;D

I just don't understand why someone would get this when they could get 4 mini-rigs for 30000 cheaper and half the power usage?

I am not knocking what they have done, it is truly impressive but is it really competitive?

1. No-one is getting it.
2. We see FPGA boards less competitive than BFL still being sold.

Holy epic shiet, this is an awesome setup.

EDIT: I'm pretty sure someone has this in their profile pic...

http://bitfury.org/bitstream/shafull.jpg

I would say yes and here are some reasons.

First.
As pointed out yet nobody has got one yet.  Nobody has also gotten a mini-rig yet either.  Lets see the delivered iron operating in the real world.

Second.
It would take 4.4 BFL Mini Rigs to equal 110 GH/s.  That would cost ~$67K and use 5.5 KW of electricity.  This system (as stated) is $90K and uses 7KW direct.  I didn't add in cooling costs because 5.5KW of mini rigs will require AC for most locations.  So it is ~$23K more and 1.5KW higher electricity.  Granted the BFL comes out ahead but who knows with volume or revisions they may be able to close the gap.

Third.
They were able to acheive 147GH/s by overclocking.  While one may not want to risk the entire rig doing that I could see overclocking say 20% of the array to get some reliability testing over the course of 6 months or so.   Maybe overclock only in winter (when watercooled setup w/ radiator place outside can suystain lower core temps).    If 147GH/s can be kept stable (granted a huge if) it would require 5.8 mini-rigs to equal the performance which would consume nearly 8 KW (plus AC load) and cost $90K.

Fourth.  
Who knows if BFL will be able to deliver (and when) on the mini-rig.  It is possible power consumption will be higher, or output will be lower.  Maybe they will hit on all specs but there is at least the chance they won't.  Hypothetically say they miss by 10% on power and 15% of performance.  That means 6.8 mini rigs costing $105K consuming 9KW (plus AC load)

Lastly (and the big one for me).  
The design is very good.  None of this slap an extra fan on the bottom and hope that keeps it cool.  It shows a very methodical approach.  That same skill set can apply to 28nm FPGA when they start hitting the market in volume coming 2013.  Imagine a 200 GH/s per rack system for roughly the same amount of power and cost. :)

That was eldentyrell with his own FPGA configuration :P

No, his was 3 distinct colors for each of the unrolled hashers.

Nice chilled water setup to keep those cores cool. This is the shit I'd like to do, if I knew how to program for FPGAs. I have the cooling experience but lack that critical skill  ;D

RS485 bus. I had same idea months ago... I need to quit job...

For those of you that were trying to figure out the network overhead, here is some good info:


Also, those copper busses look like exactly what I need for my rig. I'll have to study the pics a bit more.

This thread is boring, it's just speculation on a very uncompetitive product.

Although the parts may not be very modern, the ideas and things surrounding it are very relevant and fun to discuss. Theoretically if designed correctly, it should be possible to replace all the little FPGA modules with 28nm models when those come along, or even specially designed ASICs.

Indeed, specialise in heating/cooling systems like that, make the FPGA/ASIC's modules, well, modular, publish specs, get me on the board of directors, lol. You got yourself a killer niche here.

I actually want to buy myself a few of those rigs minus FPGA modules.

28nm is still very far away.

on the -7 series the routing resource is far different form spartan6, so this design can not be simply transplant to -7 series, but this architecture is still useful.

Any word yet if the low end -7 series will have metal heatspreader.  I would imagine you could get 20 to 30 Mhz more out of the Spartans if it like trying to pull that heat through the low conductivity plastic package.

Someone's being a little extra pissy this morning. I didn't see the sticky indicating that no FPGAs could be discussed unless it beats the BFL offerings.

I wouldn't say this is uncompetitive at all. If they built it for US$90K and it gets 110GH/s, it's the cheapest of the LX150 options. The power consumption is pretty high, but I'd be interested to see the actual breakdown. 110GH/s÷360 = 305MH/s, and they claim their 300MH/s bitstream consumes 12W which seems reasonable compared to other LX150s. For 360 FPGAs, that's 4.32kW. The remainder at 2.7kW seems a little high for the microcontroller backplanes, Atom boards and inefficiencies in the power supplies.

As for the price, it's moot since they haven't sold any at that price as far as anyone here knows. For that matter, BFL isn't selling their minirigs either. At this point they're just taking people's money as an interest free loan for an indeterminate amount of time.

The woman, my first love had a tattoo of a butterfly a bit like this, so I am attracted to anything to do with butterflies and because of this, Butterfly Labs have won my heart as soon as I heard about them.

http://i254.photobucket.com/albums/hh89/dan_2285/300_291033.jpg

Did she also have an ass like that?

No, Enterpoint's cairnsmore1 pre-order prices are cheaper. It will do at the very least 800 Mh/s with an average-performing bitstream (more likely 850 Mh/s) at $640. This is 1.25 Mh/s/$ (more likely 1.33 Mh/s/$). BitFury is more expensive at 1.22 Mh/s/$.

I guess one could say BitFury is cheaper on a technicality: Cairnsmore1 has not shipped yet.

The Cairnsmore are cheaper, but that's a time limited special offer (at least according to them). At the regular price of US$1280, they'd be more expensive.

by our review, not only heat. :)
some thing other limit break out when we solved over-heat.

How were you solving the overheat? Liquid nitrogen? ;D

On their website, they state:
Then after choosing serial round design it was very challenging to fit it exactly into 240 slices (8 x 32 area). As you see in snapshot image on the left, magenta color shows exactly two SHA256 rounds location. These double-SHA256 with round and round expanders and additional control logic fits into 240 slices. This took another month of development. Fitting in 240 slices was important to obtain good fill of XC6SLX150 right part.

I hate to break the news, but 8 x 32 is not 240. It is 256. At least, where I grew up.  ::)

So, what did they really do? Fit two rounds of SHA-256 into 240 slices, including control logic? I find that hard to believe.
Or fit two rounds of SHA-256 into 256 slices - I find that slightly easier to believe, but it still would be a major achievement.

i believe because we did just exactly the same.  2X 64cycle SHA256 core in 8X32 area, include control logic,  timing report is much over 300MHz.
the coding work is easy(maybe less than 50 lines.) but write the UCF files used month of time, and still have some small bugs now.  :)

at present no comment, but
much easier than you think...  ;D

My point was, that 8 x 32 is not 240. It is 256.
If you can fit this in only 240 slices, then maybe 16 x 15 is a better geometry, since 16 x 15 really is 240.
Or am I missing the point here?

42? (i have nothing useful to say... sorry.)

Could it be related to the fact that a Bitcoin hash only needs 61 rounds instead of 64?

No. Completely unrelated.

A guy or gal named Valery just responded to a personal email of mine with the clarification that they are indeed talking about 8 x 30 slices,
the same number a count on their screen shot comes up with.
In other words, 8 x 32 was a typo, which they have corrected on their website by now.

I find it amusing people are comparing a non released product to something that is already operating and outputting real world numbers.

i think it's really not important to a accurate number. our cores are using 256 slices. but only 64 clocks.


by special optimization on the arithmetic and setup pre-processors (certainly, inside the FPGA), it can reduce 3-4 calculate rounds.


i think it's very close to us.

Hey, at least I get to share with zhoutong the dubious honor of having had my name verbified by the forum users.  I guess that's something! ;)


Just guessing, but he probably daisy-chains the hashers in each clock region, runs them one step out-of-phase with each other, and has a single bram feed them k-values which get passed along from one hasher to the next, bucket-brigade style.  My very first design -- which was bit-serial (really bad idea!) -- worked that way.


The DNA register is just a shift register; it's trivial to swap it out for an SRL32 in fpga_editor.

By the way, these guys (http://dl.acm.org/citation.cfm?id=1344729) have documented the bitstream format and made tools that turn .bit files back into .ncd files -- even (completely illegible) .v files in some cases.


I don't think Xilinx wants the liability that comes with being a certificate authority -- especially one whose certificates can't be revoked because they're burned into millions of dollars worth of silicon.  You can bootstrap similar schemes yourself on Virtex-6 and above; see section 6 of this paper (http://dl.acm.org/citation.cfm?id=1950432).


I wouldn't trust them if I were you.  It's completely trivial (http://eprint.iacr.org/2011/390) to extract the AES key from Xilinx devices, even Spartan-6 (http://eprint.iacr.org/2011/391.pdf).  Even battery-backed ram.  Only one power-on is required, and the equipment isn't expensive (if you rent it it's downright cheap).  They didn't fix this problem until Virtex-6.


Quite prescient of you -- stay tuned.  But I'm not sure how well this would work for you -- with a highly-rolled design it's easy for an attacker to tell the difference between countermeasure circuits and the actual hashers -- just look for the pattern and chop out anything irregular.  Once you've got it down to a few hundred slices it's easy to figure out where the inputs and outputs are and what they mean. Replicate that block, stitch it back together and the game's over.

On the other hand, you guys make your own hardware -- that's a big advantage when it comes to anti-piracy measures.  You might be better off looking into ways to leverage that, like a tamper-proof housing around the spartan that erases the bitstream if breached and extra circuits to thwart power-analysis attacks.  People are also less likely to try to reverse engineer your work if they have to take apart and possibly damage a box they've paid $100,000 for!

So eldentyrell eldentyrell'ed existing Spartan 6 bitstreams, then bitfury eldentyrell'ed eldentyrell, and now BFL is trying to eldentyrell bitfury.

I simply don't have enough popcorn for this.

ok, yea... that got some laughs out of me, d3.

I don't think these announcements in close succession are a coincidence.

Seeing that EldenTyrell is planning to sell his 260 MH/s bitstream starting June 1st, Bitfury tried to preempt these sales by disclosing their own 300 MH/s bitstream, which has a better price/performance ratio than BFL's Single, at about half the power draw. Of course, BFL doesn't want Single sales to drop off by 95%, hence they pre-announce their ASIC, and thus ensure that sales of Lancelot, Bitfury and Eldentyrell's bitstream will be zero or close to zero. But such a pre-announcement of a better product can have a devastating side effect on your OWN product sales as well, which has bankrupted more than a few companies. For the baby boomers among us, let me just mention Osborne. Enter the buy-back guarantee. The buy-back guarantee ensures that BFL's sales will be unaffected by the pre-announcement - nobody will cancel existing orders and nobody will shy away from new orders.

Brilliantly played, BFL.

Yeah except DMC could very well be the largest buyer of miner hardware, and if I don't like what BFL now is doing, I won't buy their hardware in the future no matter how cheap it is, and would do business with Bitfury and Eldentyrell instead (who, really, should be combining forces right about now).

Bring it on :D

the only osbourne i know is norman (aka the green goblin), and a google for "osbourne company, -ozzy, -kelly, -sharon" fails to return anything. care to link?

also, BFL's pay up front policy was always a genius (if somewhat controversial) way to ensure enough bankroll to ramp up production while guarding against competition.

http://en.wikipedia.org/wiki/Osborne_Computer_Corporation

interesting read, thanks

CONFIRM. Exactly how this is done... Why to install multiple K RAM, if you can install only few one per whole chip ? ;-)


I've thought that it is different to convert .bit to .ncd .... But as you given me following links it seems to be trivial...


-1 for Xilinx... it means that their bitstream non-disclosure protection basically make burden on normal developers, but not defies hackers / ip thieves, because they would have time and money to invest into reverse-engineering tools.


Just downloaded it... But if .bit -> .ncd could be converted - it will be not difficult to decode keys from chip. OR - EXTREMELY complex self-modifying bitstream should be made for protection alone... So costs would be not justified for this SHA256 thing protection alone... I've implemented some time ago meta-translators for x86 code protection, generating morphed code & executable difficult for analysis, and with FPGA it would be even more complex.


So in -7 series they will make logic that consumes _same_ power not depending on their internal key, so correlation will not be possible ? Have they at least aware of such bug ?

[/quote]

I'll wait for your release, anyway you have my question in your thread.... And I may reconsider initial licensing offer, as I still have no binding on that of course. As I still have about 200 Gh/s power, and if it would become 240 Gh/s - that would be nice benefit. And it is substantial benefit, as I can get board for say

$700 without VAT with 6 spartan6 on it - if it would be 1.8 Gh/s this means $0.38 per Mh/s
if it would be 2.2 Gh/s this means $0.32 per Mh/s.

So looking again on these numbers and having troubles with protection of bitstream, all of these devices can be "on hold" in some datacenter say in Iceland in name of their owners, but without ability to get them in hardware or get access without our consent/permission to equipment until IP released open-source. And open-source release I believe should be done at least for educational purposes, when we'll be ready to roll out best 28nm technology. Say this could be beneficial for DMC initiative. Also _existing_ hashing power (200 GH/s) can be good backing that equipment would be actually deployed, as my investors trust me with this.

So the coupon for 1 Mh/s with say 1 year hardware redemption possibility if you get enough for single board + shipment can be sold for about $0.60 + cost of equipment maintenance, insurance, etc - that would be fair price. And seems to be more fair play than "perpetual bonds" without significant backing, where bond issuer can go defunct half the road etc.
And also looking @ GLBSE it seems to be very risky, I suppose that some legal framework needed for this, to protect rights of buyers. Just putting reputation against such venture would be not enough I think. As investing into mining not with 4-6 month break even point would scare off investors if they would feel that fighting for their rights could cost more and without returning their assets than invested funds.

One of the ways could be - implementing specialized legal-based framework for hashing power trading. For example domain names are sold - sold legally and without any problems... And people not worry owning domain name worth say $10'000'000 etc. The same should be with equipment probably for mining, as this could help dramatically to secure investments into IP alone. Into ASIC for example as well. As when it would come to invest say $5 M into ASIC production, and there will be right engineers to proceed - it would be still great problem that "good fellow who organized all of that" would not just take part of these money and run away.

Feel free to not disclose this, but what kind of volume are you going through that you're able to get a finished board with 6 LX150s on it for $700? I would have thought that even in large volume the S-6 LX150s would cost close to that.

No, in volume of 100s, a Spartan6-150 costs just barely more than $100. $110, $115, $120, something like that.

That's what I mean, $700/6 = $117. That doesn't leave a lot of room for the board, other components and assembly. I was wondering how many FPGAs he's going through.

I've already disclosed it, but I would not exactly tell that say Spartan has price $xxx because it is not the case with chip markets, as what basically cost there is not chip production, but NRE (R&D, masks, marketing etc) costs that Xilinx paid to make Spartan's rolling. And price for it will be falling with time.

But most important for Xilinx is not to make competition for their sales of Sparan's for other purpose - i.e. that will not buy it for $50 and sell for $100 to other contractors of them, who buy them at $100 level.

This is as ASIC vs FPGA design... FPGA is basically custom ASIC... do you think that its price is what silicon worth ? It's basically interest that FPGA vendor would like to get. I've told it already - that if FPGA vendor would like to - he can blow off with 28-nm say Virtex-7 sales for $50 that could be priced $10k on digikey any ASIC initiative here... And FPGA vendors more likely impose danger, as FPGAs are better suited for such calculations than say what GPU vendors manufacture...

This is what actually rises concerns about proof-of-work overall security. If you mention Scrypt - then - I can place about 4 to 6 hashers inside of Spartan and get blowing off speeds for that..... So it is even worse... As this makes edge for FPGA actually better than worse. As RAM accesses could be pipelined via multiple pipes............ getting bandwidthes that would not be available within usual computers/GPUs. Although I cannot parallelize single Scrypt, I can execute MULTIPLE calculations of different Scrypts - that's the point... Pipelining accesses to RAM...

What can really make benefits - is the both - modification of hashing algorithm and calculated hash, making ASICs obsolete, and highly-tuned FPGA modules, GPU modules and CPU modules more or less comparable. But that requires complex research indeed and probably not question of current day, and it should be performed by people not only who knows math in cryptography, but who also knows how hardware could be implemented etc. This not going to happen soon indeed as well.

And another weakness is ability to merge mining into pools... As this allows to manipulate hashing power against network...

Do want!

I must have missed this one.

Keep in mind that BFL has already lied once (https://bitcointalk.org/index.php?topic=66314.0) about whether or not their product was a custom ASIC, and they got caught (https://bitcointalk.org/index.php?topic=79825).  Then they simply deleted the ASIC claim from their FAQ.

You're on the right track there!  But buy-back guarantees aren't the only preannouncement/vaporware-proof sales strategy.  There's another one, and it's called….



I believe it's about to look slightly less brilliant.

Hrm, not too sure about that.  FPGAs are pretty easy to simulate in software… it just takes a really really really long time and runs really really really slowly.  But the attacker only has to do that once.  The root problem is that they don't need to be able to understand your design; they only need to be able to simulate the device it runs on and snoop the bits being written into the ICAP port.



I believe so.  I can't speak for Xilinx in particular, but I know a guy who had to design a decryption circuit with this property for some sort of wireless system.  There are lots of ways to do it; some of them aren't too hard.  The lazy way is to run your circuit through a transformation that turns every wire into two wires; on odd numbered clock cycles you drive both wires to zero and on even numbered clock cycles you pull high exactly one of the wires (the "left" one to represent logic-1 and the "right" one to represent logic-0).  So the power consumption is perfectly uniform: for each bit there is one wire worth of capacitance discharged on each odd-numbered cycle and one wire worth of capacitance charged on each even-numbered cycle.  Of course this makes your circuit 2-3 times larger and twice as slow, but for something tiny like an AES core it's no big deal.



Probably a good idea.  Here's one other reason I forgot: if you let people ship you boards that you didn't design, how do you know they don't have a microcontroller on there somewhere snooping the JTAG bus and capturing your decryption key as you send it to the device in cleartext?  If the snoop wire is on one of the inner planes of a 4-layer board and the microcontroller draws power from VCCAUX you'd never notice it.



I think there's a real market for that -- combined hardware and hosting sales.  You can also offer to ship them the hardware but tell them you're going to wipe the bitstream and encryption key off of it before you ship it out.



Definitely.

I really dislike being drawn into these discussions but in this case it's necessary to correct you.  BF Labs has never gone on record claiming it's previous generation processors are pure ASIC.  Never.  Forum members simply came to their own conclusions based on our FAQ (which did not say it was pure ASIC, just left it ambiguous).  Others read erroneous forum posts as fact and then repeated them as the lore of the day.   Now you're doing the same in hopes of undermining our reputation as you release your product.  There's no mystery here as to what's going on and I'm not so naive to think this post will stop it.  Carry on.

Ima puttin my mod hat on here.

Don't feed the trolls, even if the troll is your competitor and you're both making lots of money. Just don't do it.