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Hello All!

I've based some of my research on topic, basically used previous work of ngzhang
where he have identified chip: https://bitcointalk.org/index.php?topic=79825.0

Unfortunately I do not know exact speed grade of used devices.

In Quartus using my "prototype" code that I used for Hardcopy IV evaluation,
and other Stratix and Cyclone V devices (I would remember that for Cyclone V
it is possible to get 320 Mh/s performance per chip @ 160 Mhz @ 6 W approx).

The same code on EP3SL150F780C4 gave highest clock 220 Mhz, and on
EP3SL150F780C3 gave highest clock 250 Mhz. It is exactly unrolled round calculation.
And clock is based on "Slow 110mV 85C Model Fmax Summary" so if some overvolt
practice done it would run a bit (probably like 10%) faster.

Fitter report:

Fitter status: Successful - Sun Jul 01 10:22:07 2012
Quartis II 64-Bit Version: 11.1 Build 173 11/01/2011 SJ Full Version
Revision Name: ALAdder
Top-level Entity Name: sha_s4_test
Family: Stratix III
Device: EP3SL150F780C4
Logic utilization: 86%
  Combinational ALUTs: 86,417 / 113,600 (76%)
  Memory ALUTs: 0 / 56,800 (0%)
  Dedicated logic registers: 85,360 / 113,600 (75%)
Total registers: 85360
Total pins: 7/488 (1%)
Total block memory bits: 198,080 / 5,630,976 (4%)

As you see - one of improvements for Stratix / Cyclone design is to use RAMs...I use them with altsyncram primitive as
it gives me ability to implement shift registers with read_during_write_mode_mixed_ports => "DONT_CARE" mode, which
is important or otherwise memory will be slower (consider this as a HINT to BFL - to not use altshift_taps or automated synthesis of shift registers).

PowerPlay gives estimation of about 26214.26 mW and average toggle rate 249.704 millions transitions / sec (for 250 Mhz clock setup).

So what this means for BFL single device:

1) Without any overdriving practices device with C4 could deliver 220*4 = 880 Mh/s and with C3 250*4 = 1000 Mh/s
2) Power consumption would be (let's assume that PowerPlay lied and it is 30 W @ 250 Mhz @ 1.1 V) ~ 50W for C4 chip and 65 W for C3 chip;
3) in case of overdriving chip to 1.2 V C4 chip would deliver about 960 Mh/s and C3 chip about 1090 Mh/s, power consumption would be about 60 W and 76W correspondingly;

But because they already have about 80W power consumption, that leads me to conclusion, that C3 chip is used, but top-level logics and round maths is inferior and suboptimal.  As basically you could get _lower_ performance just by doing operations in wrong order.

I've already tried to contact BFL in PM - regarding my development and ASIC future deployments, but no answer. Maybe this topic would add some heat.

But I have few questions here:
1. What chip speed grade exactly there ?

2. What voltage is used there (this can be probably measured by many owners of BFL singles) ? Is it standard 1.1 V or something like 1.2 V ?

It would be nice, if BFL would do full disclosure here about their previous product art, as their ASIC initiative seems to make them obsolete already.

Also 2 BFL - if you use same top-level for your ASIC development, don't you think you may end up with product "obsolete-on-arrival" ? Because this is not "custom IC cell design", this is just math, and not complex part of it - as this "test sha_s4_test.vhd" is actually pretty small file mostly using RTL-style code and not using low-level primitives etc. I've run fitter and synthesis without optimization settings. But - if you can't deliver best in top-level optimization, why would I believe, that you would in low-level, where things are more complex and you'd likely have to do full-wave simulations of your custom cells, and still have several re-spins ? Or in layout - because layout could be done in a way by automatic tools, that will destroy all harvested performance. (2 DiabloD3 and those who think that custom IC is always that difficult - NO - I've studied more - if you don't try to harvest performance, and would do reliable cell and don't care about performance much, it is _likely_ that your cell would work, you may even implement cell that would work on different fabs... "portable" one but it would be quite inefficient... actually custom IC may be even cheaper - because basically it is just the same as PCB but on silicon, so if you do design in a way where you accept wide tolerance of your transistors - you get good manufacturability, good portability but poor performance... surprising, but tools for custom IC design without extensive modelling are actually cheaper - say for example www.tannereda.com - pretty nice tool to go from schematic to layout of chip - you even can get evaluation there for free and try to layout several transistors yourself, testing their performance in SPICE... that would be however likely far from specs you get from silicon... ).

I would be sorry, if you have worked on ASIC for quite long period and already have layout, because it seems that you'll have to re-do it if my estimations about your top-level is right.

Regards,
BitFury.

PS. 2 BFL fans - please do not turn BFL into religion :-) There's mining speculation subforum for exactly that purpose.

PPS. As you see _only_ 75% of chip is used... In extra space there could be fitted approx 2 times bigger serial hashers as addition, as design using automated placement would fit into 90% of a chip. Leaving about 10%. In these 10% it is possible to place about 8 serial hashers running at same or faster (LIKELY FASTER) clock. Each hasher outputting additional 3.5 Mh/s - so +25-28 Mh/s per chip and +50-56 Mh/s per BFL single. Setting best theoretical output as 1140 Mh/s per BFL single.

Well, this is a pretty thinly veiled piece of BFL-bashing.

Maybe he realized that there is no way to compete with BFL and wants to get a job there, by showing how 'smart' he is. Otherwise, he'd just make something better himself :)

Well. I don't need job with them, but I may sell to them solution of course. Right now they have more than enough money just to buy some know-hows about sha256. And looking at their hash-rates I clearly see that they need it :-)

As for Spartan solution - it is already fastest, and if yohan's prices for board combined with my bitstream price per Mh/s would be $0.53 / Mh/s for FPGA (1200 Mh/s for $640). This already beats BFL prices. If my licensing per-spartan would be applicable ($25 per chip) - then it would be 1200 Mh/s for $740 - $0.616 - again beats BFL. But - yohan prefers 840 Mh/s :-) While our capabilities do not allow to deploy quickly and cheap solutions.

For ASIC solution it is tougher - because this sets stakes higher. And I don't like to happen competing with phantom like it was with 20 W / 1050 Gh/s single... Trying like crazy getting 500 Mh/s from single Spartan :-) And then seeing that no magic was there, just some marketing fraud. I think they did it with this intention as well, to make others spending time trying to compete with the thing you can't :-) And then simply say "oops" - it is 80 W but not 20 W :-) Sorry - this is the thing that I won't forget :-) Quite happy that mini-rig was done differently. :-)

Well, it was cut to half to get it together.

Well. wrong point. To clarify it further - look @ transactions of BFL:

http://blockchain.info/address/1JuZT3sBomuzcFjQvVTLdXM97U6wCvazJR

Today there's 7'500 BTC is left (of total 112k BTC turnover).

I would gladly accept that 7'500 BTC and sell them know-how that would make their solution faster in range 10% to 20%.

This deal is effective for next 24 hours, otherwise terms may be reviewed.

What this makes ? they could deliver something in range 30 Th/s to 50 Th/s and could 35 Th/s to 55 Th/s. Effectively increasing gain for all their customers, and if they would wish for all buyers of mini-rigs and singles.

If they would wish - for their payment I could make full disclosure here (if they don't fear other developers for ASICs and FPGAs). But I won't do it on my own, as this is small edge from start over their tech. Of course that is not exclusive transfer of IP and not impose any condition that it won't be used in any other ASIC or FPGA solution. Exclusive deal will not be possible as I would embed into price for it potential revenues forecasting next 5 years, as it would quite crazy to compete with this solution.

Interesting post, but FPGA is already dead, based on the fact that people are canceling their FPGA orders and converting them to ASIC. 6 months ago this post would be much more interesting, when FPGA was in the headlines.

That address belongs to bit-pay, not to BFL, so, you can't say for sure if that payment was for them or not.
Also, the only transaction to that adress today was of 3.500 BTC, not 7.500 like you say.
Look at the first transaction that ever went to it, 1 year ago http://blockchain.info/tx-index/1018671/3f53678ae6f8d51f004705aae9dff75c62e924fe34fb26c04c869f861fade274

You don't seem as smart as you say you are, dude. ::)

I think the point was the huge spike in tx activity on 6/23 forward.  Plausible.

As for the last part.  Could you build the rack, cooling, PCB's and bitstreams they did?  No?  Ok, then.

But this is not about fpga, but about math in rounds (top-level vhd or verilog design RTL or primitives - that does not matter). So it applies to ASICs as well as to FPGAs... If they had it - would you think they would intentionally cripple their BFL single and mini-rig ?

What's plausible is that it's a Bit-pay consolidation adress. Just look at the exact sums that get sent to the address.
Bit-pay converts the USD price to BTC each time a payment is made, so those exact amounts are impossible. Also, they use a different address for each transaction.
What you're seeing there is one of bit-pay's cold storage addresses. Ofcourse some of those coins are from BFL sales, but that's not a BFL address.

With a desktop power supply powering my 6 singles and a Dreamplug, I get about 50 Watts per single at the wall.

It must be the default power adapter that eats up a whole 30 Watts to itself.

Thanks for report, but could you measure it with multimeter - voltage and current consumed by board ? That is really interesting. And possibly core voltage ?

Thanks again!!!

Agreed.  I don't know what bit-pay's volume is, but I can't imagine that the volume from 6/23 forward is coincidental.

IIUC, with EP3SL150F780C4/C3 the the clock rate (MHz) to hash rate (Mh/s) ratio seems to be the same (different power consumption).
Will the ratio be more than 1Mh/s per 1MHz with newer generation FPGA, or will they instead just have more MHz?
sorry, it seems I don't yet understand enough to ask the right questions...

Depends on architecture. For example for spartan sea-of-hashers - it is not. Mh/s is based on how many small cores inside placed. Fractional could be there.

Basically for example in Spartan - 61 clock cycles used for calculation 4 cycles used for loading of new job. 65 clock total. 82 cores. You get <clock> * 82 / 65 Mh/s hash rate.

For Altera solution I've put into chip that is 2 unrolled sha256, so output 2 * <clock> Mhz.

If you can do this, why not use the tricone model? Publish a bitstream for cairnsmore that extracts a commission and go straight to the end user. Every single person would use it. You could direct 200mh/s? to yourself and make your goal of $25/chip in no time. There are hundreds of these ready to go.

Do you own the hardware? If you don't have at least 2 of each for testing go shit in your hat.
Whats your products performance? NO SIMULATIONS either.

With tricone model unrolled round design is necessary, because otherwise it is near impossible to protect design. for me this means start another design from scratch for unrolled round. I already had ideas how to fit actually 2 full unrolled rounds there at clock 150-160 Mhz approx. (300 - 320 Mh/s). and little amount of small hashers (4-5) each giving 4 Mh/s approx. So total about 316 Mh/s to 340 Mh/s which is more than sea of hashers but also power envelope not 12 W but only 8W. This design would beat also Stratix approach with BFL mini-rig, as basically spartans would consume for 25 Gh/s about 820 W from plug compared to 1.25 kW of mini-rig. And will work on all boards as well. But this is due found solution with round expander which needs to wide buses with dual-clock design.

Plus another big part of work is testing for compatibility with every board around - I need these boards.

About question for hardware - about 655 spartans installed and mining using current bitstream (one full and one 5/6 filled rack).
So yes - verified in hardware of course, not in software. About BFL estimation - only simulations though, so it may fail due to power problems... but actually not likely, as these conditions are not putting chips to their edges at all, compared with 12 W on Spartan device.

thank you for the insight.

Jothan's numbers are incorrect (perhaps he is trying to subtract a baseline idle power consumption that is incorrectly measured, or his watt meter is defective, or his singles are throttling)... I measured power consumption with a clamp meter around the 12V input, and I get 66W per Single (rev 3 without the big 80mm fan an the bottom, the ones with the fan consume 68W), with an average 81W at the wall measured with a kill-a-watt, meaning the power adapters are 66/81 = 81% efficient.

And BFL seems to be using core voltage of 1.1V per the test points in the top right corner of their PCB: https://i.imgur.com/vrzol.jpg
I measured 1.13V with a multimeter on this 1.1V test point.

If I recall, don't you run your Spartan6s at higher voltages to achieve the MH/s that you are with your design? I imagine you'd hit the same problem that the tricone design is hitting with sagging voltages on boards that don't feed a slightly higher core voltage.

About board voltage - yes - 1.3 V, and 1.26 V on chip. We have board in production with separate power supplies and LVDS high precision clock supplied based on SI5338A external PLL. It may give superior performance to Spartan internal clock generators.

2 mrb: thanks for your input. 66 W per single means about 33 W per chip and including COP of system it is probably 26-28 W per chip (I expect 12 V -> 1.1 system should have COP about 80-85%).

so your bitstream it´s  300Mh/s? per Spartan Chip?  it would be 600Mh/s at Icarus?

Depends. Potentially yes. 12 W power per Spartan Chip. That power makes it difficult to use on many boards, for example with ZTEX boards.

You may look on our web site how many there capacitors below the chip (www.bitfury.org). On Icarus it maybe just 260-280 Mh/s, because it maybe wise to _lower_ voltage there to 1.15 V and decrease frequency accordingly. So it would run about 210 Mhz - 220 Mhz and consume about 9 - 9.5 W taking about 8 Amps power.

But exact combination of voltage and frequency should be determined based on power supply components and bypass capacitor calculations.

Licensing terms were written on this forum - basically $25 per spartan for low volumes and $20 per spartan for higher volumes. + Additional offer to scalp even more performance for $5 per spartan, if spartan volumes will be higher than 5000 total subscribing. Enterpoint shown no interest in this, as well as other board vendors except starting project - shalab.si

Maybe this happened because I wrote that these works will be open-source when spartans will be phased-out from generic mining rush. It seems to starting happening by the way. Depends on what will happen with ASICs.

Buy the board, program it, demonstrate your work, then people will believe and have buying interest, right now it's just promises without any backing :)

This is what I am doing. Just not boards, but producing 1-U servers with 48 spartan on boards. Soon first limited try-out will be sold, and I will inform everybody here as well.

About taking any board - if it would be piece of cake - like spending one day and done - I would do this. But actually only compilation takes 24 hours... Then it would take even more for adoption and debugging, multiply it per number of boards. Not knowing exactly volumes - means you would spent effort and it won't produce any fruit.

Also with pricing... such prices as $250 per spartan seems ridiculous. Like some vendors offer. I understand that as "dev board" for geeks to play it is nice offer, but as for mining - that is bad offer. Maybe this played a bit as well, as I disclosed how much it costs to build boards, etc. 1U will be more expensive though than initial setup of bitfury with rack ... more density ==> higher costs (say without active cooling it is unlikely that you would put more than 24 spartans in 1U).

What was the original hashrate BFL claimed when they were making a prototype of bitforc esingle? wasn't it like 1.5ghash or something at 40 watts?

1GH/s @ 20W.

I suspect you're bumping into the same reason their initial specs didn't match the delivered product: the power (and perhaps clock?) estimates out of these tools are wildly wrong because they don't account for the very high toggle rates.

Your numbers would have been more in line with what BFL originally claimed for the product but couldn't deliver.

^^^ This.

good news for you !!!

http://www.butterflylabs.com/wp-content/uploads/2012/06/IMG_3155.jpg

http://www.butterflylabs.com/wp-content/uploads/2012/06/IMG_3122.jpg

you can see here how many users they are on eclipse
https://eclipsemc.com/ (https://eclipsemc.com/)

Active Miners    1497
Current Speed:    1.73 TH/s

of course they are asic miner who mining !!!!

here the production line
http://www.butterflylabs.com/mini-rig-production-line/ (http://www.butterflylabs.com/mini-rig-production-line/)

You do realise those photos are from last June and those are the FPGA rigs, right?

bitfury might have a much better handle on how to simulate and get the correct numbers since he's taken his designs and actually put them onto silicon. While there could be something specific about the EP3SL150F780C4 that causes it to be so far out from simulations, it's probably pretty likely that if bitfury's simulations match his power draw for his own chips, they won't be that far off for modeling the same high level design on a different chip.

Still, why are we necroposting this? :)