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Title: Open source ASIC design plans in Hardware Description Language (HDL) format? Post by: Geremia on April 27, 2015, 02:15:41 PM Are there any freely-available ("open source") ASIC design plans in, e.g., HDL (https://en.wikipedia.org/wiki/Hardware_description_language) or AHDL (https://en.wikipedia.org/wiki/Hardware_description_language) format(s)? (cf. the related Bitcoin StackExchange question (https://bitcoin.stackexchange.com/q/37114/4334))
Title: Re: Open source ASIC design plans in Hardware Description Language (HDL) format? Post by: TheRealSteve on April 28, 2015, 06:07:37 AM Nope. There's several open source board designs, but no open source ASIC. Designing one for larger nodes isn't hard, you could easily do a hardcopy style from an FPGA design (that are available) - designing an efficient one is another matter of course :)
Title: Re: Open source ASIC design plans in Hardware Description Language (HDL) format? Post by: Geremia on April 28, 2015, 06:27:48 AM There's several open source board designs, but no open source ASIC. There's this (https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner), but, yes, technically FPGA ≠ ASIC.Title: Re: Open source ASIC design plans in Hardware Description Language (HDL) format? Post by: SpanishSoldier on April 28, 2015, 06:31:58 PM Are there any freely-available ("open source") ASIC design plans in, e.g., HDL (https://en.wikipedia.org/wiki/Hardware_description_language) or AHDL (https://en.wikipedia.org/wiki/Hardware_description_language) format(s)? (cf. the related Bitcoin StackExchange question (https://bitcoin.stackexchange.com/q/37114/4334)) There was a project regarding this: OpenBitASIC : The Open Source Bitcoin ASIC Initiative (https://bitcointalk.org/index.php?topic=76351.0) |