Bitcoin Forum

Bitcoin => Hardware => Topic started by: BitSyncom on October 24, 2012, 08:58:10 AM



Title: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on October 24, 2012, 08:58:10 AM
the purpose of this thread is to provide transparency and keep our existing and potential customers up-to-date whilst we work out some unforeseen website integration issues.


Quote
Hello everyone, my name is Yifu. Despise my fairly-lengthy involvement with Bitcoin, most of you do not know me. Rest assured however, I am no stranger to many in the Bitcoin community that is currently building/have built exciting business and/or systems. I must confess it has been my intention to stay away from the forums from the start as I enjoy being in the state of "doing" rather than in the acts of "blowing hot air". Alas, I do what I must.

I decided to look into ASICs awhile back because a simple and powerful reason: the lack of competition in Bitcoin mining dedicated hardware. Utilizing my well-traveled history, being multilingual and various skill sets is how I got involved with Avalon. Anyways, enough about me. Let's get to the good stuff.


before I begin you may wish to catch up on previous newsletters (http://us5.campaign-archive2.com/home/?u=238a9ecd2e5192e3cd3ace26d&id=9bf987f2aa) and a reddit AMA (http://www.reddit.com/r/Bitcoin/comments/10vmxa/avalon_asic_ama/) I conducted a few weeks ago.

http://store.avalon-asic.com | http://support.avalon-asic.com

Intro. Avalon launched with a challenge to our competitors: a over 50% dollar per GHash gain. Our competitors since then has also increased their specifications in order to stay competitive. Deviated from their original plan the competition managed to even the playing field, yet we simply proceeded with our original design goals and have reached 64Gh/s, and now 66Gh/s! Once again taking the lead in $/Ghash. While the competition promised early delivery dates but kept pushing them back. Avalon instead gave an very conservative estimate but now is scheduled to ship even earlier at Jan. 20th 2013.

Specification.
Code:
Chip Specification
Technology Summary:
    TSMC 0.11- micron G process
        5 Metal
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 256+ MHz
Number of Pads: 48
    8 Data
    40+1 Power
Package Type: QFN48 -0.5 Pitch
Packaged Chip Size: 7 mm x 7 mm

Chip Interface
Data Pins (8 in total):
Clock                     i
Serial Data In  [2]       i
Serial Data Out [2]       o
Serial Data Bypass [2]    o
Reserved    [1]    -

Avalon since inception has been designed to be an stand-alone unit, embed Linux openWRT equipped with WIFI capabilities and an Ethernet Port, while the competition is designed to operated over USB, depended on the need of a host computer. Continuing our trend, we have narrowed down our power estimates from 600W to 400W and this number is guaranteed to decrease further. Did I mention our power supply is a standard ATX?

The true genius of Avalon lies within its modular design. need a better PSU? No problem! Install your own. In fact, it is within our schedule to release the controller ( openWRT ) image.iso before the end of the year to give eager developers a head start to spin your own custom mining setups. Embrace open source!

Trade-Ins. Avalon believes in continuing the trust that have build up with our old customers. Reinstating our policy of $300 per Icarus, $400 per Lancelot, limited one FPGA trade-in per ASIC unit. The trade-in program will continue to be available and will apply to 1st-gen Avalons when the time comes.

Stress Testing. Avalon will not be testing these ASICs on the Bitcoin network period, whether it being the main-net, test-net, or even test-net-in-a-box. Why is that you may ask?

We will be testing these ASICs to do what exactly they are designed for, that is computing double-SHA256 hashes. this algorithm is not bitcoin exclusive at all. It is just so happens to be the block hashing algorithm, thus it would be silly to even set up a mining pool or use the bitcoin network in and form or way. We will be testing using our own custom software written to stress test our chips.

Shipping We at Avalon understands the some what unreliableness of EMS in certain countries, to address this issue, all existing and future orders will have the choice to be shipped out via DHL at no additional charge. This will ensure timely delivery of our products.

Inventory. Avalon learned from the mistake of our competitors and since conception has decided to release small order batches of 300 ( a number solely based on our estimated capacity) and only when a batch is close to finished, we will begin the sales of the next batch. When a new batch is announced, there will be another thread. In short, any units ordered so far, until further notice is part of batch #1, which is currently scheduled to ship at Jan 14th. In addition, as people fail to follow up with their orders, there are still some units left in the store, so if you missed your chance originally, now it's the time.

Facility Photos. Due to popular demand by the community, We have uploaded our facility photos. The full res album is at http://imgur.com/a/KPBTl
http://i.imgur.com/ntaUcs.jpghttp://i.imgur.com/DP17cs.jpghttp://i.imgur.com/UUPM4s.jpghttp://i.imgur.com/HxCqCs.jpg

Retail Pricing.
$1,299? Yep, to stay with the spirit of the competition. $1,299 for 66Gh/s.

question, comments and grievances welcome.


Title: Re: Avalon ASIC Development Status
Post by: BitSyncom on October 24, 2012, 09:10:48 AM
reserved.

Updating as promised,

Let's be frank. We ran into a potential delay of 4-7 days.

What does this mean?

We when taped out the chips to TSMC we had a "projected out date" of Jan 3, 2013 which is on schedule with our late dec. / early jan. demonstration dates. Now however after this week's website update our "projected out date" has changed to Jan 7th, 2013 and "committed date" has been revealed to be Jan 10th, 2013. TSMC did not give us a reason for this, but as a small customer you are really at the mercy of bigger customers running higher priority lots. e.g. "super hot lot"  The "committed date" is the promised date of delivery, it is very unusual for TSMC to break their "committed date", so we expect our chips to ship on or before Jan 10th, 2013.

Another potential problem is Customs clearing, the packaging company Fujitsu is located in Shanghai's Export Processing Zone (EPZ), while the packaging itself will not see delays, it may take an additional 2-3 days to clear Customs. To make up for this, if it occurs, we will be flying down to Shanghai to the demonstration in the EPZ instead of waiting for the shipping to the factory for assembly.

With all this happening, it has burned through the 1 week additional leeway time we originally left out. I must say it will be difficulty for us to ship on Jan 14th, we however expect to ship around Jan 18 ~ 20.


Since some people were wondering how many chips are on a wafer earlier in the thread after we posted the MT forms I'll tell you, each wafer contains 4055 chips.
Code:
TSMC
TMEM91
================================================
Chip Size :   X = 3.9760 ,Y = 4.0560 mm
Reticle Size :   X/cell =  3 ,Y/cell =  3
Offset Value :   X = -3.7668 ,Y = -2.2990 mm
Alignment Mark :   (118.80,83.20),(-118.80,-83.20)
Alignment Mark Tolerant Distance :      1.6 mm
Notch Reserved Distance :   7.75 mm
Start Distance :   7.75 mm
Ring Edge :   3.0 mm
Photo Die Number:    4055

and this is the chip layout.
http://i.imgur.com/0xYrks.jpg (http://i.imgur.com/0xYrk.jpg)


Title: Re: Avalon ASIC Development Status
Post by: eldentyrell on October 24, 2012, 09:26:58 AM
Packaged Chip Size: 7 mm x 7 mm

Thanks for the transparency, but the unpackaged die size is what you ought to be posting.  Without that it's impossible to make performance comparisons (or at least those comparisons would have to assume it fills the whole package cavity, which portrays Avalon in the worst possible light).  Please provide the unpackaged die size.

Also, I think you may have neglected to say how many of these chips are in the 60GH/s device… or perhaps I missed that.  Anyways, without knowing how many chips are in the device, none of the information above is really useful.  Did you post this somewhere that I didn't see?


Quote
Core Frequency: 256+ MHz

Interesting; an FO4 on TSMC 110nm is around 63ps, so at your 3.9ns cycle time (256mhz cycle rate) gives a datapath that is 62 FO4's deep.  Of course that doesn't mean there are 62 levels of logic!  Wire delays and clock skew (for chips that have clocks) come out of this budget too.


Title: Re: Avalon ASIC Development Status
Post by: ngzhang on October 24, 2012, 09:40:39 AM
reserved.


Title: Re: Avalon ASIC Development Status
Post by: PuertoLibre on October 24, 2012, 10:10:11 AM
 ;D :o 8)

Finally...

Sounds great that you guys are leveling up the GH/s race. So far I think only Tom from bASIC might compete on this race. I guess the three letter company will ship with the specs they have set to date (60Gh/s).

How many workhorse chips do you have in this rig?

------------------------

Also it was a very nice touch for you guys to use open source code AND a standard power supply. Sounds like you guys thrive on open-ended innovation. ;)


Title: Re: Avalon ASIC Development Status
Post by: Dexter770221 on October 24, 2012, 10:20:05 AM
Power consumption is quiet high :( If belives to BFL 6 times higher than their product.
There will be possibility to buy only chips? QFN package is simple to solder, and PCB design shouldn't be a problem. I have my own vision how rig should look like ;)
I think that you may have many clients like me...


Title: Re: Avalon ASIC Development Status
Post by: Tinua on October 24, 2012, 11:05:55 AM
What do you think about this?
Especially as regards the European market, with electricity costs between $ 0.10-0.30/kwh

Alright, one more scenario, more extreme:

Let's assume $12/BTC, $0.25/kwh power cost, and 1000 TH network hashrate after reward halving.

Hypothetical device that does 60 GH, costs $1300, and uses 60W:
$100K buys about 4600 GH of hardware which will use about 4.6kW of power and earn about $5980 per month, minus about $830 for power, for 5.15% monthly ROI.

Hypothetical device that does 54 GH, costs $1070, and uses 405W:
$100K buys about 5100 GH of hardware which will use about 38kW of power and earn about $6630 per month, minus about $6885 for power, for -0.26% monthly ROI. Uh oh.

Hypothetical device that does 54 GH, costs $1070, and uses 120W:
$100K buys about 5100 GH of hardware which will use about 11kW of power and earn about $6630 per month, minus about $2040 for power, for 4.59% monthly ROI.

But someone with $100K to invest, ought to find a better place to setup than where power costs $0.25/kwh.

And if ~5% monthly ROI were attractive to professional miners, why has mining been historically much more profitable than that, except when the exchange rate fell toward $2? I think 10-20% monthly ROI will continue for the next year or so at least. Though a price war among mining devices could really screw ROI up.
https://bitcointalk.org/index.php?topic=119744.msg1294453#msg1294453 (https://bitcointalk.org/index.php?topic=119744.msg1294453#msg1294453)


Title: Re: Avalon ASIC Development Status
Post by: BitSyncom on October 24, 2012, 11:41:05 AM
What do you think about this?
Especially as regards the European market, with electricity costs between $ 0.10-0.30/kwh

strictly speaking on power being the only variable I wouldn't even suggest to "mine-for-profit" basis with power rates higher than $0.10 ( and you are unable to get write offs or reductions. )

The real factor in the transition period of ASIC units will ultimately be delivery time, when difficulty is lower and the ROI is much higher.

Let's take this conservative example. using http://bitcoinx.com/profit/index.php

6 times the current difficulty
$.25 power cost.
400W
60GH/s

your break even time is 81 days, thats little over 2 month, of course assuming you can only maintain this ROI rate for 12 days or so, you would have effectively made 15% of your invest back.

with the current trend of everybody pushing their shipping date back I feel everybody has over estimated how quickly the difficulty will rise.

Let's assume Tom sold 1000 units, that's give or take 50TH/s,
Avalon only selling 300 units first batch, ~20TH.
BFL sells a crazy estimate of 2000 units, 120TH.

that barely adds up to 200THash, which is about 10 times the current network rate, and if difficulty goes up by a factor of ten using the same formula above. your ROI is 156 days.

honestly, it isn't that bad.

disclaimer: Avalon nor Yifu will be responsible for information provided here based an educated guess of future Bitcoin mining difficulty.


Title: Re: Avalon ASIC Development Status
Post by: benco on October 24, 2012, 12:52:39 PM

that barely adds up to 200THash, which is about 10 times the current network rate, and if difficulty goes up by a factor of ten using the same formula above. your ROI is 156 days.

honestly, it isn't that bad.

this would be true only in the case that the difficulty will remain unchanged for 5 months, and you know that it will not :)

real ROI will be, at best, somewhere at 8 months.



Title: Re: Avalon ASIC Development Status
Post by: thorvald on October 24, 2012, 02:45:51 PM

that barely adds up to 200THash, which is about 10 times the current network rate, and if difficulty goes up by a factor of ten using the same formula above. your ROI is 156 days.

honestly, it isn't that bad.

this would be true only in the case that the difficulty will remain unchanged for 5 months, and you know that it will not :)

real ROI will be, at best, somewhere at 8 months.



+1


Title: Re: Avalon ASIC Development Status
Post by: ice_chill on October 24, 2012, 03:20:28 PM
While the price and performance is great, 400watts vs 60watts is far from competitive. Also a laptop will consume at most 30watts when mining hardware is attached, so it's strange that your all in one unit needs so much more.

I see you mention the power consumption will drop, but it needs to drop a lot.


Title: Re: Avalon ASIC Development Status
Post by: crazyates on October 24, 2012, 03:38:25 PM
They've admitted to using a larger die size than their competitors. What else did you expect? The only consolation is being able to swap out to a more efficient PSU, and the fact that it doesn't need a host computer to run. Still, that GHs/1kUSD is nice for those of us with access to free electric.


Title: Re: Avalon ASIC Development Status
Post by: Bogart on October 24, 2012, 03:57:12 PM
They've admitted to using a larger die size than their competitors. What else did you expect? The only consolation is being able to swap out to a more efficient PSU, and the fact that it doesn't need a host computer to run. Still, that GHs/1kUSD is nice for those of us with access to free electric.

A larger size than bASIC's 90nm, but smaller than ASICMINER's 130nm.  I don't believe any other ASIC makers have disclosed their process node size.


Title: Re: Avalon ASIC Development Status
Post by: cablepair on October 24, 2012, 05:45:32 PM
Awesome Job Guys. :)

+1 and lots of respect to your team - Good luck with everything, I know your going to bring a really special and innovative product to the table.

If there is anything myself or anyone on my team can do for you please don't hesitate to reach out. We are are competitors but we still are friends :)

Good luck!

Tom
tom@btcfpga.com
(315) 514-0269




Title: Re: Avalon ASIC Development Status
Post by: ice_chill on October 24, 2012, 05:57:45 PM
Awesome Job Guys. :)

+1 and lots of respect to your team - Good luck with everything, I know your going to bring a really special and innovative product to the table.

If there is anything myself or anyone on my team can do for you please don't hesitate to reach out. We are are competitors but we still are friends :)

Good luck!

Tom
tom@btcfpga.com
(315) 514-0269




Easy to say that when you have a superior product, will see how well wishing you are to BFL :)


Title: Re: Avalon ASIC Development Status
Post by: flynn on October 24, 2012, 06:12:46 PM
Very interesting.

Amazingly small chips. Do you know yet how many of them will be on one board ?


Title: Re: Avalon ASIC Development Status
Post by: kaerf on October 24, 2012, 06:46:19 PM
Avalon since inception has been designed to be an stand-alone unit, embed Linux openWRT equipped with WIFI capabilities and an Ethernet Port, while the competition is designed to operated over USB, depended on the need of a host computer. Continuing our trend, we have narrowed down our power estimates from 600W to 400W and this number is guaranteed to decrease further. Did I mention our power supply is a standard ATX?

Will you eventually be selling a non-standalone version or will the unit come with the ability to disable the openWRT hardware? What are the power estimates for the non-mining (linux host) hardware?

With such high power usage, it seems you'd need to at least double the hash rate to be competitive from a pricing standpoint.

strictly speaking on power being the only variable I wouldn't even suggest to "mine-for-profit" basis with power rates higher than $0.10 ( and you are unable to get write offs or reductions. )

When designing your hardware, please don't assume that only people who can get power for <= $0.10 would like to "mine for profit". Power usage is a significant concern if your competitors are offering 60GH/s @ 60W. To be competitive (assuming similar hash rates and cost per device), you really need to have something less than ~200W (personally, I'd really only see it being competitive at <150W for similar hash rates).

that said, i'm happy there is competition in the marketplace and commend the avalon team on their efforts.


Title: Re: Avalon ASIC Development Status
Post by: ice_chill on October 24, 2012, 07:05:36 PM
Yes to above post, because when the difficulty increases far enough, it's the running costs that will determine the lifespan of the product.


Title: Re: Avalon ASIC Development Status
Post by: crazyates on October 24, 2012, 07:14:57 PM
Retail Pricing.
$1,299? Yep, to stay with the spirit of the competition. $1,299 for 66Gh/s.
Good news! Do you have any idea when the non-preorder, retail ordering will start?


Title: Re: Avalon ASIC Development Status
Post by: jjshabadoo on October 24, 2012, 07:29:40 PM
Hey Ice_chill,

Hard for Tom to be friendly with BFL when Josh trolls his thread mercilessly.



Title: Re: Avalon ASIC Development Status
Post by: Inaba on October 24, 2012, 10:40:27 PM
Hey Ice_chill,

Hard for Tom to be friendly with BFL when Josh trolls his thread mercilessly.



Except that, I only post in Tom's threads when he posts lies about myself or BFL.  So... it's not really trolling if it's responding to posts Tom has made.  If Tom doesn't want me to post in his threads, he should stop lying.  Nice try though.



Title: Re: Avalon ASIC Development Status
Post by: BitSyncom on October 24, 2012, 11:15:47 PM
With such high power usage, it seems you'd need to at least double the hash rate to be competitive from a pricing standpoint.

Run the numbers then speak to me again.

When designing your hardware, please don't assume that only people who can get power for <= $0.10 would like to "mine for profit". Power usage is a significant concern if your competitors are offering 60GH/s @ 60W.

That's not what I said, nor what we at Avalon did. I made a statement on long term mining as an investment, stating if you can not get access to cheap power, do not go into mining.

this would be true only in the case that the difficulty will remain unchanged for 5 months, and you know that it will not :)

real ROI will be, at best, somewhere at 8 months.

8 month based on what? I would much prefer if you have some numbers to back this claim up.

In addition, in case you missed my point. These numbers are made based on the assumption ASIC miners are mining at this 6x or 10x difficulty from day one, this will not happen at all. This is similar to saying the difficulty will raise 6x or 10x before any ASICs are delivered. which as you know, clearly is not the case.

In fact, by stating this 10x estimate, I am saying I predict within 6 month, the network speed will go up 10x, even when by the time all the ASICs become online, and difficulty goes up your ROI to start mining at 6 month later will be 156 days I gave out, which only means one thing, that your ROI will definitely be much less.

I have already gave a really conservative estimate on ROI, unless anybody can show me some other numbers that reach your conclusion of how Power Consumption matters a lot in ROI, I would be much appreciated if people do not speak with such prejudice about power consumption and spread FUD in this thread.

Thank you.

Good news! Do you have any idea when the non-preorder, retail ordering will start?

Very soon now, we still have more exciting news to release, and after we tackle a potential shipping delay around Chinese New Year. Once we mitigated this issue we can offer a better picture on when these will ship out. Unlike our competition, we will release much smaller batches every week or so, and they will ship out within the week. Meaning our customers will always receive their product quickly as possible and we do not get stuck with back orders which we have to fill.


Title: Re: Avalon ASIC Development Status
Post by: Inaba on October 24, 2012, 11:30:19 PM
The difficulty will be 10x within four weeks of the first ASICs that start shipping, be it BFL or Tom's offering.  After a month, most of the back orders of both companies will be well into consumers hands and the difficulty will rise.  6 months?  It will be a lot more than 10x by then.

Your ROI vs Power Consumption is based on your cost for power and if you're assuming cheap power to base your calculations on, I think you're doing a disservice to a lot of miners.  There's no reason to only mine if you have cheap power - you should buy power efficient devices. 

It's pretty irresponsible to even suggest that power doesn't matter, if for no other reason than the environmental impact.  It's a travesty when people mine with inefficient devices just because they aren't the ones having to pay for that power.  But someone, somewhere, is having to pay and it's costing the environment no matter who's paying the monetary bill. Everyone should be striving to have the most power efficient mining devices out there.


Title: Re: Avalon ASIC Development Status
Post by: Tinua on October 24, 2012, 11:48:12 PM
What do you think about this?
Especially as regards the European market, with electricity costs between $ 0.10-0.30/kwh

strictly speaking on power being the only variable I wouldn't even suggest to "mine-for-profit" basis with power rates higher than $0.10 ( and you are unable to get write offs or reductions. )

Sorry, but you know, in how many countries in the world the power rates is cheaper than $0.10, right?
In Europe I know none! This means, that you throw away in minimum the whole European market for  "mine-for-profit" or "long term mining as an investment" customers!


Title: Re: Avalon ASIC Development Status
Post by: PuertoLibre on October 24, 2012, 11:58:32 PM
The difficulty will be 10x within four weeks of the first ASICs that start shipping, be it BFL or Tom's offering.  After a month, most of the back orders of both companies will be well into consumers hands and the difficulty will rise.  6 months?  It will be a lot more than 10x by then.
Congrats, you just made a point that hurts the ASIC sales across the board.

If your words are taken literally, then the ASIC sellers are selling people very expensive lemons that will take a year or more to get their investment back....and then.....*barely any profit* per month.

Your ROI vs Power Consumption is based on your cost for power and if you're assuming cheap power to base your calculations on, I think you're doing a disservice to a lot of miners.  There's no reason to only mine if you have cheap power - you should buy power efficient devices.  

It's pretty irresponsible to even suggest that power doesn't matter, if for no other reason than the environmental impact.  It's a travesty when people mine with inefficient devices just because they aren't the ones having to pay for that power.  But someone, somewhere, is having to pay and it's costing the environment no matter who's paying the monetary bill. Everyone should be striving to have the most power efficient mining devices out there.
Tethered wattage means your device will consume anywhere from 60watts on up:

Not including a standard router wattage: 20watts~

If a laptop: 30 to 65 additional watts.

If a barebones desktop: Anywhere from 80 to 160 watts. (not including the monitor)

        If a fully loaded desktop with 1 or more GPU cards....I care not to speculate. (These are people of the "enthusiast" mining community!)


----------------------------

If we aren't getting very cheap DD-WRT routers in the box to offset the above tethered wattage, Your 60watt number is only for those whom aren't looking at the real numbers.

Without a very cheap low powered controller it is 60 + 20 + 30 = 110 watts. (Low powered laptop)

If a barebones desktop is employed (best case scenario): 60 + 20 + 85 = 165 watts. (not including an active monitor)

I care not to speculate on what a multi-GPU rig consumes.


Title: Re: Avalon ASIC Development Status
Post by: Gomeler on October 25, 2012, 12:05:06 AM
Any chance of decreasing the operating speed and core voltage to boost GH/w efficiency? I fear if BFL delivers on their 1 GH/w efficiency and nobody is close then they will be the only choice for those with a multiple year outlook on using these devices.


Title: Re: Avalon ASIC Development Status
Post by: gmaxwell on October 25, 2012, 12:09:54 AM
If your words are taken literally, then the ASIC sellers are selling people very expensive lemons that will take a year or more to get their investment back....and then.....*barely any profit* per month.
What kind of major business expenses pay themselves back— passively no less!— in just a year?   Perhaps 7%/wk is more to your liking? Those tastes are catered to in other parts of the forum.

There are major risks in mining— including the risk that all that fancy hardware could be worthless before it arrives due to a loss of interest in Bitcoin, security flaws, legal attacks, etc. Or things like breakthrough optimizations for SHA256^2 allowing massive speedups on equal process or someone somehow doing a major run a vastly better process... just to name a few.

Meanwhile y'all have been ordering devices without concrete specs (including BFL customers— a substantial amount of pre-ordering happened when they were saying nothing about power at all!) which makes concrete reasoning about returns impossible if uncertainty about the future difficulty and exchange rate hadn't already made it impossible.

And after that, you're worried about some months difference in payback timeframes for some estimates?  Suicidal.  I hope no one has put money into these asic preorders that they can't afford to lose.


Title: Re: Avalon ASIC Development Status
Post by: Tinua on October 25, 2012, 12:20:18 AM
If a barebones desktop is employed (best case scenario): 60 + 20 + 85 = 165 watts. (not including an active monitor)
--------------------------------------------------------------
Your 60watt number is only for those whom aren't looking at the real numbers.
why you calculate with a single mining device? why not .. with 5 or 10?

60 + 60 + 60 + 60 + 60 + 20 + 85 = 405 watts (not including an active monitor) (for 300Gh/s)
60 + 60 + 60 + 60 + 60 + 60 + 60 + 60 + 60 + 60 + 20 + 85 = 705 watt (not including an active monitor) (for 600Gh/s)

so, what do you mean with your statement above?  ???


Title: Re: Avalon ASIC Development Status
Post by: PuertoLibre on October 25, 2012, 12:24:03 AM
If your words are taken literally, then the ASIC sellers are selling people very expensive lemons that will take a year or more to get their investment back....and then.....*barely any profit* per month.
What kind of major business expenses pay themselves back— passively no less!— in just a year?   Perhaps 7%/wk is more to your liking? Those tastes are catered to in other parts of the forum.
I can't speak for anyone else, but I am looking for BTC rather than converting those BTC into $$$ directly. So that is not my operating strategy.

There are major risks in mining— including the risk that all that fancy hardware could be worthless before it arrives due to a loss of interest in Bitcoin, security flaws, legal attacks, etc. Or things like breakthrough optimizations for SHA256^2 allowing massive speedups on equal process or someone somehow doing a major run a vastly better process... just to name a few.

Meanwhile y'all have been ordering devices without concrete specs (including BFL customers— a substantial amount of pre-ordering happened when they were saying nothing about power at all!) which makes concrete reasoning about returns impossible if uncertainty about the future difficulty and exchange rate hadn't already made it impossible.

And after that, you're worried about some months difference in payback timeframes for some estimates?  Suicidal.  I hope no one has put money into these asic preorders that they can't afford to lose.
Perhaps there will be a manufacturing defect that will rear it's ugly head after customers have received their orders. Dunno.

Either way, it sounds like one way to stay profitable with mining hardware...is remote upgradability.

If the device cannot be upgraded with better cooling to achieve higher Gh/s then it is a bad option for the long term.



Title: Re: Avalon ASIC Development Status
Post by: PuertoLibre on October 25, 2012, 12:26:20 AM
If a barebones desktop is employed (best case scenario): 60 + 20 + 85 = 165 watts. (not including an active monitor)
--------------------------------------------------------------
Your 60watt number is only for those whom aren't looking at the real numbers.
why you calculate with a single mining device? why not .. with 5 or 10?

60 + 60 + 60 + 60 + 60 + 20 + 85 = 405 watts (not including an active monitor) (for 300Gh/s)
60 + 60 + 60 + 60 + 60 + 60 + 60 + 60 + 60 + 60 + 20 + 85 = 705 watt (not including an active monitor) (for 600Gh/s)

so, what do you mean with your statement above?  ???
It becomes more efficient with more than one mining device. But...there aren't that many miners out there who are investing 5 thousand or more dollars into their pre-orders.

You could cater to the niche crowd within the niche crowd though...using those numbers though!


Title: Re: Avalon ASIC Development Status
Post by: Tinua on October 25, 2012, 12:33:07 AM
................. But...there aren't that many miners out there who are investing 5 thousand or more dollars into their pre-orders.
Sure???
So, from where does the expected increase of the difficulty about 10x or 20x?


Title: Re: Avalon ASIC Development Status
Post by: PuertoLibre on October 25, 2012, 12:36:31 AM
................. But...there aren't that many miners out there who are investing 5 thousand or more dollars into their pre-orders.
Sure???
So, from where does the expected increase of the difficulty about 10x or 20x?
I am guessing from the collective volume.

Why don't you start a poll thread and ask people what they ordered and the quantity so we have an idea of whom is heavily invested in ASIC mining?


Title: Re: Avalon ASIC Development Status
Post by: Tinua on October 25, 2012, 12:46:44 AM
................. But...there aren't that many miners out there who are investing 5 thousand or more dollars into their pre-orders.
Sure???
So, from where does the expected increase of the difficulty about 10x or 20x?
I am guessing from the collective volume.

Why don't you start a poll thread and ask people what they ordered and the quantity so we have an idea of whom is heavily invested in ASIC mining?
You think one poll is representative? Think not! Furthermore, there is already a list of BFL-order. Perhaps 10% on it

And.......what no one considered so far: The energy prices will rise in the future in many countries, and will not stay on the same level!



Title: Re: Avalon ASIC Development Status
Post by: BitSyncom on October 25, 2012, 12:49:08 AM
The difficulty will be 10x within four weeks of the first ASICs that start shipping, be it BFL or Tom's offering.  After a month, most of the back orders of both companies will be well into consumers hands and the difficulty will rise.  6 months?  It will be a lot more than 10x by then.

How is this any different then? Avalon will be also shipping around that time, and we are bound to finish shipping before you simply due to our much lower volume, are you saying you(BFL) and Tom will ship 150+TH before we ship any of our Avalon units out? then I suppose I do not want to compare my oranges to your imaginary apples.

Either way, I'll be providing a ASIC web based comparison tool within the week and people will decide for themselves.


Title: Re: Avalon ASIC Development Status
Post by: Tinua on October 25, 2012, 12:54:01 AM
Either way, I'll be providing a ASIC web based comparison tool within the week and people will decide for themselves.
Sounds good!


Title: Re: Avalon ASIC Development Status
Post by: Inaba on October 25, 2012, 01:03:51 AM
The difficulty will be 10x within four weeks of the first ASICs that start shipping, be it BFL or Tom's offering.  After a month, most of the back orders of both companies will be well into consumers hands and the difficulty will rise.  6 months?  It will be a lot more than 10x by then.

How is this any different then? Avalon will be also shipping around that time, and we are bound to finish shipping before you simply due to our much lower volume, are you saying you(BFL) and Tom will ship 150+TH before we ship any of our Avalon units out? then I suppose I do not want to compare my oranges to your imaginary apples.

Either way, I'll be providing a ASIC web based comparison tool within the week and people will decide for themselves.

Forgive me if I am mistaken, but aren't you scheduled to ship in January?  Assuming Tom is on time (and there's no reason to think he isn't) between Tom and BFL, yes I expect 150 TH to be shipped by the end of January.  If you're shipping in December, then I retract my statement.  We should have our entire pre-order backlog cleared in January, assuming all goes according to plan. 

As far as the "barely any profit" per month goes, that only applies to devices with GH/w ratios.   The more efficient devices should remain profitable for a very long time.


Title: Re: Avalon ASIC Development Status
Post by: BitSyncom on October 25, 2012, 01:17:24 AM
Forgive me if I am mistaken, but aren't you scheduled to ship in January?  Assuming Tom is on time (and there's no reason to think he isn't) between Tom and BFL, yes I expect 150 TH to be shipped by the end of January.  If you're shipping in December, then I retract my statement.  We should have our entire pre-order backlog cleared in January, assuming all goes according to plan

As far as the "barely any profit" per month goes, that only applies to devices with GH/w ratios.   The more efficient devices should remain profitable for a very long time.


Sounds good.


Title: Re: Avalon ASIC Development Status
Post by: kaerf on October 25, 2012, 01:51:47 AM
Assuming bASIC and BFL ship around the start of December.

By the end of Decemeber, I expect bASIC to have shipped all units .
Quote from: cablepair
...it will require at least a 7 days of 8-10 hour days,

~800 * 54 = 43 TH/s (assuming bASIC performance stays at 54GH/s..it will most likely be higher)

BFL has more orders and more man power...let's be really conservative and say they ship 75GH/s in Dec.

thats 43 + 75 + 22 = 140 TH/S bare minimum

So that IS ~7X difficulty from day ONE for Avalon customers. I believe your "conservative" ramp up numbers are not conservative enough.

Regardless, I'd say a very "conservative" guess is that within 3 months of Avalon's release, difficulty will be over 10X (IMO, easily). Long terms calculations should begin a minimum of 10X.

Everyone has been saying time-to-ship is the most important factor...well I'd like to look slightly further out than 3 months. The most that I can conservatively plan for is 6-10 months. Who knows what the landscape will be like several months from now.

My outlook for the short-medium term is 10x-30x difficulty. All 3 major offerings will be profitable during this time...how profitable depends on power cost.

Since BFL has published (confident) power numbers...let's use them as a baseline.

Cost per day @ $0.10 @ 60W = $0.14
Cost per day @ $0.10 @ 100W = $0.29
Cost per day @ $0.10 @ 200W = $0.48
Cost per day @ $0.10 @ 400W = $0.96

Cost per day @ $0.25 @ 60W = $0.36
Cost per day @ $0.25 @ 100W = $0.60
Cost per day @ $0.25 @ 200W = $1.20
Cost per day @ $0.25 @ 400W = $2.40

25 BTC/block @ 30M difficulty @ $12 USD/BTC = $12.07 / day

Let's look at how much profit is effected by power

using 60W as baseline
Cost per day @ $0.10 @ 60W = baseline is 0% more profitable
Cost per day @ $0.10 @ 100W = baseline is 1.27% more profitable
Cost per day @ $0.10 @ 200W = baseline is 2.94% more profitable
Cost per day @ $0.10 @ 400W = baseline is 7.38% more profitable

Cost per day @ $0.25 @ 60W = baseline is 0% more profitable
Cost per day @ $0.25 @ 100W = baseline is 2.09% more profitable
Cost per day @ $0.25 @ 200W = baseline is 7.72% more profitable
Cost per day @ $0.25 @ 400W = baseline is 21.10% more profitable

Obviously, as difficulty goes up, profitability goes updown. As such, the affect of power usage on profitable also goes up.

Some people might say 5% is nothing...we tip pool operators that much. Others are trying to maximize every penny. Granted, Avalon now claims a 10% edge in hashing power (over BFL)...I am uncertain how long that edge will last. Both bASIC and BFL have stated that there is (perhaps significant) room for improvement here.


I have orders from each of the big 3, so I'm not trying to bash Avalon here. As a customer I just want a great product that will give me a decent bang for my buck.

BFL offers good hash rate with lower power.
bASIC offers good $/GH...still waiting for power numbers.
Avalon still has good $/GH (with bumped specs)....still waiting for power numbers.

I tried to diversify for the first run of ASICs, but if/when I decide to order more units...I'm looking for the best bang for the buck going forward.


Title: Re: Avalon ASIC Development Status
Post by: PuertoLibre on October 25, 2012, 01:54:01 AM
The difficulty will be 10x within four weeks of the first ASICs that start shipping, be it BFL or Tom's offering.  After a month, most of the back orders of both companies will be well into consumers hands and the difficulty will rise.  6 months?  It will be a lot more than 10x by then.
Congrats, you just made a point that hurts the ASIC sales across the board.

If your words are taken literally, then the ASIC sellers are selling people very expensive lemons that will take a year or more to get their investment back....and then.....*barely any profit* per month.





As far as the "barely any profit" per month goes, that only applies to devices with GH/w ratios.   The more efficient devices should remain profitable for a very long time.


You actually confirmed that....disturbing. Well I applaud your honesty on it at least...


Title: Re: Avalon ASIC Development Status
Post by: libertybuck on October 25, 2012, 02:01:27 AM
> if you can not get access to cheap power, do not go into mining.

严重支持!



Title: Re: Avalon ASIC Development Status
Post by: PuertoLibre on October 25, 2012, 02:03:55 AM
Assuming bASIC and BFL ship around the start of December.

By the end of Decemeber, I expect bASIC to have shipped all units .
Quote from: cablepair
...it will require at least a 7 days of 8-10 hour days,

~800 * 54 = 43 TH/s (assuming bASIC performance stays at 54GH/s..it will most likely be higher)

BFL has more orders and more man power...let's be really conservative and say they ship 75GH/s in Dec.

thats 43 + 75 + 22 = 140 TH/S bare minimum

So that IS ~7X difficulty from day ONE for Avalon customers. I believe your "conservative" ramp up numbers are not conservative enough.

Regardless, I'd say a very "conservative" guess is that within 3 months of Avalon's release, difficulty will be over 10X (IMO, easily). Long terms calculations should begin a minimum of 10X.

Everyone has been saying time-to-ship is the most important factor...well I'd like to look slightly further out than 3 months. The most that I can conservatively plan for is 6-10 months. Who knows what the landscape will be like several months from now.

My outlook for the short-medium term is 10x-30x difficulty. All 3 major offerings will be profitable during this time...how profitable depends on power cost.

Since BFL has published (confident) power numbers...let's use them as a baseline.

Cost per day @ $0.10 @ 60W = $0.14
Cost per day @ $0.10 @ 100W = $0.29
Cost per day @ $0.10 @ 200W = $0.48
Cost per day @ $0.10 @ 400W = $0.96

Cost per day @ $0.25 @ 60W = $0.36
Cost per day @ $0.25 @ 100W = $0.60
Cost per day @ $0.25 @ 200W = $1.20
Cost per day @ $0.25 @ 400W = $2.40

25 BTC/block @ 30M difficulty @ $12 USD/BTC = $12.07 / day

Let's look at how much profit is effected by power

using 60W as baseline
Cost per day @ $0.10 @ 60W = baseline is 0% more profitable
Cost per day @ $0.10 @ 100W = baseline is 1.27% more profitable
Cost per day @ $0.10 @ 200W = baseline is 2.94% more profitable
Cost per day @ $0.10 @ 400W = baseline is 7.38% more profitable

Cost per day @ $0.25 @ 60W = baseline is 0% more profitable
Cost per day @ $0.25 @ 100W = baseline is 2.09% more profitable
Cost per day @ $0.25 @ 200W = baseline is 7.72% more profitable
Cost per day @ $0.25 @ 400W = baseline is 21.10% more profitable

Obviously, as difficulty goes up, profitability goes up. As such, the affect of power usage on profitable also goes up.

Some people might say 5% is nothing...we tip pool operators that much. Others are trying to maximize every penny. Granted, Avalon now claims a 10% edge in hashing power (over BFL)...I am uncertain how long that edge will last. Both bASIC and BFL have stated that there is (perhaps significant) room for improvement here.


I have orders from each of the big 3, so I'm not trying to bash Avalon here. As a customer I just want a great product that will give me a decent bang for my buck.

BFL offers good hash rate with lower power.
bASIC offers good $/GH...still waiting for power numbers.
Avalon still has good $/GH (with bumped specs)....still waiting for power numbers.

I tried to diversify for the first run of ASICs, but if/when I decide to order more units...I'm looking for the best bang for the buck going forward.

I hope you keep us posted on your impressions of each device and it's performance/watt.

It is rare to find someone whom can compare all three in the same locality. Your reviews will be indispensable.


Title: Re: Avalon ASIC Development Status
Post by: arklan on October 25, 2012, 02:11:07 AM
this whole power debate is exactly why i have always planned to set up solar/wind/whatever power sources asap for any significant mining effort. ...i should set up a solar selling business for BTC... :D


Title: Re: Avalon ASIC Development Status
Post by: PuertoLibre on October 25, 2012, 02:19:54 AM
this whole power debate is exactly why i have always planned to set up solar/wind/whatever power sources asap for any significant mining effort. ...i should set up a solar selling business for BTC... :D
Rather than solar alone you should look into companies that are pioneering technology to convert heat (on your roof) into power. Most average sized houses have a 47 kilowatt hotplate right above their heads.

All that energy goes to waste every day. Companies that are working to harness that thermal energy are probably going to be very rich in the future.

Some thermal waters heaters (not the solar panel type) for example, require very little roof area to heat water. Converting the rest of it into actual electrical energy is the sweet spot in alternative energy.


Title: Re: Avalon ASIC Development Status
Post by: Zeek_W on October 25, 2012, 03:40:26 AM
this whole power debate is exactly why i have always planned to set up solar/wind/whatever power sources asap for any significant mining effort. ...i should set up a solar selling business for BTC... :D

I have wind, hydro and solar setup on my property. I don't live there but when I do - free everything!


Title: Re: Avalon ASIC Development Status
Post by: pieppiep on October 25, 2012, 03:42:56 AM
this whole power debate is exactly why i have always planned to set up solar/wind/whatever power sources asap for any significant mining effort. ...i should set up a solar selling business for BTC... :D

I have wind, hydro and solar setup on my property. I don't live there but when I do - free everything!
If I want 'free' energy like that, I still have to buy the turbines/panels, so there still is no free energy.


Title: Re: Avalon ASIC Development Status
Post by: Coinoisseur on October 25, 2012, 03:45:35 AM
What do you think about this?
Especially as regards the European market, with electricity costs between $ 0.10-0.30/kwh

strictly speaking on power being the only variable I wouldn't even suggest to "mine-for-profit" basis with power rates higher than $0.10 ( and you are unable to get write offs or reductions. )

Sorry, but you know, in how many countries in the world the power rates is cheaper than $0.10, right?
In Europe I know none! This means, that you throw away in minimum the whole European market for  "mine-for-profit" or "long term mining as an investment" customers!

The main inputs of mining are equipment cost and electricity cost, decent mining setups require pretty light amount of man hours to maintain. So like other electricity sensitive activities areas with the cheapest power will have a distinct advantage in terms of ROI rates. Unless Europe develops more efficient hardware and then restricts export of said hardware it's going to be at a disadvantage in these activities given current electricity costs.


Title: Re: Avalon ASIC Development Status
Post by: DoomDumas on October 25, 2012, 04:09:30 AM
I keep reading about estimate, prediction, comparison.. power usage, difficulty, Gh/s...

Everytimes, ONE BIG THING comes to my mind...

Is'nt all a big guess about the future "price" of a bitcoin ?  

No one can predict the price, I assume that's why all calculation and estimate are done on a 12$ basis..  Ok, we need a base to make up our mind..

BUT, it almost a certitude that the ratio of exchange will not be 12 USD/BTC in two years, even in few month !

As we saw in the last 2 years, the ratio of exchange USD/BTC have been between 2 and 30  (let's say 32 to simplify)  from 2 to 32 it's 4 times doubling or dividing.

Some scenario on a 2 year time span :


(IMHO) realistic possibility : X4 or /4

12 double 4 times = 192 USD/BTC ratio.  peoples will then say, OMG, why I have not ordered tons of those asic !
12 halved 4 times = 1.5 USD/BTC ratio.  I dont want to write what peoples might say !
major event : 0 USD/BTC  (it's not impossible)


(IMHO) conservative possibility : X2 or /2

12 double 1 time = 24 USD/BTC : enought to say I would mine with a power cost of 0.30$/Kwh
12 divided 1 time = 6 USD/BTC : hard time for miner !
major event : 0 USD/BTC  (it's not impossible)

As an optimistic : I'll give it a try... I bet on a 100 Fiat/BTC ratio within 2 years....

Buying asic..

And I'll never invest more than I can afford to lose overnight because "major event : 0 USD/BTC  (it's not impossible)"


Was my 2 satoshi




Title: Re: Avalon ASIC Development Status
Post by: Syke on October 25, 2012, 04:38:41 AM
Is'nt all a big guess about the future "price" of a bitcoin

So take price out of the equation. A slightly better way to estimate future returns is on BTC output verses BTC cost today.

Today's price of $12/btc, $1299 = 108 BTC for an Avalon ASIC.
66 GH/s, 12.5 btc/block reward

That leaves only 1 variable, network difficulty. ASIC pre-orders are going to hit 10x pretty quickly, beyond that it'll probably taper off.

10x network difficulty = 1.08 btc/day

100 days to recover spent coins. Funny how that turned out to be a nice round number.


Title: Re: Avalon ASIC Development Status
Post by: Transisto on October 25, 2012, 06:41:45 AM
About power figures,

If the same energy now spent on GPU get spent on 1w/ghs ASICs the difficulty will be 450x what it is now or ~1.38 billion.

That would be 200m$ worth of BFL hardware... Not going to happen, leaving quite a margin for less efficient device to cover their investments ... at some point.


Title: Re: Avalon ASIC Development Status
Post by: mrb on October 25, 2012, 07:04:54 AM
That would be 200m$ worth of BFL hardware... Not going to happen, leaving quite a margin for less efficient device to cover their investments ... at some point.

Are you one of these guys who think that "640kB ought to be enough for anyone"?

If Bitcoin continue to succeed, it will come to a point where $200M will have been spent on mining hardware.
Just consider that today alone, $20M has been spent on CPU/GPU/FGPA mining hardware.
Going to $200M is only a 10x increase.


Title: Re: Avalon ASIC Development Status
Post by: pieppiep on October 25, 2012, 07:11:00 AM
That would be 200m$ worth of BFL hardware... Not going to happen, leaving quite a margin for less efficient device to cover their investments ... at some point.

Are you one of these guys who think that "640kB ought to be enough for anyone"?

If Bitcoin continue to succeed, it will come to a point where $200M will have been spent on mining hardware.
Just consider that today alone, $20M has been spent on CPU/GPU/FGPA mining hardware.
Going to $200M is only a 10x increase.
Unless by then $ stops to exists and you buy your hardware with BTC  ;D


Title: Re: Avalon ASIC Development Status
Post by: Transisto on October 25, 2012, 07:39:36 AM
That would be 200m$ worth of BFL hardware... Not going to happen, leaving quite a margin for less efficient device to cover their investments ... at some point.

Are you one of these guys who think that "640kB ought to be enough for anyone"?

If Bitcoin continue to succeed, it will come to a point where $200M will have been spent on mining hardware.
Just consider that today alone, $20M has been spent on CPU/GPU/FGPA mining hardware.
Going to $200M is only a 10x increase.

The 20m$ GPUs pay themselves in ~300 days with current profit/watts, while the 200m$ = ~20 years (Edit: Actually never given reward halving)

The price would need to be of an average of 240$ during the next four year for hardware to pay for itself in the same duration.

In other word, very plausible given the imbalance in monetary distribution, Unfortunately my planing for a such a scenario is right next to my alien invasion preparedness folder.


Title: Re: Avalon ASIC Development Status
Post by: Xfinity on October 25, 2012, 08:46:18 AM
Is'nt all a big guess about the future "price" of a bitcoin ?  

+1, we can only speculate at this point. We will soon know ;)...


Title: Re: Avalon ASIC Development Status
Post by: makomk on October 25, 2012, 09:37:41 AM
That would be 200m$ worth of BFL hardware... Not going to happen, leaving quite a margin for less efficient device to cover their investments ... at some point.
That would be 200M $ worth of BFL hardware at current prices. There's a substantial financial incentive for them to drop their prices once business slows down - the marginal cost of ASICs is fairly low and the up-front cost fairly high, and they probably want to make as much money on that upfront investment as possible. Of course, that doesn't leave much room for purchasers of BFL's devices to cover their investments either.


Title: Re: Avalon ASIC Development Status
Post by: ercolinux on October 25, 2012, 09:57:41 AM
That would be 200m$ worth of BFL hardware... Not going to happen, leaving quite a margin for less efficient device to cover their investments ... at some point.
That would be 200M $ worth of BFL hardware at current prices. There's a substantial financial incentive for them to drop their prices once business slows down - the marginal cost of ASICs is fairly low and the up-front cost fairly high, and they probably want to make as much money on that upfront investment as possible. Of course, that doesn't leave much room for purchasers of BFL's devices to cover their investments either.

Indeed pushing too much power in the network in a time brings to very low profit unless price of btc skyrockets. So if ASIC producer don't want to kill themself they have to don't reduce price or put too many ASIC out. Doing some small calculation if network power jumps at 40X a 60GH/s ASIC can barely cover the energy costs in USA and noway is profitable in lot of European country (in Italy you've to add 500$ in a year to cover energy cost).
So or price of BTC double in next few months or power increment due to ASIC introduction will not be over a 20-25X or there'll be no profit in mining


Title: Re: Avalon ASIC Development Status
Post by: Aseras on October 25, 2012, 01:03:42 PM
Something many of you are forgetting is that the bitcoin infrastructure as it is now, with pools and current hardware will essentially go bye bye once the asics start hitting hard. It's going to turn the world upside down for a few weeks/months. There's something like 20t/hash now and a majority of that is going to evaporate a month or two into asics.


Title: Re: Avalon ASIC Development Status
Post by: pieppiep on October 25, 2012, 01:09:54 PM
Why would the pools disappear?
If someone mines with a single gpu now and has 1/10000th of the total networkspeed and gets a asic and still has a 1/10000th of the total networkspeed, it's still a good idea to use a pool.


Title: Re: Avalon ASIC Development Status
Post by: ercolinux on October 25, 2012, 02:02:17 PM
Why would the pools disappear?
If someone mines with a single gpu now and has 1/10000th of the total networkspeed and gets a asic and still has a 1/10000th of the total networkspeed, it's still a good idea to use a pool.

A mining rig of 500MH/s today have 1/40000 of network power a single 60GH ASIC at the beginning will be near 1/2000 (like a 2GH today) and a 1TB rig will be in the 1/100th range like a small pool today (30-40GHs of today rigs); pool still can work, but it's quite easy for who have 2-3 60GH ASIC mine in solo and get 1-2 block a month in the first month.


Title: Re: Avalon ASIC Development Status
Post by: dani on October 25, 2012, 08:11:51 PM
Is there anything planned after avalon? Avalon II maybe? Or maybe just another batch? Didnt read anything about it, nor from any other competitor.. just curious :)


Title: Re: Avalon ASIC Development Status
Post by: MrTeal on October 25, 2012, 10:48:16 PM
Packaged Chip Size: 7 mm x 7 mm

Thanks for the transparency, but the unpackaged die size is what you ought to be posting.  Without that it's impossible to make performance comparisons (or at least those comparisons would have to assume it fills the whole package cavity, which portrays Avalon in the worst possible light).  Please provide the unpackaged die size.

Also, I think you may have neglected to say how many of these chips are in the 60GH/s device… or perhaps I missed that.  Anyways, without knowing how many chips are in the device, none of the information above is really useful.  Did you post this somewhere that I didn't see?
Assuming a maximum die size of about 25mm^2 in a 7mm QFN, I would guess quite a lot of them if the unit is actually drawing 400W. Probably a few dozen. That's a lot of heat to move from a molded package.

That would be 200m$ worth of BFL hardware... Not going to happen, leaving quite a margin for less efficient device to cover their investments ... at some point.
That would be 200M $ worth of BFL hardware at current prices. There's a substantial financial incentive for them to drop their prices once business slows down - the marginal cost of ASICs is fairly low and the up-front cost fairly high, and they probably want to make as much money on that upfront investment as possible. Of course, that doesn't leave much room for purchasers of BFL's devices to cover their investments either.
There's definitely a lot of room for BFL to come down, but I'm not sure just how much. I could see the Minirig SC come in at $15k, but it doesn't matter if the ASICs fall out of the sky, you're not going to see a Minirig SC at $1500 until there's a respin that brings down the power and size of a 1.5TH/s machine to close to the size of a Single. My speculation is that BFL could sell the Minirig SC quite profitably at the $15k price point of the current MR, but it would not be economical at $7500 (1/4 it's current price) unless they start to produce tens of thousands of them.


Title: Re: Avalon ASIC Development Status
Post by: DoomDumas on October 26, 2012, 01:54:32 AM
Why would the pools disappear?
If someone mines with a single gpu now and has 1/10000th of the total networkspeed and gets a asic and still has a 1/10000th of the total networkspeed, it's still a good idea to use a pool.

A mining rig of 500MH/s today have 1/40000 of network power a single 60GH ASIC at the beginning will be near 1/2000 (like a 2GH today) and a 1TB rig will be in the 1/100th range like a small pool today (30-40GHs of today rigs); pool still can work, but it's quite easy for who have 2-3 60GH ASIC mine in solo and get 1-2 block a month in the first month.

Maybe Im wrong, but mining on a pool or solo would get almost the same result, even in a few month time span...   your tought ?


Title: Re: Avalon ASIC Development Status
Post by: Bogart on October 26, 2012, 02:29:45 AM
Why would the pools disappear?
If someone mines with a single gpu now and has 1/10000th of the total networkspeed and gets a asic and still has a 1/10000th of the total networkspeed, it's still a good idea to use a pool.

A mining rig of 500MH/s today have 1/40000 of network power a single 60GH ASIC at the beginning will be near 1/2000 (like a 2GH today) and a 1TB rig will be in the 1/100th range like a small pool today (30-40GHs of today rigs); pool still can work, but it's quite easy for who have 2-3 60GH ASIC mine in solo and get 1-2 block a month in the first month.

Maybe Im wrong, but mining on a pool or solo would get almost the same result, even in a few month time span...   your tought ?

I don't understand why so many people are confused about this.

Yes, statistically it should work out exactly the same.  Solo just tends to be a lot more "chunky" in its payouts.

(minus any variance based on server reliability, server operator fees, etc.)


Title: Re: Avalon ASIC Development Status
Post by: Aseras on October 26, 2012, 04:10:19 AM
Why would the pools disappear?
If someone mines with a single gpu now and has 1/10000th of the total networkspeed and gets a asic and still has a 1/10000th of the total networkspeed, it's still a good idea to use a pool.

All the major pools now won't support an ASIC. There has to be major changes for them to support ASIC. Especially at the beginning when ASIC are returning easy work extremely fast. Even with stratum there's going to be major bandwidth problems in the beginning.


Title: Re: Avalon ASIC Development Status
Post by: Inaba on October 26, 2012, 04:15:56 AM
That would not be true.  EMC, BTCguild, Slush and Eligius are all ready and waiting for ASIC.


Title: Re: Avalon ASIC Development Status
Post by: ercolinux on October 26, 2012, 06:23:25 AM
Why would the pools disappear?
If someone mines with a single gpu now and has 1/10000th of the total networkspeed and gets a asic and still has a 1/10000th of the total networkspeed, it's still a good idea to use a pool.

A mining rig of 500MH/s today have 1/40000 of network power a single 60GH ASIC at the beginning will be near 1/2000 (like a 2GH today) and a 1TB rig will be in the 1/100th range like a small pool today (30-40GHs of today rigs); pool still can work, but it's quite easy for who have 2-3 60GH ASIC mine in solo and get 1-2 block a month in the first month.

Maybe Im wrong, but mining on a pool or solo would get almost the same result, even in a few month time span...   your tought ?

I don't understand why so many people are confused about this.

Yes, statistically it should work out exactly the same.  Solo just tends to be a lot more "chunky" in its payouts.

(minus any variance based on server reliability, server operator fees, etc.)

If your hash rate is very high mining in solo is more convenient: you don't have the fees to pay to pool and you get also all the transaction fee. On the long run even with the variance in payouts you can easily earn a 2-5% more with solo mining.


Title: Re: Avalon ASIC Development Status
Post by: pieppiep on October 26, 2012, 06:44:53 AM
Why would the pools disappear?
If someone mines with a single gpu now and has 1/10000th of the total networkspeed and gets a asic and still has a 1/10000th of the total networkspeed, it's still a good idea to use a pool.

All the major pools now won't support an ASIC. There has to be major changes for them to support ASIC. Especially at the beginning when ASIC are returning easy work extremely fast. Even with stratum there's going to be major bandwidth problems in the beginning.
Why is the 1kB/s (regardless of miningspeed) a major bandwidth problem?


Title: Re: Avalon ASIC Development Status
Post by: Soros Shorts on October 26, 2012, 09:59:30 AM
Why would the pools disappear?
If someone mines with a single gpu now and has 1/10000th of the total networkspeed and gets a asic and still has a 1/10000th of the total networkspeed, it's still a good idea to use a pool.

All the major pools now won't support an ASIC. There has to be major changes for them to support ASIC. Especially at the beginning when ASIC are returning easy work extremely fast. Even with stratum there's going to be major bandwidth problems in the beginning.
Why is the 1kB/s (regardless of miningspeed) a major bandwidth problem?
If there were a period where a block was solved once every 5 seconds (just making this number up) until difficulty caught up I am guessing that there could be a temporary network congestion problem. Mining might only be 1kB/s but block propagation could take up a large chunk of network bandwidth. You could see p2pool-like problems manfesting on the main Bitcoin network, the major one being collisions of solved blocks that will result in many orphans. This wouldn't be a pool issue, though.


Title: Re: Avalon ASIC Development Status
Post by: pieppiep on October 26, 2012, 10:17:00 AM
Why would the pools disappear?
If someone mines with a single gpu now and has 1/10000th of the total networkspeed and gets a asic and still has a 1/10000th of the total networkspeed, it's still a good idea to use a pool.

All the major pools now won't support an ASIC. There has to be major changes for them to support ASIC. Especially at the beginning when ASIC are returning easy work extremely fast. Even with stratum there's going to be major bandwidth problems in the beginning.
Why is the 1kB/s (regardless of miningspeed) a major bandwidth problem?
If there were a period where a block was solved once every 5 seconds (just making this number up) until difficulty caught up I am guessing that there could be a temporary network congestion problem. Mining might only be 1kB/s but block propagation could take up a large chunk of network bandwidth. You could see p2pool-like problems manfesting on the main Bitcoin network, the major one being collisions of solved blocks that will result in many orphans. This wouldn't be a pool issue, though.
5 seconds a block won't be a big problem because it won't generate extra transactions. Each block will be the 80 bytes header with a little data for the block reward, at most 1/4kB.
There probably won't even be much collisions because I really doubt an increase of 100k of speed will come at once from multiple sources.

5 seconds a block takes at most 2016 * 5 = 10080 seconds = 2 hours 48 minutes to change the difficulty to 20 seconds a block. (maximum increase is times 4)


Title: Re: Avalon ASIC Development Status
Post by: BitSyncom on October 26, 2012, 12:39:33 PM
Most pool can queried for 120 getworks at a time, noticeably the ecoinpool variant. With other new systems like Stratum with aims to solve any other potential problem and future proofing the network.

In addition, like I have previously stated, Avalon will be releasing our image.iso for the controller sometime in December this will include documentation on how our ASIC will communicate with mining softwares and pools. we will also be providing patches to opensource miners like CGminer.

With that said, we are aware of this bandwidth concern and do not deem it to be a problem at the moment.


Title: Re: Avalon ASIC Development Status
Post by: Aseras on October 26, 2012, 06:10:39 PM
That would not be true.  EMC, BTCguild, Slush and Eligius are all ready and waiting for ASIC.


No one knows if they are ready because no one has a working asic to test.

The BFL singles had issues with pools and clients when they first came out. They still don't work well with p2pool because of how the bitstream works.

Asic are basically just hardcoded fpga, but faster. No one really knows yet exactly what hiccups there will be, but I think for the first few weeks after they hit it's going to be very interesting and very bumpy.

The majority of the asics save the japalepeno? are going to be multithreaded or appear as a multi gpu/asic device, so each device is going to request several works at once and return several at once, hundreds or thousands of times faster than now. Even with stratum and nrolltime allowing the miner to save requesting and generate it's own work, they have to go back up to a pool and get confirmed. It's going to be interesting


Title: Re: Avalon ASIC Development Status
Post by: Inaba on October 26, 2012, 06:46:51 PM
Heh.. if you say so!


Title: Re: Avalon ASIC Development Status
Post by: Aseras on October 26, 2012, 09:02:12 PM
Heh.. if you say so!


well hurry up and build a working asic so we will all know already. Stop farking off in the forums and start soldering or cursing at someone in mandarin :P


Title: Re: Avalon ASIC Development Status
Post by: squeept on October 26, 2012, 09:09:35 PM
Heh.. if you say so!


well hurry up and build a working asic so we will all know already. Stop farking off in the forums and start soldering or cursing at someone in mandarin :P

I'm sending Inaba a care package of the mandarin Rosetta Stone and a used Weller hobby iron. Do work, son.


Title: Re: Avalon ASIC Development Status
Post by: gmaxwell on October 26, 2012, 10:43:08 PM
No one knows if they are ready because no one has a working asic to test.
The BFL singles had issues with pools and clients when they first came out. They still don't work well with p2pool because of how the bitstream works.
It's quite easy (two lines changed or so) to modify pool software to accept 'difficulty 0' shares, and a regular cpu miner to consider every attempt a winner.. by doing this you can produce rates enormously faster than any asic.  If you're board its only a few more lines changed to fork testnet or bitcoin and mine a bunch of fake blocks to test the whole system. 

There may be some burps in practice but you can certainly get some reasonable testing in.


Title: Re: Avalon ASIC Development Status
Post by: eldentyrell on October 27, 2012, 09:42:25 PM
They've admitted to using a larger die size than their competitors.

Link?  I haven't seen anything from them regarding die size, but I haven't been following too closely.

I'm also worried by their refusal to say how many chips are in the 60GH/s device.  I count at least five people asking in this thread and still no answer.


Title: Re: Avalon ASIC Development Status
Post by: crazyates on October 28, 2012, 01:53:54 AM
They've admitted to using a larger die size than their competitors.
Link?  I haven't seen anything from them regarding die size, but I haven't been following too closely.

I'm also worried by their refusal to say how many chips are in the 60GH/s device.  I count at least five people asking in this thread and still no answer.

Dude, he listed that information in the very first post of this thread: 110nm.

Code:
Chip Specification
Technology Summary:
    TSMC 0.11- micron G process

He has previously posted that they would be using either 110nm or 130nm, but confirmed the details here.



Title: Re: Avalon ASIC Development Status
Post by: MrTeal on October 28, 2012, 01:56:38 AM
They've admitted to using a larger die size than their competitors.
Link?  I haven't seen anything from them regarding die size, but I haven't been following too closely.

I'm also worried by their refusal to say how many chips are in the 60GH/s device.  I count at least five people asking in this thread and still no answer.

Dude, he listed that information in the very first post of this thread: 110nm.

Code:
Chip Specification
Technology Summary:
    TSMC 0.11- micron G process

He has previously posted that they would be using either 110nm or 130nm, but confirmed the details here.
Die size isn't the process node, it's how physically large the die is. IE, 5mmx5mm or 25mm^2, something like that.


Title: Re: Avalon ASIC Development Status
Post by: crazyates on October 28, 2012, 02:20:43 AM
They've admitted to using a larger die size than their competitors.
Link?  I haven't seen anything from them regarding die size, but I haven't been following too closely.

I'm also worried by their refusal to say how many chips are in the 60GH/s device.  I count at least five people asking in this thread and still no answer.

Dude, he listed that information in the very first post of this thread: 110nm.

Code:
Chip Specification
Technology Summary:
    TSMC 0.11- micron G process

He has previously posted that they would be using either 110nm or 130nm, but confirmed the details here.
Die size isn't the process node, it's how physically large the die is. IE, 5mmx5mm or 25mm^2, something like that.
My bad. /facepalm


Title: Re: Avalon ASIC Development Status
Post by: crazyates on October 28, 2012, 02:21:38 AM
Code:
Chip Specification
Technology Summary:

Packaged Chip Size: 7 mm x 7 mm
?


Title: Re: Avalon ASIC Development Status
Post by: Cablez on October 28, 2012, 02:23:12 AM
Code:
Chip Specification
Technology Summary:

Packaged Chip Size: 7 mm x 7 mm
?

That would be the fully packaged chip size. The die size would be a fraction of that in ex. 5x5mm or so.


Title: Re: Avalon ASIC Development Status
Post by: crazyates on October 28, 2012, 03:43:30 AM
I'm bad at this. I'm also tired. I think I'll shut up now.  ;)


Title: Re: Avalon ASIC Development Status
Post by: Cablez on October 28, 2012, 04:01:11 AM
No worries mate. I am beyond sleepy too. ;)


Title: Re: Avalon ASIC Development Status
Post by: bitboyben on October 29, 2012, 03:20:21 AM
Any photos? website?


Title: Re: Avalon ASIC Development Status
Post by: BitSyncom on October 29, 2012, 08:59:25 AM
update.

Shipping. We at Avalon understands the some what unreliableness of EMS in certain countries, to address this issue, all existing and future orders will be shipped out via DHL at no additional charge. This will ensure timely delivery of our products.


Title: Re: Avalon ASIC Development Status
Post by: thorvald on October 29, 2012, 10:17:07 AM
nice +1


Title: Re: Avalon ASIC Development Status
Post by: squid on October 29, 2012, 12:57:43 PM
Can't believe I missed this thread. Glad to see more competition in the ASIC market!


Title: Re: Avalon ASIC Development Status
Post by: Vicus on October 29, 2012, 02:16:32 PM
update.

Shipping. We at Avalon understands the some what unreliableness of EMS in certain countries, to address this issue, all existing and future orders will be shipped out via DHL at no additional charge. This will ensure timely delivery of our products.
For Russia DHL is absolutely unacceptable.
1. DHL doesn't deliver the goods to Russia for individuals. The exception is made for some online shops which have the direct contract relations with DHL.
2. For DHL of 30% duty is raised, if cost (including delivery cost) of the goods exceeds 200 euro/month. For EMS this threshold is 1000 euro/month (tax = 0.3 * (cost - threshold)).
3. Procedure of customs cleaning is more difficult for DHL and offen demands services of the customs broker. In case of EMS customs cleaning is strongly simplified.

I understand that EMS can deliver the goods not so quickly, but DHL this bigger evil for Russia.

Please take in account that info, when you will be shipping in Russia.


Title: Re: Avalon ASIC Development Status
Post by: BitSyncom on October 29, 2012, 04:02:11 PM
For Russia DHL is absolutely unacceptable.
1. DHL doesn't deliver the goods to Russia for individuals. The exception is made for some online shops which have the direct contract relations with DHL.
2. For DHL of 30% duty is raised, if cost (including delivery cost) of the goods exceeds 200 euro/month. For EMS this threshold is 1000 euro/month (tax = 0.3 * (cost - threshold)).
3. Procedure of customs cleaning is more difficult for DHL and offen demands services of the customs broker. In case of EMS customs cleaning is strongly simplified.

I understand that EMS can deliver the goods not so quickly, but DHL this bigger evil for Russia.

Please take in account that info, when you will be shipping in Russia.

Thank you for bring this to our attention, for now all orders are defaulted to DHL which has the fastest average shipping time to ensure timely delivery. We of course, will also listen to customers who wishes to use EMS instead due to various reasons, not to mention it is in fact cheaper for us to ship via EMS.


Title: Re: Avalon ASIC Development Status
Post by: Bogart on October 29, 2012, 06:51:37 PM
update.

Shipping. We at Avalon understands the some what unreliableness of EMS in certain countries, to address this issue, all existing and future orders will be shipped out via DHL at no additional charge. This will ensure timely delivery of our products.

Awesome!  That should save me a week off my delivery wait time, if not more.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: Kuma on October 29, 2012, 10:47:30 PM
Yep in some countries there can be different customs, as for courier services like DHL the price for shipping is added to the customs. EMS is taken as the post service and the shipping via post is deducted from the base for the customs.
The best way should be to add some switch to the shop to choose prefered shipping service.


Title: Re: Avalon ASIC Development Status
Post by: ninjaboon on October 29, 2012, 11:37:45 PM
update.

Shipping. We at Avalon understands the some what unreliableness of EMS in certain countries, to address this issue, all existing and future orders will be shipped out via DHL at no additional charge. This will ensure timely delivery of our products.

one up for avalon +1. your competitors charge extra for DHL.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: luffy on October 30, 2012, 08:49:03 AM
i prefer EMS in my country. i remember DHL to charge a high fee at customs.
Can we choose please?


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: allinvain on October 30, 2012, 01:08:40 PM
EMS is my preference as well...


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: Raize on October 30, 2012, 04:20:49 PM
I've sent emails but gotten no responses, does anyone know what we're supposed to do if we presently own Icarus but still want to reserve ASICs? Thanks.


Title: Re: Avalon ASIC Development Status
Post by: mrb on November 01, 2012, 06:57:50 AM
yes I expect 150 TH to be shipped by the end of January.

I doubt it. BFL already admited being 2 months behind schedule in delivery the SC line (Oct -> Dec).


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: BitSyncom on November 01, 2012, 11:29:50 PM
I've sent emails but gotten no responses, does anyone know what we're supposed to do if we presently own Icarus but still want to reserve ASICs? Thanks.

I've not gotten your email, be sure to send it to support@avalon-asic.com to ensure proper processing, or go on our support website http://support.avalon-asic.com directly to open a ticket in the future.

To answer your question, we will open the orders for trade-in customers later this month.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: BitSyncom on November 04, 2012, 10:00:03 PM
Can we choose please?

Yes, choice will be offered. I think the correct wording for this announcement is the added option to ship via DHL, but in addition DHL will be the default option selected, if you wish to use EMS, some actions will be required of the customer.

p.s.
Still recovering from Sandy, will provide more updates soon.


Title: Re: Avalon ASIC Development Status
Post by: kano on November 05, 2012, 03:42:27 PM
Most pool can queried for 120 getworks at a time, noticeably the ecoinpool variant. With other new systems like Stratum with aims to solve any other potential problem and future proofing the network.

In addition, like I have previously stated, Avalon will be releasing our image.iso for the controller sometime in December this will include documentation on how our ASIC will communicate with mining softwares and pools. we will also be providing patches to opensource miners like CGminer.

With that said, we are aware of this bandwidth concern and do not deem it to be a problem at the moment.
Regarding cgminer ...

Well firstly, to use the correct term - we accept git pull requests - just like bitcoin :)

Secondly, cgminer already supports roll-ntime, vardiff shares and Stratum.
GBT is in development and already working. It will probably be in the next release.

Getwork with roll-ntime can still support over 500GH/s in cgminer per single getwork for 2 minutes.
Higher diff shares is dependent on the pool - all 3 protocols (Getwork, Stratum and GBT) allow it.
GBT currently requires more bandwidth than Getwork and will well beyond 500GH/s
Anyway, those are really pool issues, not miner issues (since cgminer already supports 2 and will support all 3 of them shortly)

From a hardware point of view (as I've mentioned before) as long as it doesn't require polling, first generation ASIC shouldn't present a problem.
At 60GH/s it will be returning ~14 shares a second which of course should be fine over Serial/USB.
10 such devices should easily be OK also.
Feel free to work out how many you can go with Serial on USB :)

As mentioned above, as long as the pool supports high difficulty shares, that wont be an issue since the pool should be targeting getting a share every few seconds (or less) with it's difficulty adjustment.

Icarus didn't have polling so I don't expect Avalon to have it either.
The only mandatory thing required for ASIC missing from Icarus was a completion message
Temperature reporting is really a must and clock control is definitely an advantage, if available, since people use their devices in many different conditions and catering to the worst is bad for those who have the best environments.

Thirdly, hardware is required for proper support.
If you are going to support all the cgminer requests regarding your changes then that covers one part of it, but if we start getting support requests regarding the software and have no hardware to run it on, then at least some of those support requests are just going to be sent to you.

Every time changes go into cgminer, if we have no hardware to test the changes we can of course not be sure of the effect of those changes on different hardware.
Rarely will it be an issue, but when it is an issue, if we have no hardware, the answer is: well that's unfortunate.

I am stating the obvious, but I thought I better say it here anyway.

Now as most people already know: both BFL and bASIC are sending devs (us and others) hardware to get it working in time for release
(BFL has also stated they are flying me to the USA and yochdog (https://bitcointalk.org/index.php?action=profile;u=35852) across the USA to see their manufacturing and report to the community)

You seem to want to do the software yourself, but just realise that you may also end up being the ones to support it if only you have the hardware ...

--

And aside to others ... regarding chip count, ngzhang said here 15~30 :)
https://bitcointalk.org/index.php?topic=110090.msg1198669#msg1198669

--

EMS has been excellent sending to me in Australia from central China, Hong Kong and the USA.


Title: Re: Avalon ASIC Development Status
Post by: BitSyncom on November 05, 2012, 04:19:03 PM
BFL has also stated they are flying me to the USA and yochdog (https://bitcointalk.org/index.php?action=profile;u=35852) across the USA to see their manufacturing and report to the community
Oh? I didn't hear about this, when is this visit happening?

Well firstly, to use the correct term - we accept git pull requests - just like bitcoin
Now as most people already know: both BFL and bASIC are sending devs (us and others)  hardware to get it working in time for release
You seem to want to do the software yourself, but just realise that you may also end up being the ones to support it if only you have the hardware ...
1. cut me some slack, I'm used to SVN and said "patch". Regardless, git pull requests will be made as it was our original intention.
2. Is that what everyone else is doing? I'll make a thread soon for developers to request dev-units. can't be the odd one out now can we?
3. What gives you that impression? I'm a big fan of open source and as stated the whole openWRT image will be released and source code provided, if people want to run BFL/bASICs attached to Avalon devices they can do that too  ;)

And aside to others ... regarding chip count, ngzhang said here 15~30 :)
https://bitcointalk.org/index.php?topic=110090.msg1198669#msg1198669

Disregard, this information no longer apply. To provide a better explanation, we used a modular design so the number of chips on the Unit is not yet final, we are still playing around the numbers to get the best power consumption vs. hashrate.


Title: Re: Avalon ASIC Development Status
Post by: kano on November 05, 2012, 05:08:43 PM
BFL has also stated they are flying me to the USA and yochdog (https://bitcointalk.org/index.php?action=profile;u=35852) across the USA to see their manufacturing and report to the community
Oh? I didn't hear about this, when is this visit happening?
Why does everyone ask that when they know I can't reply :D

Quote
Well firstly, to use the correct term - we accept git pull requests - just like bitcoin
Now as most people already know: both BFL and bASIC are sending devs (us and others)  hardware to get it working in time for release
You seem to want to do the software yourself, but just realise that you may also end up being the ones to support it if only you have the hardware ...
1. cut me some slack, I'm used to SVN and said "patch". Regardless, git pull requests will be made as it was our original intention.
2. Is that what everyone else is doing? I'll make a thread soon for developers to request dev-units. can't be the odd one out now can we?
3. What gives you that impression? I'm a big fan of open source and as stated the whole openWRT image will be released and source code provided, if people want to run BFL/bASICs attached to Avalon devices they can do that too  ;)
Simply that cgminer is open source so you are well able to fork it if required.
The comment about cgminer had been made long ago but neither of us have had contact from you about it so I just presumed you were wanting to support it yourself but thought I'd point out the obvious reasons for having devs with the hardware.

Quote
And aside to others ... regarding chip count, ngzhang said here 15~30 :)
https://bitcointalk.org/index.php?topic=110090.msg1198669#msg1198669

Disregard, this information no longer apply. To provide a better explanation, we used a modular design so the number of chips on the Unit is not yet final, we are still playing around the numbers to get the best power consumption vs. hashrate.
OK. When I was looking for the early comments I made in the Lancelot thread, I came across that and thought it might still be valid.
I now see the answer is "no" :)


Title: Re: Avalon ASIC Development Status
Post by: irritant on November 05, 2012, 05:41:19 PM
Quote
3. What gives you that impression? I'm a big fan of open source and as stated the whole openWRT image will be released and source code provided, if people want to run BFL/bASICs attached to Avalon devices they can do that too 


how many devices can the avalon host (usb ports?)?


Title: Re: Avalon ASIC Development Status
Post by: BitSyncom on November 05, 2012, 08:39:07 PM
Why does everyone ask that when they know I can't reply :D
What do you mean? as in BFL has yet to inform you of this or you are not allow to say? little digging say they were suppose to do this Oct/Nov.

Simply that cgminer is open source so you are well able to fork it if required.
The comment about cgminer had been made long ago but neither of us have had contact from you about it so I just presumed you were wanting to support it yourself but thought I'd point out the obvious reasons for having devs with the hardware.

I guess I wasn't around when that happened, but don't take offense to it :)

how many devices can the avalon host (usb ports?)?

there's a usb port, so as many as your USB hub allow? I'm going to look up the actual limitations of the USB controller and get back to you.


Title: Re: Avalon ASIC Development Status
Post by: kano on November 05, 2012, 10:24:28 PM
Why does everyone ask that when they know I can't reply :D
What do you mean? as in BFL has yet to inform you of this or you are not allow to say? little digging say they were suppose to do this Oct/Nov.
Just that BFL have usually been very secret and if I know something everyone else doesn't know, of course I'm not going to be the one to announce it ...

Quote
Simply that cgminer is open source so you are well able to fork it if required.
The comment about cgminer had been made long ago but neither of us have had contact from you about it so I just presumed you were wanting to support it yourself but thought I'd point out the obvious reasons for having devs with the hardware.

I guess I wasn't around when that happened, but don't take offense to it :)
None taken. That's why I posted. To find out.


Title: Re: Avalon ASIC Development Status
Post by: Bogart on November 06, 2012, 04:11:33 AM
Why does everyone ask that when they know I can't reply :D
What do you mean? as in BFL has yet to inform you of this or you are not allow to say? little digging say they were suppose to do this Oct/Nov.
Just that BFL have usually been very secret and if I know something everyone else doesn't know, of course I'm not going to be the one to announce it

I hope you're not saying that when you come back from your tour.


Title: Re: Avalon ASIC Development Status
Post by: kano on November 06, 2012, 06:32:57 AM
Why does everyone ask that when they know I can't reply :D
What do you mean? as in BFL has yet to inform you of this or you are not allow to say? little digging say they were suppose to do this Oct/Nov.
Just that BFL have usually been very secret and if I know something everyone else doesn't know, of course I'm not going to be the one to announce it

I hope you're not saying that when you come back from your tour.
Eh? Why on earth would that happen?

The point of it for BFL is to prove to yochdog and I that they have what they say they have and tell everyone.
Though of course it's not a forgone conclusion that my response will be positive, of course.

It wont happen, but to be blunt, if when I left, they said to not say anything ... of course that would be the first of many things I would say :P


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: Inaba on November 06, 2012, 06:03:23 PM
There will be no restrictions on what Kano and Yoch can report.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: crazyates on November 06, 2012, 06:11:28 PM
There will be no restrictions on what Kano and Yoch can report.

I want to know how many doorknobs are located inside their office. I want to know how many steps it is from the farthest employee parking lot to the front door. How tall are the ceilings? How often are the paper towels in the bathroom refilled? Is it all the same color flooring throughout the entire building?

Answer me those, and then maybe I'll believe BFL is real.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: BitSyncom on November 06, 2012, 06:51:05 PM
There will be no restrictions on what Kano and Yoch can report.

So when is this thing happening Josh?


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: eldentyrell on November 08, 2012, 02:41:16 AM
Hi, could you please post your die size so I can list your product's η-factor (https://bitcointalk.org/index.php?topic=119668.0)?  BFL has posted all the information needed to compute theirs.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: Unacceptable on November 08, 2012, 05:27:00 AM
There will be no restrictions on what Kano and Yoch can report.

I want to know how many doorknobs are located inside their office. I want to know how many steps it is from the farthest employee parking lot to the front door. How tall are the ceilings? How often are the paper towels in the bathroom refilled? Is it all the same color flooring throughout the entire building?

Answer me those, and then maybe I'll believe BFL is real.

You Crazzzzzzy man  :D


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: BitSyncom on November 08, 2012, 06:16:24 AM
Hi, could you please post your die size so I can list your product's η-factor (https://bitcointalk.org/index.php?topic=119668.0)?  BFL has posted all the information needed to compute theirs.

3.882 mm

p.s.
while I understand your H/s/nm theory. The reality is you can't quiet measure things like that.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: eldentyrell on November 08, 2012, 01:04:50 PM
Hi, could you please post your die size so I can list your product's η-factor (https://bitcointalk.org/index.php?topic=119668.0)?  BFL has posted all the information needed to compute theirs.

3.882 mm

And the other necessary piece of information: how many of these 15(mm2) chips are in your 66Gh/s product?


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: kano on November 08, 2012, 08:38:12 PM
Hi, could you please post your die size so I can list your product's η-factor (https://bitcointalk.org/index.php?topic=119668.0)?  BFL has posted all the information needed to compute theirs.

3.882 mm

And the other necessary piece of information: how many of these 15(mm2) chips are in your 66Gh/s product?
Only necessary for the manufacturer ...


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: Phinnaeus Gage on November 08, 2012, 08:44:03 PM
There will be no restrictions on what Kano and Yoch can report.

I want to know how many doorknobs are located inside their office. I want to know how many steps it is from the farthest employee parking lot to the front door. How tall are the ceilings? How often are the paper towels in the bathroom refilled? Is it all the same color flooring throughout the entire building?

Answer me those, and then maybe I'll believe BFL is real.

Full Disclosure: This account is not one of my sock puppets, albeit I like how he thinks.  ;D


Title: Re: Avalon ASIC Development Status
Post by: hardcore-fs on November 09, 2012, 12:53:34 AM
Why does everyone ask that when they know I can't reply :D
What do you mean? as in BFL has yet to inform you of this or you are not allow to say? little digging say they were suppose to do this Oct/Nov.

Simply that cgminer is open source so you are well able to fork it if required.
The comment about cgminer had been made long ago but neither of us have had contact from you about it so I just presumed you were wanting to support it yourself but thought I'd point out the obvious reasons for having devs with the hardware.

I guess I wasn't around when that happened, but don't take offense to it :)

how many devices can the avalon host (usb ports?)?

there's a usb port, so as many as your USB hub allow? I'm going to look up the actual limitations of the USB controller and get back to you.

Wrong!!!!... it has little to do with the controller and far more to do with the inherent protocols and what you will use them for.

Maximum chain for the USB is 127 devices.
BUT........
Since the USB spec is SINGLE point to point communication, the limiting factor is going to be the bandwidth of the USB MINUS connects/disconnects over the speed of the number of devices.

That is to say that EVEN with 250MB/s of bandwidth OR USB3 , the shear act of connection & disconnection per device is going to be the overall limiting factor. ESPECIALLY for small packets of data (nonce result/key).

Which is WHY the absolute best way to do this would be with TWO ethernet/WIFI ports.
You could use  IP address X.X.X.254 to broadcast a STREAM of jobs continually on one ethernet port.
Then use the second Ethernet port to return results to the controller (smaller bandwidth with buffered results).
Absolutely NO need to connect/disconnect the work communication channel.

HUB the first ethernet connection. (an ETHERNET hub duplicates the same data packets on ALL connection without intervention, very high speed ESP. for a single stream.)
SWITCH the second ethernet connection.(more intelligent but induces slight switching delay)
As the secondary channel reported completion, then the primary communication channel would modify the stream to add new jobs & remove old ones.

Since it is a stream, it can scale well over multiple hubs....... USB will get buried at an exponential rate due to the speed of the ASIC clients need for WORK.


HC






Title: Re: [Announcement] Avalon ASIC Development Status
Post by: crazyates on November 09, 2012, 01:27:49 AM
There will be no restrictions on what Kano and Yoch can report.
I want to know how many doorknobs are located inside their office. I want to know how many steps it is from the farthest employee parking lot to the front door. How tall are the ceilings? How often are the paper towels in the bathroom refilled? Is it all the same color flooring throughout the entire building?

Answer me those, and then maybe I'll believe BFL is real.
Full Disclosure: This account is not one of my sock puppets, albeit I like how he thinks.  ;D
I'm not?


Title: Re: Avalon ASIC Development Status
Post by: 2112 on November 09, 2012, 01:30:01 AM
HUB the first ethernet connection. (an ETHERNET hub duplicates the same data packets on ALL connection without intervention, very high speed ESP. for a single stream.)
SWITCH the second ethernet connection.(more intelligent but induces slight switching delay)
Actually if you measure the packet loss statistic you'll find that using only hubs (or even just one hub) will give you best results. Run-of-the-mill Ethernet switches have unfortunately quite bad error probabilities.

Even the top-of-the-line Ethernet switches with 802.3x and 802.1p are just about equaling error rates of a cheap fixed-speed 10BaseT or 100BaseTX hubs with all cards correctly supporting the collision detection/exponential backoff/retry.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: kano on November 09, 2012, 05:15:45 AM
Meanwhile on my not very expensive D-Link DGS-1008D GBit switch my desktop is connected to:

http://media.gdgt.com/img/product/12/9ry/dgs-1008d-oqx-460.jpg

p9p1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet xxx.xxx.xxx.xxx  netmask 255.255.255.0  broadcast xxx.xxx.xxx.255
        inet6 xxxx::xxxx:xxxx:xxxx:xxxx  prefixlen 64  scopeid 0x20<link>
        ether xx:xx:xx:xx:xx:xx  txqueuelen 1000  (Ethernet)
        RX packets 62921947  bytes 33087058738 (30.8 GiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 63627380  bytes 48378527420 (45.0 GiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

16:10:52 up 4 days,  2:51, 33 users,  load average: 1.36, 1.43, 1.48

Yep I prefer switches ...


Title: Re: Avalon ASIC Development Status
Post by: hardcore-fs on November 09, 2012, 10:41:53 AM
HUB the first ethernet connection. (an ETHERNET hub duplicates the same data packets on ALL connection without intervention, very high speed ESP. for a single stream.)
SWITCH the second ethernet connection.(more intelligent but induces slight switching delay)
Actually if you measure the packet loss statistic you'll find that using only hubs (or even just one hub) will give you best results. Run-of-the-mill Ethernet switches have unfortunately quite bad error probabilities.

Even the top-of-the-line Ethernet switches with 802.3x and 802.1p are just about equaling error rates of a cheap fixed-speed 10BaseT or 100BaseTX hubs with all cards correctly supporting the collision detection/exponential backoff/retry.


Then there is something very very wrong with your network or switch source (HuaWei?)...........

A hub sends packets to EVERY connection, making it ideal for single channel network mass communication, but fairly shite for anything else, because like USB, ethernet can only have one conversation on the wire at a time.
So if every connection is shouting to the hub, then the hub is backing off ALL the connections whilst it duplicates ALL the damned packets, to EACH connection.


 (which rules out your point Two above as well), since if you route ALL the traffic (IN/OUT) via 1  hub, then the returning hashes from the miners will prevent work being distributed and disrupt your stream.......

A switch is far more elegant, it knows the source/destination and so produces an exponential REDUCTION of traffic based on the number of connections VRS a hub.




Title: Re: Avalon ASIC Development Status
Post by: 2112 on November 09, 2012, 11:57:04 AM
Then there is something very very wrong with your network or switch source (HuaWei?)...........

A hub sends packets to EVERY connection, making it ideal for single channel network mass communication, but fairly shite for anything else, because like USB, ethernet can only have one conversation on the wire at a time.
So if every connection is shouting to the hub, then the hub is backing off ALL the connections whilst it duplicates ALL the damned packets, to EACH connection.


 (which rules out your point Two above as well), since if you route ALL the traffic (IN/OUT) via 1  hub, then the returning hashes from the miners will prevent work being distributed and disrupt your stream.......

A switch is far more elegant, it knows the source/destination and so produces an exponential REDUCTION of traffic based on the number of connections VRS a hub.
I can't really fault your theoretical analysis. What you wrote is quite right, especially about the benefit of multicasting. But I really doubt that you've actually run such configuration for any significant period of time.

I actually have production experience with multiple clusters in multiple physical/organizational locations with quite similar properties to the ones you've described: about 50/50 mixture of multicast/unicast packets, traffic non-peaky but near-uniform, short packets.

It is our observation that to achieve effective 0% packet loss we needed to specify either Cisco Catalyst (or similar class) switches or
(quite strangely) old Allied Telesyn/NetGear ProSafe/Intel InBusiness/etc. fixed-speed (or managed) hubs. The popular unmanaged office switches like NetGear/D-Link/Cisco Linksys were all showing anywere from serval through several tens to hundred-something occurences of packet corruption/loss per day. The steady-state packet rate is 50Hz-100Hz (or pps).

Our conjecture about those rare but steady failures is that this is somehow related to how the small/cheap switches pass as FCC Class B. To get home-office rating vendors use spread spectrum clocking, which is in effect an intentional jitter. So in order to get best performance use either FCC Class A data-center grade devices or cheap obsolete hubs that passed FCC Class B because they work under CSMA/CD principle.

Oh, and an additional free piece of advice who want to build cheap multicast clusters with hubs: test whether your network adapters actually do support half-duplex. Quite a number of devices claim to support half-duplex but actually don't and need upgraded firmware or simply a replacement. Various versions of popular LNE100TX & KNE100TX are common culprits; but there are so many variants of them that you'll really need exact part numbers. Some versions of Intel PRO/100+ line drivers for Windows don't correctly work with half-duplex.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: 2112 on November 09, 2012, 04:31:37 PM
p9p1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet xxx.xxx.xxx.xxx  netmask 255.255.255.0  broadcast xxx.xxx.xxx.255
        inet6 xxxx::xxxx:xxxx:xxxx:xxxx  prefixlen 64  scopeid 0x20<link>
        ether xx:xx:xx:xx:xx:xx  txqueuelen 1000  (Ethernet)
        RX packets 62921947  bytes 33087058738 (30.8 GiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 63627380  bytes 48378527420 (45.0 GiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
Kano is trolling, but he's a constructive troll, so his message is worth replying to. I was trying to find a link to the source code of utility I used for testing, but I can't seem to locate it. It was an offshot of "ttcp".

1) RX/TX statistics in many modern NIC are always zero, unless explicitly enabled. Somebody explained to me that it has something to do with passing WHQL certification. There are (or were) apparently two levels of it: normal and certified-for-clusters. At the "normal" level it is apparently much easier to get the "compatible with Windows X" certification if errors are reported only in specific circumstances. To get uncensored statistics you'll may need to place the chip in the "enterprise" or "diagnostic" or "cluster" mode. (Not to be confused with 802.3ad link aggregation or similar stuff).

2) To get a real feel for real packet loss use "ttcp" and monitor "netstat -s". For deepest understanding use both TCP/IP and UDP/IP mode with various buffer sizes.

3) There used to be a version of "ttcp" that supported one-sided testing by connecting on the remote side to the "simple IP services": echo, discard, chargen. Nowadays they need to be enabled explicitly. They aren't really usefull for benchmarking, but they are greatly useful to see if your network hub/switch/router can really cope with many hosts talking simultaneously. Please post here if you find such an utility.

4) If you see the statistics jumping in multiplies of 16777216 instead of 1 then don't assume that the driver is majorly broken. It may simply use incorrect byte order. So swap the byte order by hand or write a short script to do byte swap.

5) Some older Unix-compatible systems still have the spray/sprayd pair of programs used for packet loss testing. You may need to explicitly enable it, but it is a very easy to use program.

Have fun.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: kano on November 09, 2012, 09:11:46 PM
Meanwhile on my not very expensive D-Link DGS-1008D GBit switch my desktop is connected to:

http://media.gdgt.com/img/product/12/9ry/dgs-1008d-oqx-460.jpg

p9p1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet xxx.xxx.xxx.xxx  netmask 255.255.255.0  broadcast xxx.xxx.xxx.255
        inet6 xxxx::xxxx:xxxx:xxxx:xxxx  prefixlen 64  scopeid 0x20<link>
        ether xx:xx:xx:xx:xx:xx  txqueuelen 1000  (Ethernet)
        RX packets 62921947  bytes 33087058738 (30.8 GiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 63627380  bytes 48378527420 (45.0 GiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

16:10:52 up 4 days,  2:51, 33 users,  load average: 1.36, 1.43, 1.48

Yep I prefer switches ...

Well - if newer kernels hide errors - my older one (name hidden to protect the innocent) doesn't seem to:

... my internet connection (linux box bridged using rpppoe) that runs through an old switch to my ADSL modem

eth1      Link encap:Ethernet  HWaddr xx:xx:xx:xx:xx:xx 
          inet addr:10.xxx.xxx.xxx  Bcast:10.xxx.xxx.255  Mask:255.255.255.0
          inet6 addr: xxxx::xxxx:xxxx:xxxx:xxxx/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:601281065 errors:37121 dropped:76234 overruns:37121 frame:0
          TX packets:565768303 errors:0 dropped:0 overruns:19 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:397893249118 (370.5 GiB)  TX bytes:282719849762 (263.3 GiB)
          Interrupt:18 Base address:0xa000

07:36:19 up 112 days, 15:43

I see errors there ... to be expected ...

But the link to the main switch at home (D-Link DGS-1016D)

http://media0.symbios.pk/d-link-16-port-gigabit-rackmountable-switch-10-100-1000-m-dgs-1016d-1001.jpg

eth0      Link encap:Ethernet  HWaddr xx:xx:xx:xx:xx:xx 
          inet addr:xxx.xxx.xxx.xxx  Bcast:xxx.xxx.xxx.255  Mask:255.255.255.0
          inet6 addr: xxxx::xxxx:xxxx:xxxx:xxxx/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:687446826 errors:0 dropped:0 overruns:0 frame:0
          TX packets:719410978 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:315374024750 (293.7 GiB)  TX bytes:434255477859 (404.4 GiB)
          Interrupt:18 Base address:0x2000

I see none.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: Aseras on November 09, 2012, 09:51:33 PM
the errors you are squabbling over are insignificant, you could get half a million drops and not even notice it.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: thorvald on November 09, 2012, 09:56:05 PM
Please use this only for Avalon ASIC Development Status

Regards
Thor


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: flynn on November 10, 2012, 11:20:01 AM
2) To get a real feel for real packet loss use "ttcp" and monitor "netstat -s". For deepest understanding use both TCP/IP and UDP/IP mode with various buffer sizes.

It's called "nttcp" or "nuttcp" on my box (Debian squeeze)


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: leiyplane on November 13, 2012, 06:01:35 AM
Can first batch of Avalon ASIC reach even higher speed than current 66GHash at final stage?


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: BitSyncom on November 14, 2012, 10:33:51 AM
Can first batch of Avalon ASIC reach even higher speed than current 66GHash at final stage?

final stage? This is hard to say at the moment, we will keep the community updated however.

In addition, I've been getting questions regarding our shipping schedule and which "batch" the Order on the shop belongs to.

Inventory. Avalon learned from the mistake of our competitors and since conception has decided to release small order batches of 300 ( a number solely based on our estimated capacity) and only when a batch is close to finished, we will begin the sales of the next batch. When a new batch is announced, there will be another thread. In short, any units ordered so far, until further notice is part of batch #1, which is currently scheduled to ship at Jan 14th. In addition, as people fail to follow up with their orders, there are still some units left in the store, so if you missed your chance originally, now it's the time.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: CoinHoarder on November 14, 2012, 02:38:04 PM
final stage? This is hard to say at the moment, we will keep the community updated however.

In addition, I've been getting questions regarding our shipping schedule and which "batch" the Order on the shop belongs to.

Inventory. Avalon learned from the mistake of our competitors and since conception has decided to release small order batches of 300 ( a number solely based on our estimated capacity) and only when a batch is close to finished, we will begin the sales of the next batch. When a new batch is announced, there will be another thread. In short, any units ordered so far, until further notice is part of batch #1, which is currently scheduled to ship at Jan 14th. In addition, as people fail to follow up with their orders, there are still some units left in the store, so if you missed your chance originally, now it's the time.

For anyone that's interested, it looks like there are 3 units left in the store that will ship with the first batch.

avalon-asic.com (http://avalon-asic.com)


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: Raize on November 14, 2012, 02:39:42 PM
Inventory. Avalon learned from the mistake of our competitors and since conception has decided to release small order batches of 300 ( a number solely based on our estimated capacity) and only when a batch is close to finished, we will begin the sales of the next batch. When a new batch is announced, there will be another thread. In short, any units ordered so far, until further notice is part of batch #1, which is currently scheduled to ship at Jan 14th. In addition, as people fail to follow up with their orders, there are still some units left in the store, so if you missed your chance originally, now it's the time.

Okay. I have 5 Icarus I'd like to trade-in to reserve 5 Avalon. I've sent at least 3 emails asking how to do this and have not gotten any replies so I'm making my problems public. Was the talk about using Icarus as a credit fake or are you planning on honor it?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: purplesquid on November 14, 2012, 04:09:20 PM
Okay. I have 5 Icarus I'd like to trade-in to reserve 5 Avalon. I've sent at least 3 emails asking how to do this and have not gotten any replies so I'm making my problems public. Was the talk about using Icarus as a credit fake or are you planning on honor it?

Trade-Ins. Avalon believes in continuing the trust that have build up with our old customers. Reinstating our policy of $300 per Icarus, $400 per Lancelot, limited one FPGA trade-in per ASIC unit. The trade-in program will continue to be available and will apply to 1st-gen Avalons when the time comes.

Important Notice
Trade-in projct:

any icarus or lancelot user can trade-in their icarus or Lancelot mining board for 300USD (icarus) or 400USD (lancelot). every new 60G mining machine can only trade-in one old mining board. this project will start after mass-production.

trade-in is NOT available for pre-orders.

There are no trade-ins for this first pre order batch, but trade-ins will be available for the first mass order batch, as far as I can interpret.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Raize on November 14, 2012, 04:24:12 PM
Okay. Sorry, I seem to have gotten confused, the price changed and I figured this was not still the preorder batch. It makes sense if you need the cash to not do tradeins at this time.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: Frequency on November 14, 2012, 11:55:29 PM
final stage? This is hard to say at the moment, we will keep the community updated however.

In addition, I've been getting questions regarding our shipping schedule and which "batch" the Order on the shop belongs to.

Inventory. Avalon learned from the mistake of our competitors and since conception has decided to release small order batches of 300 ( a number solely based on our estimated capacity) and only when a batch is close to finished, we will begin the sales of the next batch. When a new batch is announced, there will be another thread. In short, any units ordered so far, until further notice is part of batch #1, which is currently scheduled to ship at Jan 14th. In addition, as people fail to follow up with their orders, there are still some units left in the store, so if you missed your chance originally, now it's the time.

For anyone that's interested, it looks like there are 3 units left in the store that will ship with the first batch.

avalon-asic.com (http://avalon-asic.com)

it magically disapeared???


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: BitSyncom on November 15, 2012, 12:58:54 AM
it magically disapeared???

Seems people have purchased those. I've just gone through and canceled a lot of pending orders from more than 10+ days ago that's still in the system, so there are some more units in stock now.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: thorvald on November 15, 2012, 02:01:46 PM
Any news regarding the devices ?

Regards
Thorvald


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: michaelmclees on November 15, 2012, 05:36:14 PM
Yeah.  I'm curious about these.  What will they look like?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 15, 2012, 06:08:42 PM
Any news regarding the devices ?

Regards
Thorvald

I suppose the competition has ruined the "no news is good news" statement. We are on schedule and is not currently running into any problems or having new development speeding up our timeline. I could post some facility photos, but I feel that's a childish move and proves nothing. Alas, if there is demand from the community, I'll be happy to show off our truly state of the art equipment used to produce the Avalon.

Yeah.  I'm curious about these.  What will they look like?

Mmm, exactly finish and metal used in the device is not final as of yet, but the dimension is most likely 375 x 375 x 150mm. It's a compact little thing.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Kuma on November 15, 2012, 06:16:28 PM

I suppose the competition has ruined the "no news is good news" statement. We are on schedule and is not currently running into any problems or having new development speeding up our timeline. I could post some facility photos, but I feel that's a childish move and proves nothing. Alas, if there is demand from the community, I'll be happy to show off our truly state of the art equipment used to produce the Avalon.

For myself I'd like to see some photos. It's not about necessity to prove anything, I just like fab photos and it makes this thread more colourful.  :)

Mmm, exactly finish and metal used in the device is not final as of yet, but the dimension is most likely 375 x 375 x 150mm. It's a compact little thing.

The dimensions sounds great, but pretty please not the white colour case for Avalon ;). Titanium or black should be best :).


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Turbor on November 15, 2012, 07:31:20 PM
I would like to see some pics too  ;D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on November 15, 2012, 11:11:37 PM

I suppose the competition has ruined the "no news is good news" statement. We are on schedule and is not currently running into any problems or having new development speeding up our timeline. I could post some facility photos, but I feel that's a childish move and proves nothing. Alas, if there is demand from the community, I'll be happy to show off our truly state of the art equipment used to produce the Avalon.

For myself I'd like to see some photos. It's not about necessity to prove anything, I just like fab photos and it makes this thread more colourful.  :)
I have pretty much the same sentiments.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 16, 2012, 03:15:47 AM
I've uploaded the full album here. http://imgur.com/a/KPBTl

and updated the front page.

http://i.imgur.com/ntaUch.jpg
http://i.imgur.com/HxCqCh.jpg
http://i.imgur.com/9PZYhh.jpg
http://i.imgur.com/cyu31h.jpg


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: CoinHoarder on November 16, 2012, 03:38:05 AM
 :o

Those look like very efficient machines. Thanks for sharing!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Kuma on November 16, 2012, 07:05:34 AM
Epic  :).
Thanks a lot for photos.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on November 16, 2012, 07:22:04 AM
For me pictures did not matter at all. It is very clear from the beginning that ngzhang and his team are having access to top manufacturing facilities + their skills make them mine favorites. That is why i "bet" on them! The main difference between them and their competition is that they are "Local" which is a huge advantage. I suggest to leave them work and to loose their time with pictures and such. When they have something to share with us they will do.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on November 16, 2012, 07:41:57 AM
For me pictures did not matter at all. It is very clear from the beginning that ngzhang and his team are having access to top manufacturing facilities + their skills make them mine favorites. That is why i "bet" on them! The main difference between them and their competition is that they are "Local" which is a huge advantage. I suggest to leave them work and to loose their time with pictures and such. When they have something to share with us they will do.
I have to say, the photos of the manufacturing line is impressive.

Though, I do have high confidence they will do as they say....it never hurts to ask.

In this case, I think the competition will be embarrassed with what they have in comparison.

Perhaps the Avalon dev team should post a thread titled:

"Avalon invests heavily in high speed production equipment"

---------------------------------------

Though, it is probably just a production line they have access to as opposed to actual purchases of property. Then again, if they have ready access to it locally, do they really need to purchase it? Probably not....

A question that comes to mind is where would an RMA be sent (for warranty repair)? Would it be sent to a USA address or a China address?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on November 16, 2012, 10:12:53 AM

If they have any sense they will handle RMA offsite and outside of China, since ShenZhen customs are having a silly season (due to the sudden surge of smuggling over the  LoWu/ Wong Gong boarders with Hong Kong/ Sheung Shui).


Currently if you want to get items into Shenzhen as returns they have to go via Beijing/ ShangHai..... because it is a shit load faster.








Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: CoinHoarder on November 16, 2012, 05:53:28 PM
I have a question. My apologies if its already been answered.

Will the Avalon be able to host other FPGAs/ASICs via USB?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 16, 2012, 07:48:48 PM
I have a question. My apologies if its already been answered.

Will the Avalon be able to host other FPGAs/ASICs via USB?

Yes, but since there's only one USB port, you'll have to use a USB hub.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on November 16, 2012, 08:00:36 PM
I have a question. My apologies if its already been answered.

Will the Avalon be able to host other FPGAs/ASICs via USB?

Yes, but since there's only one USB port, you'll have to use a USB hub.

0_0


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on November 17, 2012, 02:31:53 AM
In view of the situation at Hua Wei and past dealings with Chinese hardware,
I think I would really like to see the embedded network and communication code.

The funniest 'Trojan' I saw was a 'very well known' alarm manufacturer  that allowed the user to enter their own  4 digit 'user code'
But actually 3 of the digits were ignored when checking............


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 17, 2012, 08:44:12 PM
In view of the situation at Hua Wei and past dealings with Chinese hardware,
I think I would really like to see the embedded network and communication code.

The funniest 'Trojan' I saw was a 'very well known' alarm manufacturer  that allowed the user to enter their own  4 digit 'user code'
But actually 3 of the digits were ignored when checking............


It's using a Atheros AR7240 / Atheros AR9331 Chipset and it'll run openWRT, you are welcome to look all you want when we release the image.iso in a 2-3 weeks.

We have gotten some impressive people working with Avalon you don't really have to worry about that. For example, Fujitsu is doing our chip packaging.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on November 18, 2012, 03:11:13 AM
In view of the situation at Hua Wei and past dealings with Chinese hardware,
I think I would really like to see the embedded network and communication code.

The funniest 'Trojan' I saw was a 'very well known' alarm manufacturer  that allowed the user to enter their own  4 digit 'user code'
But actually 3 of the digits were ignored when checking............


It's using a Atheros AR7240 / Atheros AR9331 Chipset and it'll run openWRT, you are welcome to look all you want when we release the image.iso in a 2-3 weeks.

We have gotten some impressive people working with Avalon you don't really have to worry about that. For example, Fujitsu is doing our chip packaging.
Does this mean it is encased in plastic or will the chip be covered with a metal heat spreader?

What are the viable ambient operating temperatures for the Avalon ASIC? (32F > 105F?)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Raize on November 18, 2012, 07:00:59 PM
I would like to reserve a spot to be in on the second batch prior to the Chinese New Year.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 19, 2012, 06:26:09 AM
Does this mean it is encased in plastic or will the chip be covered with a metal heat spreader?

What are the viable ambient operating temperatures for the Avalon ASIC? (32F > 105F?)

Are you talking about the Atheros AR7240? or the ASIC? I'll assume it is the ASIC in question. I have already released packaging information we'll be using QFN, so yes it is plastic. The current ASIC is designed to operate at ambient temperature of 40C. There will be heat-sinks on both side of the PCB. the unit also designed to create a wind-tunnel like effect for air flow, I'll provide more detail once that test finishes.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: poon-TANG on November 19, 2012, 07:30:47 AM
No pics of the actual devices?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 19, 2012, 07:58:41 PM
No pics of the actual devices?

It is currently not in our favor to release this information.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on November 19, 2012, 10:03:35 PM
No pics of the actual devices?

It is currently not in our favor to release this information.
What is a [reasonable] timeframe for a render and an actual picture of the Avalon Device?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 19, 2012, 11:01:15 PM
No pics of the actual devices?

It is currently not in our favor to release this information.
What is a [reasonable] timeframe for a render and an actual picture of the Avalon Device?

This isn't a matter that is limited by time. Rather we do not wish to reveal our cards so early because we believe we have truly designed a unique ASIC that's very different from BFL and bASIC. After BFL and Tom starts demoing their devices and perhaps even started to ship them, In other words: Once the competition has demonstrated their device is finished and final, then we will release our information. Unless of course they push their release date back even further, then I think it is safe to say everything shall be revealed before this year ends.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on November 19, 2012, 11:56:06 PM
No pics of the actual devices?

It is currently not in our favor to release this information.
What is a [reasonable] timeframe for a render and an actual picture of the Avalon Device?

This isn't a matter that is limited by time. Rather we do not wish to reveal our cards so early because we believe we have truly designed a unique ASIC that's very different from BFL and bASIC. After BFL and Tom starts demoing their devices and perhaps even started to ship them, In other words: Once the competition has demonstrated their device is finished and final, then we will release our information. Unless of course they push their release date back even further, then I think it is safe to say everything shall be revealed before this year ends.
It sounds like you have a number of undisclosed features, correct?

Can you start a thread where we can make feature requests for the second/third generation Avalon device? (or would you prefer private feature requests by email?)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 20, 2012, 12:59:13 AM
It sounds like you have a number of undisclosed features, correct?
This is correct.

Can you start a thread where we can make feature requests for the second/third generation Avalon device? (or would you prefer private feature requests by email?)

You are welcome to put suggestions into this thread, PM me on the forum or send me a email. It is your choice to decide the delivery method for your own content.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on November 20, 2012, 02:50:26 AM
No pics of the actual devices?

It is currently not in our favor to release this information.
What is a [reasonable] timeframe for a render and an actual picture of the Avalon Device?

This isn't a matter that is limited by time. Rather we do not wish to reveal our cards so early because we believe we have truly designed a unique ASIC that's very different from BFL and bASIC. After BFL and Tom starts demoing their devices and perhaps even started to ship them, In other words: Once the competition has demonstrated their device is finished and final, then we will release our information. Unless of course they push their release date back even further, then I think it is safe to say everything shall be revealed before this year ends.

If 2 of your main competitors, BFL and bASIC, are both far enough along into the process of getting ASICs into customers hands as they say they are, then what are your concerns about publicizing this information? It's too late in the game for them to really steal any ideas from you, isn't it?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 20, 2012, 03:52:36 AM
If 2 of your main competitors, BFL and bASIC, are both far enough along into the process of getting ASICs into customers hands as they say they are, then what are your concerns about publicizing this information? It's too late in the game for them to really steal any ideas from you, isn't it?

If, then indeed. They are scheduled to ship before us anyways, I am fortunately enough to have the option to wait and see.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on November 20, 2012, 06:53:55 AM
Quote

If 2 of your main competitors, BFL and bASIC, are both far enough along into the process of getting ASICs into customers hands as they say they are, then what are your concerns about publicizing this information? It's too late in the game for them to really steal any ideas from you, isn't it?

Who says so? You or them? It may turn out that they are far behind at the end. Please leave Avalon team to work and stop losing their time with pictures and stuff. A picture, 3d rendering does not prove anything at all at least for me


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bcpokey on November 20, 2012, 07:07:06 AM
Quote

If 2 of your main competitors, BFL and bASIC, are both far enough along into the process of getting ASICs into customers hands as they say they are, then what are your concerns about publicizing this information? It's too late in the game for them to really steal any ideas from you, isn't it?

Who says so? You or them? It may turn out that they are far behind at the end. Please leave Avalon team to work and stop losing their time with pictures and stuff. A picture, 3d rendering does not prove anything at all at least for me

Takes like 20 minutes to take some good pictures, and provides people with days/weeks of things to talk about, drool over, and be satisfied with. I suppose in a perfect world everyone would both have the hype and high energy to throw thousands of dollars into an unknown pit, but also the calm and patience to not need any kind of reassurance that they didn't get ripped to kingdom come, but let's just deal with things as they are yes?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Fcx35x10 on November 20, 2012, 06:11:21 PM
looking good, keep us posted. i can't wait to see actual hardware pictures when they ship out


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 21, 2012, 02:00:27 PM
Takes like 20 minutes to take some good pictures, and provides people with days/weeks of things to talk about, drool over, and be satisfied with. I suppose in a perfect world everyone would both have the hype and high energy to throw thousands of dollars into an unknown pit, but also the calm and patience to not need any kind of reassurance that they didn't get ripped to kingdom come, but let's just deal with things as they are yes?

How can one be satisfied with something they don't even understand what they are looking at? I am personally being some what cautious of my competition because few oddities they have demonstrated...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Aseras on November 21, 2012, 02:06:50 PM
Would it be possible to get a pic or render of what the device is going to look like? Don't need anything fancy or details of the internals. Just how it looks on the outside so I can plan decorating my office with them :D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: abeaulieu on November 21, 2012, 02:23:28 PM
Takes like 20 minutes to take some good pictures, and provides people with days/weeks of things to talk about, drool over, and be satisfied with. I suppose in a perfect world everyone would both have the hype and high energy to throw thousands of dollars into an unknown pit, but also the calm and patience to not need any kind of reassurance that they didn't get ripped to kingdom come, but let's just deal with things as they are yes?

How can one be satisfied with something they don't even understand what they are looking at? I am personally being some what cautious of my competition because few oddities they have demonstrated...


Oddities like power consumption figures?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 21, 2012, 03:34:52 PM
Would it be possible to get a pic or render of what the device is going to look like? Don't need anything fancy or details of the internals. Just how it looks on the outside so I can plan decorating my office with them :D

It's a metal box! 375 x 375 x 150mm like I mentioned in a earlier reply (https://bitcointalk.org/index.php?topic=120184.msg1337076#msg1337076) As for color and finish, we may do a vote in 1-2 weeks and let the community decide.

Oddities like power consumption figures?

Not exactly, I've previously stated in the AMA (http://www.reddit.com/r/Bitcoin/comments/10vmxa/avalon_asic_ama/c6h1li1) month ago, their numbers are achievable, I have no reason to doubt them. I simply dislike their marketing approach of reporting the numbers in the "best-possible" scenario as oppose to giving conservative estimates and work their way down via process of elimination and testing.


I must say, the following criticism is purely my personal opinion, and often at times I feel it is not my place as a competitor representative to point these things out as they will not be presented as intended. although in this case I'm sure others with knowledge of IC design will agree with the following musings.


Code:
bASIC had mentioned how they have the ASIC(chips) but do not have the PCB.

This is very odd to me, in IC design cycles, a Tapeout (http://en.wikipedia.org/wiki/Tape-out) takes about 1~2 month, and during this time you can't do anything besides waiting for the foundry, usually you do everything else you can to get rest of the hardware ready so when you receive your chips you can finish your product immediately. Sure there maybe possible delays but bASIC has stated they have had the chips for quiet some time, how can PCB take so long?

Code:
BFL shows pictures of board, that seem is completed but won't do demonstrations, or invite Kano / Yochdog to the in house viewing

If you have everything why wouldn't you show off a working product, it is easiest way to convince the public and and future potential buyers. Does it mean it didn't work? Recently I also found out BFL had at least 1 revision of the chip (https://forums.butterflylabs.com/showthread.php/406-Any-chance-the-chips-won-t-work?p=5701&viewfull=1#post5701). This raised a red flag right away, it means they had to either perform Metal Fix a, Gate Fix, or even worst a RTL Fix. This also means that there was a problem with the previous revision, and since BFL have yet to receive the new chips (https://forums.butterflylabs.com/showthread.php/406-Any-chance-the-chips-won-t-work?p=5701&viewfull=1#post5701). We may never know if those chips on the pictures even worked.

This is why I said how can one be satisfied with something they don't even understand what they are looking at.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: punin on November 21, 2012, 04:40:11 PM
Josh has stated on BFL forums that the chips in the pics were non-functional dummy chips.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on November 21, 2012, 04:50:06 PM
Josh has stated on BFL forums that the chips in the pics were non-functional dummy chips.
According to Josh, they had some sort of issue with refraction on their first mask set.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 21, 2012, 04:55:45 PM
Josh has stated on BFL forums that the chips in the pics were non-functional dummy chips.
According to Josh, they had some sort of issue with refraction on their first mask set.
Source? I apologize if this was common knowledge, I was under the impression they were functional.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on November 21, 2012, 05:00:43 PM
Josh has stated on BFL forums that the chips in the pics were non-functional dummy chips.
According to Josh, they had some sort of issue with refraction on their first mask set.
Source? I apologize if this was common knowledge, I was under the impression they were functional.

Quote from: BFL_Josh
There is no visual difference between the Little Single and the Single. They are virtually the same except for the number of chips.

As for why the delay, if the November issue of Bitcoin Magazine would come out it would make a lot more sense.  Bottom line is, our chips are the most advanced chips by a wide, wide, margin compared to any other offering.  Because of that, the design has taken longer than expected.  Our process node also blows away any of the toy offerings from the other vendors and we had to deal with some unexpected refraction issues that needed to be addressed.
https://forums.butterflylabs.com/showthread.php/251-More-Jalapeno-Pictures-amp-Shipping-Update?p=3906&viewfull=1#post3906

He's previously posted that the chips aren't functional on their forums, but it's getting hard to find anything there, the search function sucks.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: eldentyrell on November 22, 2012, 06:11:45 AM
Hi, could you please post your die size so I can list your product's η-factor (https://bitcointalk.org/index.php?topic=119668.0)?  BFL has posted all the information needed to compute theirs.

Have you had a chance to post these figures?


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: BitSyncom on November 22, 2012, 06:31:33 AM
Hi, could you please post your die size so I can list your product's η-factor (https://bitcointalk.org/index.php?topic=119668.0)?  BFL has posted all the information needed to compute theirs.

Have you had a chance to post these figures?

Yes, awhile ago.

https://bitcointalk.org/index.php?topic=120184.msg1323704#msg1323704


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: Mikej0h on November 22, 2012, 02:33:55 PM
For anyone that's interested, it looks like there are 3 units left in the store that will ship with the first batch.

avalon-asic.com (http://avalon-asic.com)

I was one of the lucky bastards :).
Bought last of shelf, however it could be more are coming if people not paying for their ASIC.


Title: Re: Avalon ASIC Development Status
Post by: BitSyncom on November 24, 2012, 05:18:12 PM
Addressing the recent bASIC 33% performance increase and shipping delays:

For long we at Avalon have predicted the possibility of a price/hash war happening due to competition; after all, we fired the first shot by announce our device at 50% performance increase than the rest of the field initially.

If 2 of your main competitors, BFL and bASIC, are both far enough along into the process of getting ASICs into customers hands as they say they are, then what are your concerns about publicizing this information? It's too late in the game for them to really steal any ideas from you, isn't it?

If, then indeed. They are scheduled to ship before us anyways, I am fortunately enough to have the option to wait and see.

See, this is exactly what I'm talking about, now bASIC has announced they are increasing the chip count on the board, and there is possibility the engineers have to redesign their board, so are they really far along the process? Like I previously mentioned,  I am fortunately enough to have the option to wait and see.


Disregard, this information no longer apply. To provide a better explanation, we used a modular design so the number of chips on the Unit is not yet final, we are still playing around the numbers to get the best power consumption vs. hash-rate.

I have also previously mentioned due to the nature of our unit design and the fact we are due to ship after our competitors, we have time to play around with our numbers. In fact, I particularly scheduled for if something like this to happen, we still have time and can ship without delays.

and Lastly, the following still holds true.
It sounds like you have a number of undisclosed features, correct?
This is correct.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on November 25, 2012, 12:49:40 AM
Is it safe to say "the Avalon device is no where near its maximum performance at the current 66Gh/s"?

Is there still quite a lot of headroom to play with?

Any idea of when the next email update (#5)  may occur?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 26, 2012, 04:00:43 AM
Any idea of when the next email update (#5)  may occur?

Soon as in probably within the next week. we want to address some of the uncertainty when it comes to ASICs.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 28, 2012, 03:22:15 AM
No delays to see here.
 
To offer some more detail on the next update, we wish to address the uncertainty the community's been having about if the ASICs are even real, mostly due to our competition failing to meet the deadlines. Recently it has been happening more often in which I had to defend the Avalon image from general statements on ASICs are delayed again and other false accusations.

In this light, we have contacted our foundry, TSMC and Fujitsu who is handling our chip packaging to provide a copy of our original contracts with them to produce the Avalon ASICs. We hope this will provide some comfort and trust with our potential customers.

Again, the reason we do not wish to release pictures such as our board design and such is purely for competitive reasons, especially now that we known bASIC has yet to complete their board.

Our demonstration is still scheduled to happen around the end of the year, then soon 1-2 weeks after the demo, Shipping will begin.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on November 28, 2012, 10:16:52 AM
Question:

Does your team [Avalon] currently possess a prototype that is currently functional at this time? (not a simulation, but a working prototype?)

Second Follow up Question:

If so, does the device work as expected? Are there any known flaws or issues with the underlying hardware at this time?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: thorvald on November 28, 2012, 10:53:32 AM
Question:

Does your team [Avalon] currently possess a prototype that is currently functional at this time? (not a simulation, but a working prototype?)

Second Follow up Question:

If so, does the device work as expected? Are there any known flaws or issues with the underlying hardware at this time?

+1


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: punin on November 28, 2012, 11:18:04 AM
They just stated that the demo unit will be ready around new year. It seems they're doing a shared wafer run (hence the small number of chips/batch). This is the cheapest and only way of creating a working ASIC prototype and also the right thing to do in general. Looking good for team Avalon. If they get it right on their first try, I doubt they'll be missing deadlines. If not, at least they haven't burned shitloads of money on a garbage mask-set.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on November 28, 2012, 11:42:49 AM
I wish them well, as I too would like to see them be the first out the door with ASICs.

Still, I wonder if they have a working prototype at this point. I understand their want for secrecy. I just want to know how far they have advanced to date. A working prototype is a very good sign.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ngzhang on November 29, 2012, 04:53:47 PM
I think the demonstration event has been mentioned at the first (around late Sep. ?). but please let Yifu to re-explain it later, he is at the meeting in Macau.

and all I can say is our project is going well.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Turbor on November 29, 2012, 06:58:06 PM
and all I can say is our project is going well.

Good to hear. Team China FTW  :D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 29, 2012, 07:15:06 PM
I think the demonstration event has been mentioned at the first (around late Sep. ?). but please let Yifu to re-explain it later, he is at the meeting in Macau
http://pbs.twimg.com/media/A8v_9YmCYAAPMgv.jpg

 (in order from left to right, and bottom to top) Ira from BitInstant, Thomas from NEFT vodka, Roger from memeorydealers, Eric from BitInstant, Kelvin from http://bitcoins.co.kr/, ME, and Charlie from Bitinstant and Bill from Calvin Ayre.

Back to work mode after Dec 2nd. Yes, everything is going smoothly


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Aseras on November 29, 2012, 09:22:51 PM
How many clock buffers does the avalon have? Will if have more than BFL? Can you upgrade our clock buffer count so we can be more competitive?

:D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Dexter770221 on November 29, 2012, 11:17:53 PM
... Can you upgrade our clock buffer count so we can be more competitive?
And that must be in software side of things of course ;)
Just add a scroll list in software somwhere. "Clock buffers: 1,2,4,8,16...2^xxyy"


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on November 30, 2012, 03:45:51 AM
Seriously NO ONE goes to Macau for a business meeting, other than the wrong sort of people.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on November 30, 2012, 04:14:16 AM
I think the demonstration event has been mentioned at the first (around late Sep. ?). but please let Yifu to re-explain it later, he is at the meeting in Macau
http://pbs.twimg.com/media/A8v_9YmCYAAPMgv.jpg

Which one is you?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on November 30, 2012, 06:03:12 AM
I think the demonstration event has been mentioned at the first (around late Sep. ?). but please let Yifu to re-explain it later, he is at the meeting in Macau
http://pbs.twimg.com/media/A8v_9YmCYAAPMgv.jpg

Which one is you?
Better question:

Who is each individual at the table? What do they each do for Avalon?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: luffy on November 30, 2012, 06:41:51 AM
easy!
they are just eating our pre orders!  ;D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ngzhang on November 30, 2012, 08:30:32 AM
easy!
they are just eating our pre orders!  ;D

 ;D
Absolutely not. Yifu attend a meeting in Macau these days, about BTC environment and economy, no direct relation with Avalon project.

when he is having a big dinner on that table,  Avalon team is at Beijing, China, working hard and eating instant noodles.  :(


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on November 30, 2012, 08:33:47 AM
easy!
they are just eating our pre orders!  ;D

 ;D
Absolutely not. Yifu attend a meeting in Macau these days, about BTC environment and economy, no direct relation with Avalon project.

when he is having a big dinner on that table,  Avalon team is at Beijing, China, working hard and eating instant noodles.  :(

We know:)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 30, 2012, 11:18:03 AM
Seriously NO ONE goes to Macau for a business meeting, other than the wrong sort of people.

I suppose by your cynic logic, and prejudice attitude (in order from left to right, and bottom to top) Ira from BitInstant, Thomas from NEFT vodka, Roger from memeorydealers, Eric from BitInstant, Kelvin from http://bitcoins.co.kr/, ME, and Charlie from Bitinstant is the wrong sort of people.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on November 30, 2012, 11:50:31 AM
@ Bitsyncom (Yifu G.)

Thank you for identifying the individuals in the picture.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on November 30, 2012, 11:54:59 AM
Question:

Will the Avalon Devices meet basic FCC requirements? (or any other European/Eurasian required certifications in various nations)

I ask just to be sure there won't be any import/certified issues.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on November 30, 2012, 12:52:25 PM
Seriously NO ONE goes to Macau for a business meeting, other than the wrong sort of people.

I suppose by your cynic logic, and prejudice attitude (in order from left to right, and bottom to top) Ira from BitInstant, Thomas from NEFT vodka, Roger from memeorydealers, Eric from BitInstant, Kelvin from http://bitcoins.co.kr/, ME, and Charlie from Bitinstant is the wrong sort of people.


Hmmm..... I think doing business in this region for over 25 years, gives me just a little perspective on the business practices of the Pearl Delta.
But perhaps brush up a little 武經七書... because I got what I needed faster than I expected.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on November 30, 2012, 01:24:23 PM
Hmmm..... I think doing business in this region for over 25 years, gives me just a little perspective on the business practices of the Pearl Delta.
But perhaps brush up a little 武經七書... because I got what I needed faster than I expected.


I think you have no sense of humility after doing business for 25 years in these regions that you lost the ability to talk to another person like a regular human being. I had no intention to hide who these people were, I simply uploaded the picture from my phone on-the-go and now had the chance to do a proper follow up, not to mention many of these faces are not new and often seen in public involving bitcoin.

It would be much appreciated in the future, especially when directing questions at me. Brush up on how to be a gentleman, remove any trace of prejudice and cynicism you have obtained from a past that has nothing to do with me.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: server on November 30, 2012, 01:39:03 PM
Hey guys, generation and culture conflict maybe...

I think the new generation entrepreneurs should be able to make their own mistakes ;D

btw nice pic thanks !


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on November 30, 2012, 10:57:40 PM
Seriously NO ONE goes to Macau for a business meeting, other than the wrong sort of people.

I suppose by your cynic logic, and prejudice attitude (in order from left to right, and bottom to top) Ira from BitInstant, Thomas from NEFT vodka, Roger from memeorydealers, Eric from BitInstant, Kelvin from http://bitcoins.co.kr/, ME, and Charlie from Bitinstant is the wrong sort of people.

I like associating faces to names, thanks. But you named 7 persons while there are 8 at the table. Who is the 8th?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on November 30, 2012, 10:58:35 PM
Seriously NO ONE goes to Macau for a business meeting, other than the wrong sort of people.

I suppose by your cynic logic, and prejudice attitude (in order from left to right, and bottom to top) Ira from BitInstant, Thomas from NEFT vodka, Roger from memeorydealers, Eric from BitInstant, Kelvin from http://bitcoins.co.kr/, ME, and Charlie from Bitinstant is the wrong sort of people.

I like associating faces to names, thanks. But you named 7 persons while there are 8 at the table. Who is the 8th?
Satoshi, obviously.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Frequency on December 01, 2012, 12:24:05 AM
Looks like half the audiance is sleeping  in that pic. :D


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: eldentyrell on December 01, 2012, 10:07:56 AM
Have you had a chance to post these figures?

Yes, awhile ago.

https://bitcointalk.org/index.php?topic=120184.msg1323704#msg1323704

Sorry, I quoted the wrong post (my fault!).  By "these figures", I meant to quote this post:


And the other necessary piece of information: how many of these 15(mm2) chips are in your 66Gh/s product?

So… how many 15(mm2) chips are in your 66Gh/s product?  Without this number it's impossible to connect the hashrate or product price with any of the other figures you've posted.


Title: Re: [Announcement] Avalon ASIC Development Status
Post by: BitSyncom on December 01, 2012, 10:25:15 AM
And the other necessary piece of information: how many of these 15(mm2) chips are in your 66Gh/s product?

So… how many 15(mm2) chips are in your 66Gh/s product?  Without this number it's impossible to connect the hashrate or product price with any of the other figures you've posted.

Disregard, this information no longer apply. To provide a better explanation, we used a modular design so the number of chips on the Unit is not yet final, we are still playing around the numbers to get the best power consumption vs. hash-rate.

I have posted this awhile ago too, once we have finalized numbers we will be happy to provide this information.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 05, 2012, 03:38:06 PM
Is update #5 scheduled for this week?

Any updates?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 05, 2012, 03:57:04 PM
Is update #5 scheduled for this week?

Any updates?

Pretty ironic as I am currently drafting the thread. You'll have to wait a bit as it is fairly lengthy and I'm still deciding what to say exactly due to some newly obtained knowledge from our Fab that are very different what the competition has been saying. I am obtaining more concrete information e.g. our whole process, initial TSMC contract, MT Form ( aka things that can only obtained by going through the Fab process and can be identified by other people with experience that can validate. ) used to back our calms. As I stated previously, my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them and maybe present a proper argument.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: CoinHoarder on December 05, 2012, 05:32:32 PM
Pretty ironic as I am currently drafting the thread. You'll have to wait a bit as it is fairly lengthy and I'm still deciding what to say exactly due to some newly obtained knowledge from our Fab that are very different what the competition has been saying. I am obtaining more concrete information e.g. our whole process, initial TSMC contract, MT Form ( aka things that can only obtained by going through the Fab process and can be identified by other people with experience that can validate. ) used to back our calms. As I stated previously, my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them and maybe present a proper argument.

Interesting... I am anxiously awaiting this!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 05, 2012, 05:35:48 PM
<subscribed>


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Aseras on December 05, 2012, 06:42:07 PM
Can't wait. Also cancel some more orders so I can buy more avalons :D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Mikej0h on December 05, 2012, 08:13:03 PM
Pretty ironic as I am currently drafting the thread. You'll have to wait a bit as it is fairly lengthy and I'm still deciding what to say exactly due to some newly obtained knowledge from our Fab that are very different what the competition has been saying. I am obtaining more concrete information e.g. our whole process, initial TSMC contract, MT Form ( aka things that can only obtained by going through the Fab process and can be identified by other people with experience that can validate. ) used to back our calms. As I stated previously, my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them and maybe present a proper argument.

Where do you post these updates?
I'm a Avalon/BitSyncom customer, but not sure where to receive this information from...

By forumpost? By e-mail?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 05, 2012, 08:20:21 PM
Where do you post these updates?
I'm a Avalon/BitSyncom customer, but not sure where to receive this information from...

By forumpost? By e-mail?

It will be posted in this thread. It is the development status thread after all.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Dhomochevsky on December 05, 2012, 09:03:48 PM
Putting this thread on my watchlist, and eagerly waiting the next update.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: libertybuck on December 05, 2012, 10:56:18 PM

Pretty ironic as I am currently drafting the thread. You'll have to wait a bit as it is fairly lengthy and I'm still deciding what to say exactly due to some newly obtained knowledge from our Fab that are very different what the competition has been saying. I am obtaining more concrete information e.g. our whole process, initial TSMC contract, MT Form ( aka things that can only obtained by going through the Fab process and can be identified by other people with experience that can validate. ) used to back our calms. As I stated previously, my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them and maybe present a proper argument.

Interesting ...

Waitting for the coming news ......


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on December 06, 2012, 02:39:56 AM

Pretty ironic as I am currently drafting the thread. You'll have to wait a bit as it is fairly lengthy and I'm still deciding what to say exactly due to some newly obtained knowledge from our Fab that are very different what the competition has been saying. I am obtaining more concrete information e.g. our whole process, initial TSMC contract, MT Form ( aka things that can only obtained by going through the Fab process and can be identified by other people with experience that can validate. ) used to back our calms. As I stated previously, my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them and maybe present a proper argument.

Interesting ...

Waitting for the coming news ......

Very interesting. It almost sounds like he was expecting worse and didn't believe the good numbers of the other vendors, but now is expecting Avalon to be better than advertised.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 06, 2012, 07:07:12 AM
Very interesting. It almost sounds like he was expecting worse and didn't believe the good numbers of the other vendors, but now is expecting Avalon to be better than advertised.

Avalon is, and always have been better than advertised, this was the style of our press release to give conservative estimates and improve the numbers as we eliminate potential and actual problems. Regardless, what I'm talking about is actually the very opposite, now looking at the evidence presented by our engineering team, our competitors have very irregular workflows that doesn't make any sense what so ever, in other words, somebody is full of shit.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 06, 2012, 07:09:27 AM
Well stop beating the bush to death and spill it man! ;D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on December 06, 2012, 07:18:57 AM
You guys are all excited, but, to me, it sounds like BitSyncom is about to announce a bad news.

"deciding what to say" -> it is only when the news is bad that time is spent deciding how to say it.

"my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them" -> the "them" refers to his engineering team. IOW the engineering team was skeptical of the competition's power efficiency claims, but BitSyncom disagreed, was more optimistic, and thought it was achievable; however the engineering team now confirmed their skepticism by having numbers showing that their own efficiency will be worse than the competition (which makes sense given that Avalon is 110nm and should be theoretically 3x worse in terms of power efficiency than 65nm (BFL)), so BitSyncom is forced to revise his optimism and forced to agree with his team that Avalon won't be competitive.

"what I'm talking about is actually the very opposite" -> he was expecting better results, but the engineering team's number look bad.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ngzhang on December 06, 2012, 07:21:48 AM
You guys are all excited, but, to me, it sounds like BitSyncom is about to announce a bad news.

"deciding what to say" -> it is only when the news is bad that time is spent deciding how to say it.

"my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them" -> the last "them" refer to his engineering team, IOW the engineering team was correct to be skeptical of the competition's power efficiency claim, IOW the engineering team found out their own efficiency is a lot worse than the competition's claim (which makes sense given that Avalon is 110nm, which should be theoretically 3x worse in terms of power efficiency when compared to 65nm (BFL)).

"what I'm talking about is actually the very opposite" -> he was expecting better results, but the engineering team's number look bad.

yeah, some bad news.  ;)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 06, 2012, 07:23:43 AM
You guys are all excited, but, to me, it sounds like BitSyncom is about to announce a bad news.

"deciding what to say" -> it is only when the news is bad that time is spent deciding how to say it.

"my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them" -> the last "them" refer to his engineering team, IOW the engineering team was correct to be skeptical of the competition's power efficiency claim, IOW the engineering team found out their own efficiency is a lot worse than the competition (which makes sense given that Avalon is 110nm, which should be theoretically 3x worse in terms of power efficiency when compared to 65nm (BFL)).

"what I'm talking about is actually the very opposite" -> he was expecting better results, but the engineering team's number look bad.

Oh indeed, some bad news is coming, but for who I wonder.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on December 06, 2012, 07:28:22 AM
I guess they are pretty bad :P


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 06, 2012, 07:30:33 AM

yeah, some bad news.  ;)
With a smile like that...I am guessing they are about to call BS on certain claims made by other vendors, then list the [technical] reasons why they think it is so?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 06, 2012, 07:31:18 AM
That'd be my take as well. These Avalon guys are having fun milking it anyway. :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on December 06, 2012, 07:36:16 AM
It could be read either way. English is not their primary language, so the semantics of certain sentences is ambiguous. I was just relating how I primarily read and understood BitSyncom's posts.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on December 06, 2012, 07:37:04 AM
I am smiling because i feel the news will be good for us for sure. I do not care about other vendors at all. There is pretty good chance Avalon to be the first! that matters for me. No power consumption no hash rate. It is most likely that they will say something good and push the delivery to happen soon. Once again it is just personal feeling..


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on December 06, 2012, 07:37:19 AM
You guys are all excited, but, to me, it sounds like BitSyncom is about to announce a bad news.

"deciding what to say" -> it is only when the news is bad that time is spent deciding how to say it.

"my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them" -> the last "them" refer to his engineering team, IOW the engineering team was correct to be skeptical of the competition's power efficiency claim, IOW the engineering team found out their own efficiency is a lot worse than the competition (which makes sense given that Avalon is 110nm, which should be theoretically 3x worse in terms of power efficiency when compared to 65nm (BFL)).

"what I'm talking about is actually the very opposite" -> he was expecting better results, but the engineering team's number look bad.
I might be a little tired, but I had a really hard time following you.

Avalon's team's engineers were skeptical of competitors power claims. He chose to plan for the worst and hope for the best, and take the competitors at their word, and temporarily assume the competitor's power draw numbers were accurate. Now however, the Avalon Team's opinions have changed.

So this could mean 2 things:
1) Avalon's competitors really have reached a level of efficiency that the Avalon team can't even get in simulations, and now the Avalon Team has chosen to listen to their engineers and ignore their competitors claims.
2) Avalon's engineering team has made drastic improvements in power efficiency, even into the range that their competitors have been advertising. This means that their competitors were right in their estimates, and means the Avalon's engineering team was previously wrong in their criticism. This also means that the Avalon could be getting lower power numbers than initially estimated?

I'm tired, and so confused.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Starlightbreaker on December 06, 2012, 07:39:23 AM
i always thought it's the first one.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on December 06, 2012, 07:41:59 AM
Hmmm..... I think doing business in this region for over 25 years, gives me just a little perspective on the business practices of the Pearl Delta.
But perhaps brush up a little 武經七書... because I got what I needed faster than I expected.


I think you have no sense of humility after doing business for 25 years in these regions that you lost the ability to talk to another person like a regular human being. I had no intention to hide who these people were, I simply uploaded the picture from my phone on-the-go and now had the chance to do a proper follow up, not to mention many of these faces are not new and often seen in public involving bitcoin.

It would be much appreciated in the future, especially when directing questions at me. Brush up on how to be a gentleman, remove any trace of prejudice and cynicism you have obtained from a past that has nothing to do with me.

Please don't try to give lecture about something you know little about,  I'm very well paid and very good at what I do.

When you have had credible death threats from 'respectable' Asian business men  and attempts to kidnap your wife, come talk to me and we can talk all you want about:
 humility/racism/prejudice/cynicism/corruption/slavery/poisoning of babies/adults for profit or anything else you think you are an expert on.






Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on December 06, 2012, 07:42:23 AM
crazyates,
Just do your math. Having asic in your hands with current difficulty and any power consumption = ROI 2 weeks top
From the other hand having ASIC when dif is 30x-50x (and constantly increasing) with zero power consumption = ROI months or even years

 


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 06, 2012, 07:58:15 AM
You guys are all excited, but, to me, it sounds like BitSyncom is about to announce a bad news.

"deciding what to say" -> it is only when the news is bad that time is spent deciding how to say it.

"my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them" -> the last "them" refer to his engineering team, IOW the engineering team was correct to be skeptical of the competition's power efficiency claim, IOW the engineering team found out their own efficiency is a lot worse than the competition (which makes sense given that Avalon is 110nm, which should be theoretically 3x worse in terms of power efficiency when compared to 65nm (BFL)).

"what I'm talking about is actually the very opposite" -> he was expecting better results, but the engineering team's number look bad.

Oh indeed, some bad news is coming, but who I wonder.
Did some competitors fab or subcontractor company implode or something?

(starts shinning the ol' crystal ball)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 06, 2012, 08:03:17 AM
BFL is supposedly getting chips from Asia next week.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kaerf on December 06, 2012, 08:16:22 AM
and bASIC chips have been done for a while (https://www.btcfpga.com/forum/index.php?topic=203.msg1445#msg1445)



I have orders from all 3...I just want someone to ship, so that I can stop checking the forums every fucking day!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 06, 2012, 08:18:05 AM
and bASIC chips have been done for a while (https://www.btcfpga.com/forum/index.php?topic=203.msg1445#msg1445)



I have orders from all 3...I just want someone to ship, so that I can stop checking the forums every fucking day!
Amen!

That's what I do every day when I am working. Read and wait.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on December 06, 2012, 08:20:43 AM
I might be a little tired, but I had a really hard time following you.

I edited my post to make it more clear: https://bitcointalk.org/index.php?topic=120184.msg1381594#msg1381594


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 06, 2012, 09:04:24 AM
This update is mainly to address the uncertainty that have been surrounding the ASIC scene recently due to the lackluster performance by our competitors. We will be walking you through our process of getting the ASIC fabricated. Unlike our competitors we are a in-house team and everyone is always on the same page.

Another update will address the actual status of our chips as we have obtained word from TSMC whom will offer us weekly updates on their website. All in all, see our arguments below regarding our competitors and wait for weekly updates directly from TSMC.

Anyhow, any of our numbers, estimates, and shipping date have not changed, just in case somebody got the wrong idea about this update.


First things first. the following Gallery is our contract with TSMC with pricing and other sensitive information removed. http://imgur.com/a/DnUNm
http://i.imgur.com/7nIM1s.jpghttp://i.imgur.com/hAfyTs.jpghttp://i.imgur.com/SQGKSs.jpghttp://i.imgur.com/zCeexs.jpg

Some background information on ASIC production process, before tape out, 3 day before uploading GDS (http://en.wikipedia.org/wiki/GDSII), we fill out a MT form with TSMC detailing the ASIC specific information so they may understand what we are doing. The gallery is here http://imgur.com/a/YOLez
http://i.imgur.com/us0iis.jpghttp://i.imgur.com/jKDeKs.jpghttp://i.imgur.com/15pWIs.jpg

to put simply, to create the physical ASIC goes something like this.

sign contract -> submit GDS for review -> mask making -> wafer making -> ship to packaging company -> packaging -> shipping.
Only then can the chips be in your hands or placed on PCB for finalization.

This whole process will take 30-50 days depending on the processor node technology used, mainly due to the increasing in layer number as you go down in processor size. for example, we have 29 layers, and since TSMC is one of the big companies in fabrication, each layer take 1.2 ( normal lot ) day per layer. in addition, accordingly to friedcat, their fab is producing 4 layers every week [odd, but I guess it is possible if fab is small].

This also means while you wait for the wafer(chips) fabrication you can not do anything else, it is usually around this time you make sure you have everything else ready.

a few things to note is,

1. while this wafer making process is going, you can't cancel it, or make adjustments, and if you wish to change anything, you will have to re-run this whole work flow all over again ( the large amount of the NRE upwards of 6 digits in USD is paid when you make the MASK). so anytime, BFL mention they are waiting for chips to come e.g. next week, but if they are still making adjustments, then this is physically impossible. In addition, fabrication company don't do chip packaging, if they are expecting the chips to arrive next week that means the production is already finished and they are probably in the chip packaging company (it is usually this time you find out if your chips work or not. which can also take some time since you'll have to test each of the chips for defects.)

2. the whole chip fabrication is very mathematically predictable based on the number of layers your ASIC has and the speed which the fabrication company can produce a layer. There is no such thing as a fabrication company giving a "fuzzy" date when it comes to when the chips will come from the assembly line. The only number that can vary is the shipping time from the fabrication company to the packaging company, but even that is no more than a few days of difference, depending on the shipping method.

3.a if bASIC made an MPW to start (which is the correct way to save money, but not time). the cost to get large amount of chips during this time is astronomical, however the average size is about 50. It is unheard of for somebody to only produce 2 chips to built a prototype and now no longer have any chips left over to build another prototype.

3.b. Even after testing MWP and everything is fine, it'll take the same amount of time to produce a new MASK ( cost and everything ) then make wafers, which will take another 30 - 50 days, which I suppose is consistent with bASIC's new mid-Jan shipping date, ( but this is optimistic estimate, the regular workflow is about 2 month)

3.c. what we think that happened is bASIC has licensed a SHA256 core, the IP company has already produced demo ASICs that utilizes this core, and did some math on how many core you can placed in the chip to obtain the 14GH/s estimated hashrate, while regular SHA256 and Bitcoin's blockchain hashing algorithm is not very different but it is not something you can compare via simulation without making an actual chip, and if they made an actual chip, even if it doesn't perform up to specifications you can still demonstrate it and be world first.

the conclusion is as follows.

1. If BFL really have chips coming, then they are not making any so-to-speak "clock buffer adjustments", either that or they don't have any chips coming and have not tape-out at all, it is also entirely possible that they have not make the MASK yet either. I guess we will find out on the week of the 11th, in this month hopefully.

2. we believe bASIC has no prototype, or have any chips. Also we at Avalon have also explored the possibility of licensing an IP core, but after some in-house comparison, none of the core on the market is superior to our own, thus we eliminated that option.

Questions, Comments are welcome.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 06, 2012, 09:32:20 AM
Oh, TSMC is using 300mm wafers. That is good to know.

Edit: Why does it say under one of the (online forms) that it failed the DRC check? (Design Rule Check)

Is that because you did something unusual with the chip that the DRC would fail the automatic checks?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on December 06, 2012, 09:50:12 AM
Thank for sharing the info.

However you did not black out the top pixel line of the price digits, so we can still make them out by comparing them with other non-obscured digits in the document (I almost wonder if you did this intentionally):


Pilot / Engineering Wafer Lot Price = either $1x,xxx.xx or $4x,xxx.xx
Production Wafer Unit Price = $4,xxx.xx
Mask Set Price = $2xx,xxx


It is probably possible to make out some of the unknown 'x' digits by counting the spacing between the pixels, but I was too lazy to do it. The most significantly digit is the most important one anyway.

This price quote is a proof to people who don't believe that ASICs are cheap to manufacture, after NRE costs are recovered. A 12-inch wafer costs $4k for Avalon. They will likely make about a thousand chips per wafer assuming a 50 mm² die. Which means each chip technically costs about $4. There is going to be ten chips or so per Avalon device, so $40 of ASIC chips in a device that is sold $1300. That's a profit margin of $1260! (I am simplying here, there are other minor costs: chip packaging, other components, PCB, etc, maybe $100-$200 maximum). Of course this insane profit margin is only valid once NRE costs ($200k+) are recovered. But some/all ASIC vendors will eventually recover them... so expect ASIC prices to eventually drop massively.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 06, 2012, 10:05:38 AM
Thank for sharing the info.

However you did not black out the top pixel line of the price digits, so we can still make them out by comparing them with other non-obscured digits in the document:

Pilot / Engineering Wafer Lot Price = either $1x,xxx.xx or $4x,xxx.xx
Production Wafer Unit Price = $4,xxx.xx
Mask Set Price = $2xx,xxx

It is probably possible to make out some of the unknown 'x' digits by counting the spacing between the pixels, but I was too lazy to do it. The most significantly digit is the most important one anyway.

This price quote is a proof to people who don't believe that ASICs are cheap to manufacture, after NRE costs are recovered. A 12-inch wafer costs $4k for Avalon. They will likely make about a thousand chips per wafer assuming a 50 mm² die. Which means each chip technically costs about $4. There is going to be ten chips or so per Avalon device, so $40 of ASIC chips in a device that is sold $1300. That's a profit margin of $1260! (I am simplying here, there are other minor costs: chip packaging, other components, PCB, etc, maybe $100-$200 maximum). Of course this insane profit margin is only valid once NRE costs ($200k+) are recovered. But some/all ASIC vendors will eventually recover them... so expect ASIC prices to eventually drop massively.

Actually this is very wrong, at this point in time, when we initially made the 300 order limitation, we were right at our break even point, and currently due to fees and other some problems, we are in fact in the red. Also while we can not reveal our chip numbers per unit, but it is much greater than 10 chips. Everyone is simply under the impression that 7GH/s chips are the "norm" due to what I believe to be false advertisement by the competition.

If you can get me those other components you mentioned like PCB, PSU and other stuff for 100-200 dollars maximum, maybe we should hire you to manage our component purchasing! a single good PSU is near $100...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on December 06, 2012, 10:10:15 AM
Thank for sharing the info.

However you did not black out the top pixel line of the price digits, so we can still make them out by comparing them with other non-obscured digits in the document:

Pilot / Engineering Wafer Lot Price = either $1x,xxx.xx or $4x,xxx.xx
Production Wafer Unit Price = $4,xxx.xx
Mask Set Price = $2xx,xxx

It is probably possible to make out some of the unknown 'x' digits by counting the spacing between the pixels, but I was too lazy to do it. The most significantly digit is the most important one anyway.

This price quote is a proof to people who don't believe that ASICs are cheap to manufacture, after NRE costs are recovered. A 12-inch wafer costs $4k for Avalon. They will likely make about a thousand chips per wafer assuming a 50 mm² die. Which means each chip technically costs about $4. There is going to be ten chips or so per Avalon device, so $40 of ASIC chips in a device that is sold $1300. That's a profit margin of $1260! (I am simplying here, there are other minor costs: chip packaging, other components, PCB, etc, maybe $100-$200 maximum). Of course this insane profit margin is only valid once NRE costs ($200k+) are recovered. But some/all ASIC vendors will eventually recover them... so expect ASIC prices to eventually drop massively.

Actually this is very wrong, at this point in time, when we initially made the 300 order limitation, we were right at our break even point, and currently due to fees and other some problems, we are in fact in the red. Also while we can not reveal our chip numbers per unit, but it is much greater than 10 chips. Everyone is simply under the impression that 7GH/s chips are the "norm".

If you can get me those other components you mentioned like PCB, PSU and other stuff for 100-200 dollars maximum, maybe we should hire you to manage our component purchasing! a single good PSU is near $100...

Of course, I am simplifying and ignoring other costs: human resources (engineers), shipping, assembly, etc. And yes Avalon, as a standalone device, is a more complex/expensive than the competition devices, so add $100-150 to my numbers as I wasn't thinking about it. I have no doubt all ASIC companies are in the red initially. It will take you guys months to start being in the black. But after that point, you do agree with me that it will be mainly profits... (and good for you! or else you would not have started the business venture at all).

(PS: the number of chips per Avalon is mostly irrevelant to these price estimations. I estimate you will have about 500mm² of die area per Avalon device. Whether it is 10 x 50mm² chips or 20 x 25 mm² chips is irrelevant to my numbers. 500mm² of wafer space will cost $40 regardless.)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 06, 2012, 10:17:39 AM


This price quote is a proof to people who don't believe that ASICs are cheap to manufacture, after NRE costs are recovered. A 12-inch wafer costs $4k for Avalon. They will likely make about a thousand chips per wafer assuming a 50 mm² die. Which means each chip technically costs about $4. There is going to be ten chips or so per Avalon device, so $40 of ASIC chips in a device that is sold $1300. That's a profit margin of $1260! (I am simplying here, there are other minor costs: chip packaging, other components, PCB, etc, maybe $100-$200 maximum). Of course this insane profit margin is only valid once NRE costs ($200k+) are recovered. But some/all ASIC vendors will eventually recover them... so expect ASIC prices to eventually drop massively.
I thought they said their chips were 15mm²?

That would be a boatload of chips on a 300mm wafer.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: beekeeper on December 06, 2012, 11:09:37 AM
Yeah, it seems its 50mm^2 packed:
Quote
Package Type: QFN48 -0.5 Pitch
Packaged Chip Size: 7 mm x 7 mm
So chip price will be something like 1usd and some pennies.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: meowmeowbrowncow on December 06, 2012, 11:53:49 AM
Thank for sharing the info.

However you did not black out the top pixel line of the price digits, so we can still make them out by comparing them with other non-obscured digits in the document:

Pilot / Engineering Wafer Lot Price = either $1x,xxx.xx or $4x,xxx.xx
Production Wafer Unit Price = $4,xxx.xx
Mask Set Price = $2xx,xxx

It is probably possible to make out some of the unknown 'x' digits by counting the spacing between the pixels, but I was too lazy to do it. The most significantly digit is the most important one anyway.

This price quote is a proof to people who don't believe that ASICs are cheap to manufacture, after NRE costs are recovered. A 12-inch wafer costs $4k for Avalon. They will likely make about a thousand chips per wafer assuming a 50 mm² die. Which means each chip technically costs about $4. There is going to be ten chips or so per Avalon device, so $40 of ASIC chips in a device that is sold $1300. That's a profit margin of $1260! (I am simplying here, there are other minor costs: chip packaging, other components, PCB, etc, maybe $100-$200 maximum). Of course this insane profit margin is only valid once NRE costs ($200k+) are recovered. But some/all ASIC vendors will eventually recover them... so expect ASIC prices to eventually drop massively.

Actually this is very wrong, at this point in time, when we initially made the 300 order limitation, we were right at our break even point, and currently due to fees and other some problems, we are in fact in the red. Also while we can not reveal our chip numbers per unit, but it is much greater than 10 chips. Everyone is simply under the impression that 7GH/s chips are the "norm" due to what I believe to be false advertisement by the competition.

If you can get me those other components you mentioned like PCB, PSU and other stuff for 100-200 dollars maximum, maybe we should hire you to manage our component purchasing! a single good PSU is near $100...


With the quality of disclosure coming from Avalon I'm starting to believe this to be true.  And I'm getting pissed.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: meowmeowbrowncow on December 06, 2012, 12:55:40 PM



If you guys at Avalon are confident of your process, tech and timeline why wouldn't you open up more capacity to accept orders from disenchanted customers of competitors?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on December 06, 2012, 01:01:26 PM
I wonder what price BFL is getting their 300mm 65nm wafers for, if Avalon is paying 4k for a 110nm wafer? Even if they pay half of what Avalon is due to their higher volume, their 100k chip order would be worth $200k.
They better hope the chips work this time.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 06, 2012, 01:12:46 PM
This update is mainly to address the uncertainty that have been surrounding the ASIC scene recently due to the lackluster performance by our competitors. We will be walking you through our process of getting the ASIC fabricated. Unlike our competitors we are a in-house team and everyone is always on the same page.

Another update will address the actual status of our chips as we have obtained word from TSMC whom will offer us weekly updates on their website. All in all, see our arguments below regarding our competitors and wait for weekly updates directly from TSMC.

Anyhow, any of our numbers, estimates, and shipping date have not changed, just in case somebody got the wrong idea about this update.


First things first. the following Gallery is our contract with TSMC with pricing and other sensitive information removed. http://imgur.com/a/DnUNm
http://i.imgur.com/7nIM1s.jpghttp://i.imgur.com/hAfyTs.jpghttp://i.imgur.com/SQGKSs.jpghttp://i.imgur.com/zCeexs.jpg

Some background information on ASIC production process, before tape out, 3 day before uploading GDS (http://en.wikipedia.org/wiki/GDSII), we fill out a MT form with TSMC detailing the ASIC specific information so they may understand what we are doing. The gallery is here http://imgur.com/a/YOLez
http://i.imgur.com/us0iis.jpghttp://i.imgur.com/jKDeKs.jpghttp://i.imgur.com/15pWIs.jpg

to put simply, to create the physical ASIC goes something like this.

sign contract -> submit GDS for review -> mask making -> wafer making -> ship to packaging company -> packaging -> shipping.
Only then can the chips be in your hands or placed on PCB for finalization.

This whole process will take 30-50 days depending on the processor node technology used, mainly due to the increasing in layer number as you go down in processor size. for example, we have 29 layers, and since TSMC is one of the big companies in fabrication, each layer take 1.2 ( normal lot ) day per layer. in addition, accordingly to friedcat, their fab is producing 4 layers every week [odd, but I guess it is possible if fab is small].

This also means while you wait for the wafer(chips) fabrication you can not do anything else, it is usually around this time you make sure you have everything else ready.

a few things to note is,

1. while this wafer making process is going, you can't cancel it, or make adjustments, and if you wish to change anything, you will have to re-run this whole work flow all over again ( the large amount of the NRE upwards of 6 digits in USD is paid when you make the MASK). so anytime, BFL mention they are waiting for chips to come e.g. next week, but if they are still making adjustments, then this is physically impossible. In addition, fabrication company don't do chip packaging, if they are expecting the chips to arrive next week that means the production is already finished and they are probably in the chip packaging company (it is usually this time you find out if your chips work or not. which can also take some time since you'll have to test each of the chips for defects.)

2. the whole chip fabrication is very mathematically predictable based on the number of layers your ASIC has and the speed which the fabrication company can produce a layer. There is no such thing as a fabrication company giving a "fuzzy" date when it comes to when the chips will come from the assembly line. The only number that can vary is the shipping time from the fabrication company to the packaging company, but even that is no more than a few days of difference, depending on the shipping method.

3.a if bASIC made an MPW to start (which is the correct way to save money, but not time). the cost to get large amount of chips during this time is astronomical, however the average size is about 50. It is unheard of for somebody to only produce 2 chips to built a prototype and now no longer have any chips left over to build another prototype.

3.b. Even after testing MWP and everything is fine, it'll take the same amount of time to produce a new MASK ( cost and everything ) then make wafers, which will take another 30 - 50 days, which I suppose is consistent with bASIC's new mid-Jan shipping date, ( but this is optimistic estimate, the regular workflow is about 2 month)

3.c. what we think that happened is bASIC has licensed a SHA256 core, the IP company has already produced demo ASICs that utilizes this core, and did some math on how many core you can placed in the chip to obtain the 14GH/s estimated hashrate, while regular SHA256 and Bitcoin's blockchain hashing algorithm is not very different but it is not something you can compare via simulation without making an actual chip, and if they made an actual chip, even if it doesn't perform up to specifications you can still demonstrate it and be world first.

the conclusion is as follows.

1. If BFL really have chips coming, then they are not making any so-to-speak "clock buffer adjustments", either that or they don't have any chips coming and have not tape-out at all, it is also entirely possible that they have not make the MASK yet either. I guess we will find out on the week of the 11th, in this month hopefully.

2. we believe bASIC has no prototype, or have any chips. Also we at Avalon have also explored the possibility of licensing an IP core, but after some in-house comparison, none of the core on the market is superior to our own, thus we eliminated that option.

Questions, Comments are welcome.
To better understand what the Avalon team is trying to say in the above points. I have linked to a simple video explanation of how Wafers are made and why it takes such a long time to make Chips (of almost any variety).

http://www.youtube.com/watch?v=aWVywhzuHnQ
http://www.youtube.com/watch?v=xftnhfa-Dmo
http://www.youtube.com/watch?v=rcYQIhG6d8U

Educate yourselves so that when the "spin" comes [from other vendors], you'll know what they are actually talking about [in their excuses].


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ngzhang on December 06, 2012, 01:14:51 PM
I wonder what price BFL is getting their 300mm 65nm wafers for, if Avalon is paying 4k for a 110nm wafer? Even if they pay half of what Avalon is due to their higher volume, their 100k chip order would be worth $200k.
They better hope the chips work this time.

i think the wafer cost is rather low than the MASK cost @ 65nm.. ...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 06, 2012, 01:22:06 PM
@ Ngzhang

Why does it say under one of the (online forms) that it failed the DRC check? (Design Rule Check)

Is that because you did something unusual with the chip that the DRC would fail the automatic checks?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ngzhang on December 06, 2012, 01:27:30 PM
@ Ngzhang

Why does it say under one of the (online forms) that it failed the DRC check? (Design Rule Check)

Is that because you did something unusual with the chip that the DRC would fail the automatic checks?


never mind, it's just a option to avoid some unnecessary trouble. 


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 06, 2012, 01:32:34 PM
If you guys at Avalon are confident of your process, tech and timeline why wouldn't you open up more capacity to accept orders from disenchanted customers of competitors?

Let me explain to you what our timeline actually looks like, so you may get a better picture.

We plan to ship at Jan 14th, 2013. Hopefully finish shipping all 300 before Chinese New Year holiday. To foresee some potential problems, we originally announced we will finish shipping all 300 units before End of February 2013 for exactly this reason. Therefore, due to this holiday, we will have a large delay between when the second shipment can start, which is estimated at Feb 24th currently.

It is because we are so confident we will not be taking your money so early and not ship any goods, especially when it is some delay that is beyond our control.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: meowmeowbrowncow on December 06, 2012, 01:40:04 PM
If you guys at Avalon are confident of your process, tech and timeline why wouldn't you open up more capacity to accept orders from disenchanted customers of competitors?

Let me explain to you what our timeline actually looks like, so you may get a better picture.

We plan to ship at Jan 14th, 2013. Hopefully finish shipping all 300 before Chinese New Year holiday. To foresee some potential problems, we originally announced we will finish shipping all 300 units before End of February 2013 for exactly this reason. Therefore, due to this holiday, we will have a large delay between when the second shipment can start, which is estimated at Feb 24th currently.

It is because we are so confident we will not be taking your money so early and not ship any goods, especially it is some delay that is beyond our control.


Ok, fair enough.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 06, 2012, 01:44:05 PM


It is because we are so confident we will not be taking your money so early and not ship any goods, especially when it is some delay that is beyond our control.
That is a pretty damn honest reason. (Wish BFL would do the same!)

When does the Chinese New Year Holiday Start and End?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on December 06, 2012, 01:44:39 PM
I wonder what price BFL is getting their 300mm 65nm wafers for, if Avalon is paying 4k for a 110nm wafer? Even if they pay half of what Avalon is due to their higher volume, their 100k chip order would be worth $200k.
They better hope the chips work this time.

i think the wafer cost is rather low than the MASK cost @ 65nm.. ...
Maybe I was misunderstood. BFL is probably getting around 1000 chips out of a 300mm wafer, so their order for a 100k chips would be about 100 wafers. The mask costs will be large, but ordering a couple to several hundred thousand dollars worth of wafers on top of your mask costs without doing a small run to test it just seems very risky.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 06, 2012, 02:09:27 PM
When does the Chinese New Year Holiday Start and End?

Chinese New Year officially starts on the 8th of February and ends on the 14th, but this is a very big holiday in China. We do not expect things to return to normal until at least ten day later, which is our second batch expected shipping date.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: abeaulieu on December 06, 2012, 02:19:06 PM
@ Ngzhang

Why does it say under one of the (online forms) that it failed the DRC check? (Design Rule Check)

Is that because you did something unusual with the chip that the DRC would fail the automatic checks?


never mind, it's just a option to avoid some unnecessary trouble. 

Well let's hope it doesn't cause any unnecessary trouble. Letting some things through DRC can cause people to overlook an important thing or two.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: AndrewBUD on December 06, 2012, 02:25:15 PM
I love how much detail you guys release. Great job :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: CoinHoarder on December 06, 2012, 05:23:08 PM
It's interesting to hear your point of view of the competitors. My opinion is similar, but I am a customer so I'm biased.

I agree bASIC/BFL have been doing shady things, they lost my trust weeks ago.

Keep doing honest business Avalon, and the customers will come.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: SgtSpike on December 06, 2012, 05:51:54 PM
1. If BFL really have chips coming, then they are not making any so-to-speak "clock buffer adjustments", either that or they don't have any chips coming and have not tape-out at all, it is also entirely possible that they have not make the MASK yet either. I guess we will find out on the week of the 11th, in this month hopefully.
My understanding is that these clock buffer adjustments were made as soon as they figured out their first batch of chips wouldn't work (late October).  They aren't still making any adjustments, they are just waiting on the newly-adjusted chips to arrive.


I wonder what price BFL is getting their 300mm 65nm wafers for, if Avalon is paying 4k for a 110nm wafer? Even if they pay half of what Avalon is due to their higher volume, their 100k chip order would be worth $200k.
They better hope the chips work this time.

i think the wafer cost is rather low than the MASK cost @ 65nm.. ...
Maybe I was misunderstood. BFL is probably getting around 1000 chips out of a 300mm wafer, so their order for a 100k chips would be about 100 wafers. The mask costs will be large, but ordering a couple to several hundred thousand dollars worth of wafers on top of your mask costs without doing a small run to test it just seems very risky.
It is quite a cost, but consider that timing is everything in this ASIC battle.  BFL spending a couple hundred thousand to avoid having to way 4-6 weeks for a sample to be cut and THEN order new wafers and wait for those as well could be a smart move.  Making customers wait another 4-6 weeks could be a reputation killer, and $200k might be a small price to pay to keep their existing preorders and reputation intact.  I'm sure they don't like that they had to spend that much money, but they couldn't wait for new samples before putting in an order for their new wafers - it would kill them as a competitor in this race.  I'm sure they're crossing their fingers that the new chips work just as much as everyone who ordered from them is.  ;)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Aseras on December 06, 2012, 05:59:23 PM
My understanding is that these clock buffer adjustments were made as soon as they figured out their first batch of chips wouldn't work (late October).  They aren't still making any adjustments, they are just waiting on the newly-adjusted chips to arrive.

It is quite a cost, but consider that timing is everything in this ASIC battle.  BFL spending a couple hundred thousand to avoid having to way 4-6 weeks for a sample to be cut and THEN order new wafers and wait for those as well could be a smart move.  Making customers wait another 4-6 weeks could be a reputation killer, and $200k might be a small price to pay to keep their existing preorders and reputation intact.  I'm sure they don't like that they had to spend that much money, but they couldn't wait for new samples before putting in an order for their new wafers - it would kill them as a competitor in this race.  I'm sure they're crossing their fingers that the new chips work just as much as everyone who ordered from them is.  ;)

you don't adjust chips. period.

You can add crap the the board to fix a leak or add voltage or capacitance. That's about it. If there was anything wrong with the chips whatsoever it's a respin at best, and worse a whole redo of the mask. That's 30-90 days of fail.

so everyone who gets a first gen BFL SC before whatever the real problem is fixed is getting a quick fix prototype board at best.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: SgtSpike on December 06, 2012, 06:07:50 PM
My understanding is that these clock buffer adjustments were made as soon as they figured out their first batch of chips wouldn't work (late October).  They aren't still making any adjustments, they are just waiting on the newly-adjusted chips to arrive.

It is quite a cost, but consider that timing is everything in this ASIC battle.  BFL spending a couple hundred thousand to avoid having to way 4-6 weeks for a sample to be cut and THEN order new wafers and wait for those as well could be a smart move.  Making customers wait another 4-6 weeks could be a reputation killer, and $200k might be a small price to pay to keep their existing preorders and reputation intact.  I'm sure they don't like that they had to spend that much money, but they couldn't wait for new samples before putting in an order for their new wafers - it would kill them as a competitor in this race.  I'm sure they're crossing their fingers that the new chips work just as much as everyone who ordered from them is.  ;)

you don't adjust chips. period.

You can add crap the the board to fix a leak or add voltage or capacitance. That's about it. If there was anything wrong with the chips whatsoever it's a respin at best, and worse a whole redo of the mask. That's 30-90 days of fail.

so everyone who gets a first gen BFL SC before whatever the real problem is fixed is getting a quick fix prototype board at best.
That's exactly what they said it was - a respin.  And that's exactly how long it is taking - 30-90 days (specifically, I'd say about 50 days at this point from late October to December 11th).  So why do you think it is NOT a respin or mask do-over?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 06, 2012, 06:10:28 PM
So what was supposed to take 25 days from Halloween?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bitcoindaddy on December 06, 2012, 06:12:36 PM
I wish all of the ASIC bitcoin companies were this open and honest about their process and status. Everyone would sleep more soundly.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on December 06, 2012, 06:14:17 PM
I wish all of the ASIC bitcoin companies were this open and honest about their process and status. Everyone would sleep more soundly.
I sleep just fine, tyvm. Maybe you should see a doctor?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ewibit on December 06, 2012, 06:15:33 PM
I wish all of the ASIC bitcoin companies were this open and honest about their process and status. Everyone would sleep more soundly.
+1
yes this could be fine for us


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 06, 2012, 06:16:48 PM
...and for this bASIC customer. Stress is high, though it'd be higher if deadlines were made and broken every two weeks instead of two months.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 06, 2012, 06:44:01 PM
The BFL reps responded to one of Avalons claims...with very vague mentions of a ~unique~ workflow arrangement enabling them to do...well, the impossible. (IMO)

https://forums.butterflylabs.com/bfl-forum-miscellaneous/500-josh-plz-give-us-some-comments-about.html#post7363


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 06, 2012, 06:47:54 PM
Actually I'm beginning to believe that's *THE ONLY* BFL rep and his response was as usual completely meaningless.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Starlightbreaker on December 06, 2012, 08:17:05 PM
The BFL reps responded to one of Avalons claims...with very vague mentions of a ~unique~ workflow arrangement enabling them to do...well, the impossible. (IMO)

https://forums.butterflylabs.com/bfl-forum-miscellaneous/500-josh-plz-give-us-some-comments-about.html#post7363
hm..

Quote

While I appreciate the technical prowess of the Avalon team, the fact of the matter is they simply don't have the resources or experience we have in this area.


HAHAHAHAHAHAHAHAHAHAHAHA


*deep breath*
...oh shit.

HAHAHAHAHAHAHAHAHAHAHAHHAHAHAHA

are they being serious?


experience in what? delaying shit so many times?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on December 06, 2012, 08:26:34 PM
Probably the only one experienced from BFL team was the "old nice looking lady soldering singles" picture , but unfortunately even that picture was removed from their website lately. So guess what no one of the "experienced" employes left ;D
I am just wondering who will solder BFL ASIC's as long as lady has gone??? ???

PS:Just found it in Google cache...
It is prety obvious that she is in top form and 1000+ Asics for 10 days are not an issue for her :o

http://www.google.com/imgres?q=butterflylabs.com&hl=en&sa=X&tbo=d&biw=1024&bih=629&tbm=isch&tbnid=9lBP555L_b3bQM:&imgrefurl=http://www.butterflylabs.com/november-production-update/&docid=T43Z4PKGlpzzdM&imgurl=http://butterflylabs.com/wp-content/uploads/2011/11/IMG_1815.jpg&w=800&h=884&ei=DP_AUOiAGKnE4gTvioDgAQ&zoom=1&iact=hc&vpx=769&vpy=280&dur=7869&hovh=236&hovw=214&tx=98&ty=193&sig=100595112714249957668&page=4&tbnh=132&tbnw=143&start=55&ndsp=20&ved=1t:429,r:59,s:0,i:268


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on December 06, 2012, 08:29:57 PM
Time until Inaba/BFL_Josh comes to defend BFL in this thread:
5... 4... 3...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 06, 2012, 08:31:24 PM
Probably the only one experienced from BFL team was the "old nice looking lady soldering singles" picture , but unfortunately even that picture was removed from their website lately. So guess what no one of the "experienced" employes left ;D
I am just wondering who will solder BFL ASIC's as long as lady has gone??? ???

Josh + pajamas = soldering machine!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on December 06, 2012, 10:02:51 PM
Well, to be blunt, I'm not sure why the Avalon team wanted to join the word war ... but I guess it's 3 now in that :P
... at least until one team releases some ASIC :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mightycount on December 06, 2012, 11:36:26 PM



If you guys at Avalon are confident of your process, tech and timeline why wouldn't you open up more capacity to accept orders from disenchanted customers of competitors?

This would make total sense. If your second shipment can beat BFL's first, a lot of people would switch, I'm sure. I for one would have to do some serious soul searching for sure after a bunch of layers of BS from BFL :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mightycount on December 06, 2012, 11:41:32 PM
I think the demonstration event has been mentioned at the first (around late Sep. ?). but please let Yifu to re-explain it later, he is at the meeting in Macau
http://pbs.twimg.com/media/A8v_9YmCYAAPMgv.jpg

Which one is you?
Better question:

Who is each individual at the table? What do they each do for Avalon?

... and who is the dude with a waitress and a chick on the far right?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Frizz23 on December 07, 2012, 12:56:03 AM
It seems Inaba has been put on a leash by his bosses. He stopped posting/insulting people here on the forums :)

So I just copied his reply from the BFL forums.

...
1. while this wafer making process is going, you can't cancel it, or make adjustments, and if you wish to change anything, you will have to re-run this whole work flow all over again ( the large amount of the NRE upwards of 6 digits in USD is paid when you make the MASK). so anytime, BFL mention they are waiting for chips to come e.g. next week, but if they are still making adjustments, then this is physically impossible. In addition, fabrication company don't do chip packaging, if they are expecting the chips to arrive next week that means the production is already finished and they are probably in the chip packaging company (it is usually this time you find out if your chips work or not. which can also take some time since you'll have to test each of the chips for defects.)
...

BFL_Josh replies: "While I appreciate the technical prowess of the Avalon team, the fact of the matter is they simply don't have the resources or experience we have in this area. While the above may be true for them (and I have no doubt it is), what they are able to accomplish in a given time frame does not necessarily apply to our development workflow and process." https://forums.butterflylabs.com/bfl-forum-miscellaneous/500-josh-plz-give-us-some-comments-about.html#post7363

What does that tell us? Right. Nothing. Just more weasel comments. It applies, or maybe it does not ... there is, maybe there is not ... we ship, maybe we won't ...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Syke on December 07, 2012, 01:25:29 AM
So what was supposed to take 25 days from Halloween?

The next scheduled announcement of another "unexpected delay" from the world's most experienced processor design team in the world!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 07, 2012, 01:54:55 AM
It seems Inaba has been put on a leash by his bosses. He stopped posting/insulting people here on the forums :)
I was hoping no one would notice that he does have a boss or his sudden silence.

So I just copied his reply from the BFL forums.

...
1. while this wafer making process is going, you can't cancel it, or make adjustments, and if you wish to change anything, you will have to re-run this whole work flow all over again ( the large amount of the NRE upwards of 6 digits in USD is paid when you make the MASK). so anytime, BFL mention they are waiting for chips to come e.g. next week, but if they are still making adjustments, then this is physically impossible. In addition, fabrication company don't do chip packaging, if they are expecting the chips to arrive next week that means the production is already finished and they are probably in the chip packaging company (it is usually this time you find out if your chips work or not. which can also take some time since you'll have to test each of the chips for defects.)
...

BFL_Josh replies: "While I appreciate the technical prowess of the Avalon team, the fact of the matter is they simply don't have the resources or experience we have in this area. While the above may be true for them (and I have no doubt it is), what they are able to accomplish in a given time frame does not necessarily apply to our development workflow and process." https://forums.butterflylabs.com/bfl-forum-miscellaneous/500-josh-plz-give-us-some-comments-about.html#post7363

What does that tell us? Right. Nothing. Just more weasel comments. It applies, or maybe it does not ... there is, maybe there is not ... we ship, maybe we won't ...
It just means that the BFL rep is an expert in the art of quantum super-positioning statements.

It can be in more than three states at the same time.

You can infer "does not necessarily apply" to mean it does apply, yet, it does not apply. It all depends on the observer.

Making vague statements and keeping your distance is what you do when you can't say or have nothing to say in such a situation. Just hope the chips arrive and then start shipping.

Oh, and the 11th, the rep said it won't be met. (later in the month is the next revision).


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 07, 2012, 01:57:32 AM
This would make total sense. If your second shipment can beat BFL's first, a lot of people would switch, I'm sure. I for one would have to do some serious soul searching for sure after a bunch of layers of BS from BFL :)
BFL has apparently designed a fab technique based on layering BS on their chip. That is why they can grow/deposit those layers so darn quickly.

It will do everything (at lower power). As long as it is not seen by the human eye.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: DiabloD3 on December 07, 2012, 03:04:50 AM
Hmmm..... I think doing business in this region for over 25 years, gives me just a little perspective on the business practices of the Pearl Delta.
But perhaps brush up a little 武經七書... because I got what I needed faster than I expected.


I think you have no sense of humility after doing business for 25 years in these regions that you lost the ability to talk to another person like a regular human being. I had no intention to hide who these people were, I simply uploaded the picture from my phone on-the-go and now had the chance to do a proper follow up, not to mention many of these faces are not new and often seen in public involving bitcoin.

It would be much appreciated in the future, especially when directing questions at me. Brush up on how to be a gentleman, remove any trace of prejudice and cynicism you have obtained from a past that has nothing to do with me.

Please don't try to give lecture about something you know little about,  I'm very well paid and very good at what I do.

When you have had credible death threats from 'respectable' Asian business men  and attempts to kidnap your wife, come talk to me and we can talk all you want about:
 humility/racism/prejudice/cynicism/corruption/slavery/poisoning of babies/adults for profit or anything else you think you are an expert on.


Dear Thread,

Shut the hell up or so God help me I will turn this car around.

Signed, your favorite angry neighborhood bastard mod


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 07, 2012, 03:22:08 AM
Some background information on ASIC production process, before tape out, 3 day before uploading GDS (http://en.wikipedia.org/wiki/GDSII), we fill out a MT form with TSMC detailing the ASIC specific information so they may understand what we are doing. The gallery is here http://imgur.com/a/YOLez
http://i.imgur.com/us0iis.jpghttp://i.imgur.com/jKDeKs.jpghttp://i.imgur.com/15pWIs.jpg

Wow, 1.3GB of GDS data.  That's a lotta bits goin into them thar chips.

I hope y'all had them verify a hash of it.  Really their form ought to have a field for it.

Nice news release.  The next news I want to hear is that you have received the prototype chips, and that they are hashing as expected. :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: julz on December 07, 2012, 06:11:26 AM
I have a support ticket open which is now nearly 2 weeks old with no response other than 'Ticket Received',  re order number 200000363.
(ticket 13)
Can I please get some action on this?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 07, 2012, 06:39:18 AM
I have a support ticket open which is now nearly 2 weeks old with no response other than 'Ticket Received',  re order number 200000363.
(ticket 13)
Can I please get some action on this?

This matter has been taken cared of, we did not get the new ticket notification. Excuses aside, if in the future, any tickets or email that has not been replied to within 3 days, feel free to address it here in the thread as many eyes will be looking at from our team, but only few people get the notification emails in case some problems arise.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: DiabloD3 on December 07, 2012, 07:52:35 AM
The BFL reps responded to one of Avalons claims...with very vague mentions of a ~unique~ workflow arrangement enabling them to do...well, the impossible. (IMO)

https://forums.butterflylabs.com/bfl-forum-miscellaneous/500-josh-plz-give-us-some-comments-about.html#post7363
hm..

Quote

While I appreciate the technical prowess of the Avalon team, the fact of the matter is they simply don't have the resources or experience we have in this area.


HAHAHAHAHAHAHAHAHAHAHAHA


*deep breath*
...oh shit.

HAHAHAHAHAHAHAHAHAHAHAHHAHAHAHA

are they being serious?


experience in what? delaying shit so many times?

"IT POPS POPCORN!" -- Satoru Iwata, President of Nintendo of Japan


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bce on December 07, 2012, 08:26:55 AM
This would make total sense. If your second shipment can beat BFL's first, a lot of people would switch, I'm sure. I for one would have to do some serious soul searching for sure after a bunch of layers of BS from BFL :)
BFL has apparently designed a fab technique based on layering BS on their chip. That is why they can grow/deposit those layers so darn quickly.

It will do everything (at lower power). As long as it is not seen by the human eye.

Ahh so it is the observer effect causing delays? :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: caoxg on December 07, 2012, 10:07:37 AM
Well Done, Guys!

你们才是真正的专业~~
干的好啊同学们!
给国人长脸了!

(求加塞预定......)  


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: AndrewBUD on December 07, 2012, 03:45:08 PM
The BFL reps responded to one of Avalons claims...with very vague mentions of a ~unique~ workflow arrangement enabling them to do...well, the impossible. (IMO)

https://forums.butterflylabs.com/bfl-forum-miscellaneous/500-josh-plz-give-us-some-comments-about.html#post7363
hm..

Quote

While I appreciate the technical prowess of the Avalon team, the fact of the matter is they simply don't have the resources or experience we have in this area.


HAHAHAHAHAHAHAHAHAHAHAHA


*deep breath*
...oh shit.

HAHAHAHAHAHAHAHAHAHAHAHHAHAHAHA

are they being serious?


experience in what? delaying shit so many times?

"IT POPS POPCORN!" -- Satoru Iwata, President of Nintendo of Japan

I was wondering about that reply. BFL has more exeperience creating ASIC devices? I call BS. :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 07, 2012, 05:54:29 PM
BFL has more exeperience creating ASIC devices? I call BS. :)

They're a market leader in microprocessor design.   It says so right on prweb.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: abracadabra on December 07, 2012, 11:11:09 PM
BFL has more exeperience creating ASIC devices? I call BS. :)

They're a market leader in microprocessor design.   It says so right on prweb.

My sarcasm detector is malfunctioning.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: abeaulieu on December 07, 2012, 11:14:01 PM
I was wondering about that reply. BFL has more exeperience creating ASIC devices? I call BS. :)

Maybe they're referring to hiring someone, either as an employee or a contractor, who has experience making ASICs.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 07, 2012, 11:16:07 PM
I was wondering about that reply. BFL has more exeperience creating ASIC devices? I call BS. :)

Maybe they're referring to hiring someone, either as an employee or a contractor, who has experience making ASICs.

That's not what it says, and if that IS the case then they should fire that person immediately...they've failed.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: SgtSpike on December 07, 2012, 11:19:34 PM
I was wondering about that reply. BFL has more exeperience creating ASIC devices? I call BS. :)

Maybe they're referring to hiring someone, either as an employee or a contractor, who has experience making ASICs.
I think that's exactly what they are referring to.

It is common for companies to refer to themselves as having "51 years of combined experience" in such and such a field.  I think when BFL claims to be experienced in creating ASICs, they mean that their engineers have designed ASICs in the past, and thus have experience in designing ASICs.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Phinnaeus Gage on December 08, 2012, 12:03:42 AM
I was wondering about that reply. BFL has more exeperience creating ASIC devices? I call BS. :)

Maybe they're referring to hiring someone, either as an employee or a contractor, who has experience making ASICs.
I think that's exactly what they are referring to.

It is common for companies to refer to themselves as having "51 years of combined experience" in such and such a field.  I think when BFL claims to be experienced in creating ASICs, they mean that their engineers have designed ASICs in the past, and thus have experience in designing ASICs.

Bruno's Barn Wood & Beams has 2,783 years experience in building primitive barn wood furniture here in the US alone.

The way I did the math is add up all the years of experience of all the furniture makers I provide lumber for and voilà. I may be off by a decade or two, but you get the idea.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 08, 2012, 12:22:28 AM
I think when BFL claims to be experienced in creating ASICs, they mean that their engineers have designed ASICs in the past, and thus have experience in designing ASICs.

https://www.elance.com/s/nasser750gx/

If we have a look at Nasser's portfolio of past engineering projects, nearly all of them incorporate an FPGA, but nary a mention of an ASIC.  Not in the CV either.

Granted, that's probably only current as of 2007.  Still...

Maybe it's those secret ninja engineers they're not telling us about.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: DiabloD3 on December 08, 2012, 02:17:46 AM
The BFL reps responded to one of Avalons claims...with very vague mentions of a ~unique~ workflow arrangement enabling them to do...well, the impossible. (IMO)

https://forums.butterflylabs.com/bfl-forum-miscellaneous/500-josh-plz-give-us-some-comments-about.html#post7363
hm..

Quote

While I appreciate the technical prowess of the Avalon team, the fact of the matter is they simply don't have the resources or experience we have in this area.


HAHAHAHAHAHAHAHAHAHAHAHA


*deep breath*
...oh shit.

HAHAHAHAHAHAHAHAHAHAHAHHAHAHAHA

are they being serious?


experience in what? delaying shit so many times?

"IT POPS POPCORN!" -- Satoru Iwata, President of Nintendo of Japan

I was wondering about that reply. BFL has more exeperience creating ASIC devices? I call BS. :)

No, BFL has more experience in making highly efficient popcorn poppers.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: abeaulieu on December 08, 2012, 02:24:16 AM
I was wondering about that reply. BFL has more exeperience creating ASIC devices? I call BS. :)

Maybe they're referring to hiring someone, either as an employee or a contractor, who has experience making ASICs.

That's not what it says, and if that IS the case then they should fire that person immediately...they've failed.

Your response is much more falsely conclusive than anything. There are no words used to say that this experience is not derived from someone or a team of someones they've hired. In fact, it's pretty obvious that's the only thing they conceivably could be talking about considering we are pretty confident those we know about in management in Josh do not have experience in designing ASICs.

Secondly, we have yet to tell if this person(s) has failed, at least in my book. I guess you should probably evaluate your metric of success.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: OgNasty on December 08, 2012, 03:05:30 AM
Anyone interested in buying a discounted Icarus to lower the cost of their Avalon by $300?  PM me.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 08, 2012, 06:11:06 AM
The BFL reps responded to one of Avalons claims...with very vague mentions of a ~unique~ workflow arrangement enabling them to do...well, the impossible. (IMO)

https://forums.butterflylabs.com/bfl-forum-miscellaneous/500-josh-plz-give-us-some-comments-about.html#post7363
hm..

Quote

While I appreciate the technical prowess of the Avalon team, the fact of the matter is they simply don't have the resources or experience we have in this area.


HAHAHAHAHAHAHAHAHAHAHAHA


*deep breath*
...oh shit.

HAHAHAHAHAHAHAHAHAHAHAHHAHAHAHA

are they being serious?


experience in what? delaying shit so many times?

"IT POPS POPCORN!" -- Satoru Iwata, President of Nintendo of Japan

I was wondering about that reply. BFL has more exeperience creating ASIC devices? I call BS. :)

No, BFL has more experience in making highly efficient popcorn poppers.
Are you sure? 65nm is pretty cool to the touch, just saying. ;)  ;D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on December 08, 2012, 06:16:26 AM
The BFL reps responded to one of Avalons claims...with very vague mentions of a ~unique~ workflow arrangement enabling them to do...well, the impossible. (IMO)

https://forums.butterflylabs.com/bfl-forum-miscellaneous/500-josh-plz-give-us-some-comments-about.html#post7363
hm..
Quote
While I appreciate the technical prowess of the Avalon team, the fact of the matter is they simply don't have the resources or experience we have in this area.
HAHAHAHAHAHAHAHAHAHAHAHA


*deep breath*
...oh shit.

HAHAHAHAHAHAHAHAHAHAHAHHAHAHAHA

are they being serious?


experience in what? delaying shit so many times?
"IT POPS POPCORN!" -- Satoru Iwata, President of Nintendo of Japan
I was wondering about that reply. BFL has more exeperience creating ASIC devices? I call BS. :)
No, BFL has more experience in making highly efficient popcorn poppers.
Are you sure? 65nm is pretty cool to the touch, just saying. ;)  ;D
http://www.verumserum.com/media/2009/12/tongue-frozen-to-pole.jpg

DO ITTTT!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 08, 2012, 09:16:38 AM
BFL says Avalon is too "hot" and "irresponsible" in an eco friendly sort of way:

Quote from: BFL_Josh;7539
So I have been very focused on our ASIC launch for the past few weeks obviously and have not given a lot of thought towards the overall climate / state of ASICs until this evening, whilest rooting a new Nexus 7 GSM model (it's still got that new Android smell)...

A few things occurred to me, after giving them some thought and I am just throwing this out here:

bASIC

The lack of information from Tom (which was endemic from the start, but people had blinders on for a number of reasons), coupled with the little bit of information he's given out points quite convincingly that he has basically gone back to the drawing board and is starting over from scratch, or close enough to it to make no difference.  Why this has happened, only Tom can say, but one can make a few educated guesses.  There are two likely scenario's I can see here, and I'm just speculating... but either the "team" that Tom had assembled never delivered anything but empty promises and Tom finally got fed up and switched teams, putting him at square one.  Another possibility is that he did in fact get some boards back and things just didn't work out like he was hoping, which means he had to go back to the drawing board.  I give equal credence to either issue, but the fact that he has absolutely nothing to show for the efforts indicates that he is either starting from scratch or never got off the ground to begin with.  In either case, a mid-January launch from Tom at this point is exceedingly unlikely, and if he does manage to get something out by the middle of January, I suspect it will underperform and the power consumption will be much more than he's indicated at this point.  I think he was basing his power and hashrate estimates off what his previous team was telling him, and he's all but admitted that previous team was useless... so any estimates coming from them are going to be suspect.  Right now, I would say out of all the ASIC vendors, Tom is the most likely to fold up shop if anyone is going to fold up.

Avalon

Avalon is like the turtle... slow and steady and they will eventually get there.  What you end up with is going to be large, loud and hot while it tears through kilowatts like a Silverback through a banana plantation.  Will it perform at the hashrate advertised?  Absolutely, I think they will nail that, but the cost to reach that performance at 110nm is going to be crippling to anyone but those with free power.  The fact that the Avalon team has publicly stated that anyone not using free power should not be mining should be a major red flag when it comes to people who have to pay for power and what Avalon is going to bring to the table.  This is to say nothing of the environmental cost and how irresponsible it is to advocate mining inefficiently and not caring about the power usage.  Having brought up the environmental issue, I do realize how potentially hypocritical it is to be a bitcoin miner and talk about the environmental impact of mining, but that doesn't it isn't and shouldn't be a concern, especially when alternates are available.  Even the bASIC as a worst case will be superior to the Avalon in terms of power usage and should be used before using an Avalon unit to mine... but the environmental impact is another discussion. 

I think Avalon is going to run into some integration issues with their all-in-one approach that they aren't expecting - how quickly they will overcome them is anyones guess, but it could potentially signal a delay, but it's not something I would bet for or against.

ASICMINER

What's going on here?  Last I heard they might have chips before the end of the year.  Their hashrate won't really affect the network as a whole very much, so it's not really an issue.

----

I think that about covers the leading ASIC scene apart from BFL.  That said, with Tom looking like he's either down for the count or severely delayed, the real race now seems to be between Avalon and BFL.  We are still on target to ship before Avalon, so that is not really an issue... but I was considering what would happen if Avalon pulled a slick one and was able to ship much earlier and something interesting occurred to me.

Avalon has 300 units they want to ship in the first batch - ok, at 66 GH/s, that increases the network hashrate about 20 TH... That is less than half the current network hashrate, which is comprised of a large portion of GPU miners.  Adding 20 TH to the network would knock many of those GPU miners out of the profitability envelope, resulting in a net increase in network hashing power between 5 - 10 TH by my estimations.  So even if Avalon shipped tomorrow, it would not throw difficulty out of whack too far and would not be catastrophic for any of the other ASIC companies.  If Avalon sticks to their timeline and is truly able to ship all 300 units in a reasonable time frame, the network hashrate would be affected only in a minor way before Avalon runs into Chinese New Year and everything is on hold for a month...  That means the total increased network hashrate between now and March (at the earliest) is 5 - 10 TH if no other ASICs ship.  This does not necessarily include ASICMiner, but the future of ASICminer is kind of murky at this point, so it's hard to predict where they will end up and what effect it will have.

"Current State of ASICs (Not a BFL ASIC update)"

Link: https://forums.butterflylabs.com/bfl-forum-miscellaneous/509-current-state-asics-not-bfl-asic-update.html


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Frizz23 on December 08, 2012, 09:44:51 AM
Quote from: BFL_Josh
... resulting in a net increase in network hashing power between 5 - 10 TH by my estimations.  So even if Avalon shipped tomorrow, it would not throw difficulty out of whack too far ...

Sounds like damage control to me. BFL/Josh has come a long way from "kill-em-all jet fighter pilot first ASICs on the market nuke everyone else rarara" to "OK we might not be the first ones but it does not matter ... OK we suck but everyone else sucks too".

Lame, seriously lame.


Quote from: BFL_Josh
...before Avalon runs into Chinese New Year and everything is on hold for a month...

Oh! I am sure that at least here BFL will be the first one! The first one to use the "unusual long Chinese New Year"-story as another excuse why they can't ship their ASICs ;)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 08, 2012, 09:57:02 AM
Quote from: BFL_Josh
... resulting in a net increase in network hashing power between 5 - 10 TH by my estimations.  So even if Avalon shipped tomorrow, it would not throw difficulty out of whack too far ...

Sounds like damage control to me. BFL/Josh has come a long way from "kill-em-all jet fighter pilot first ASICs on the market nuke everyone else rarara" to "OK we might not be the first ones but it does not matter ... OK we suck but everyone else sucks too".

Lame, seriously lame.
You noticed it too, huh?

When the rep is on the defensive it is because he is worried about the competition. Hes done it to Tom, now to Avalon.


Quote from: BFL_Josh
...before Avalon runs into Chinese New Year and everything is on hold for a month...

Oh! I am sure that at least here BFL will be the first one! The first one to use the "unusual long Chinese New Year"-story as another excuse why they can't ship their ASICs ;)
<shrug>

Imagine if Avalon does ship first. The panic...the panic...

What he failed to mention is that Avalon customers will probably not affect difficulty, true. But that just means they might have made the right choice and will be mining green heaven. While his own customers sit and watch their computer screens for the next delay...

Enough profit so that even at 400watts they will be able to pay off the year of electricity use in less than a day. Thats IF, it stays at 400watts by the next update. Which should be soon I hope.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: SLok on December 08, 2012, 02:41:08 PM
Enough profit so that even at 400watts they will be able to pay off the year of electricity use in less than a day. Thats IF, it stays at 400watts by the next update. Which should be soon I hope.
Dream on, you'll need a 60w unit to achieve that, but it would happen in half a day.
For a 400w Avalon, at $0.10 a kwh that's 9.6kw a day = $0.96 x 365 = $350.40 a year.
So not even at today's difficulty "they will be able to pay off the year of electricity use in less than a day". More like 3 days, IF you strike blocks as any mining calculator suggests. Which no-one will.
At 4x difficulty that's 11 days for the power (at $0.10/kwh) and 40 weeks for the device. If the difficulty stays a 4x, which it won't.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 08, 2012, 03:06:36 PM
Enough profit so that even at 400watts they will be able to pay off the year of electricity use in less than a day. Thats IF, it stays at 400watts by the next update. Which should be soon I hope.
Dream on, you'll need a 60w unit to achieve that, but it would happen in half a day.
For a 400w Avalon, at $0.10 a kwh that's 9.6kw a day = $0.96 x 365 = $350.40 a year.
So not even at today's difficulty "they will be able to pay off the year of electricity use in less than a day". More like 3 days, IF you strike blocks as any mining calculator suggests. Which no-one will.
At 4x difficulty that's 11 days for the power (at $0.10/kwh) and 40 weeks for the device. If the difficulty stays a 4x, which it won't.
I stand corrected! It's actually 3 Days. ;)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: thorvald on December 08, 2012, 04:16:08 PM
Hello

Like some of you i`m waiting for my Avalon miners to arrive faster.

I just do not want to read thousand's of treads and pages about something that is not related with the product.

Can you please only use this for Avalon update.

Regards,

Thorvald



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 08, 2012, 09:08:20 PM
Can you please only use this for Avalon update.

Good luck with that, even the moderator can't.

Doesn't Avalon have their own forum site, like the other vendors?  You might have better luck there.

I can't remember the site offhand...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: abeaulieu on December 08, 2012, 09:31:48 PM
Can you please only use this for Avalon update.

Good luck with that, even the moderator can't.

Doesn't Avalon have their own forum site, like the other vendors?  You might have better luck there.

I can't remember the site offhand...

I think they use actual means of communication for official updates. I remember seeing some emails come through at some point...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: fcmatt on December 08, 2012, 09:36:51 PM
Can you please only use this for Avalon update.

Good luck with that, even the moderator can't.

Doesn't Avalon have their own forum site, like the other vendors?  You might have better luck there.

I can't remember the site offhand...

I think they use actual means of communication for official updates. I remember seeing some emails come through at some point...

My official emails from them always went into my spam folder and you need a lousy rep for that to happen.
Not being able to change my delivery addy on their order website modified my decision to order. So it was canceled.
I guess using their website to run a blog is difficult.... Heck, even a text file.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 09, 2012, 12:11:10 AM
I guess someone got the last laugh....

https://www.bitmit.net/en/item/11120-intratech-asic-miner-aerius-x1-35-gh-s


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: beekeeper on December 09, 2012, 12:26:09 AM
I guess someone got the last laugh....

https://www.bitmit.net/en/item/11120-intratech-asic-miner-aerius-x1-35-gh-s

Heh, weird. The board and the coolers seem like BFL.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on December 09, 2012, 12:37:54 AM
I guess someone got the last laugh....

https://www.bitmit.net/en/item/11120-intratech-asic-miner-aerius-x1-35-gh-s

Heh, weird. The board and the coolers seem like BFL.

it is a SCAM...........
https://bitcointalk.org/index.php?topic=60586.msg839374#msg839374 (https://bitcointalk.org/index.php?topic=60586.msg839374#msg839374)

Those are pictures of the Bitforce single.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 09, 2012, 01:16:15 AM
Doesn't Avalon have their own forum site, like the other vendors?  You might have better luck there.

I can't remember the site offhand...

Found it:

http://forum.bitsyn.com/

Not much activity tho.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on December 09, 2012, 02:01:27 AM
I guess someone got the last laugh....

https://www.bitmit.net/en/item/11120-intratech-asic-miner-aerius-x1-35-gh-s

Heh, weird. The board and the coolers seem like BFL.

it is a SCAM...........
https://bitcointalk.org/index.php?topic=60586.msg839374#msg839374 (https://bitcointalk.org/index.php?topic=60586.msg839374#msg839374)

Those are pictures of the Bitforce single.

That wasn't obvious when you first clicked on it?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 420 on December 09, 2012, 02:22:27 AM
Avalon still on schedule for Jan 14?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ngzhang on December 09, 2012, 03:12:13 AM
Avalon still on schedule for Jan 14?

yep :D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 420 on December 09, 2012, 03:13:00 AM
Avalon still on schedule for Jan 14?

yep :D

that means some are already done


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 09, 2012, 03:55:55 AM
Avalon still on schedule for Jan 14?

yep :D
When does the next update happen? (The one refering to the actual hardware of Avalon?)

And

Any comments on BFL's latest rants about your hardware?

Are you the turtle and are they the hare?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 09, 2012, 05:40:14 AM
Doesn't Avalon have their own forum site, like the other vendors?  You might have better luck there.

I can't remember the site offhand...

Found it:

http://forum.bitsyn.com/

Not much activity tho.

Still as I mentioned before, currently doing website overhaul, but understandably with the recent developments ( ASICs aside ), the mere website has been put into the back burner, but I am drafting up news letters for people with the next round of hardware updates, in addition with the recent paperwork update I gave out.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 09, 2012, 10:55:22 AM
And yet another series of dismissive comments from a BFL rep (on the topic of Avalon):

Quote from: BFL_Josh;7581
I was suppose to get more info yesterday (Friday) but the liason had nothing for me at COB, so it should be Monday that I have the confirmation from the fab... I am equally tired of the confirmation being pushed back as everyone else, believe me.  Regardless, to answer your question(s), I would not say your estimate is accurate.  We are still scheduled to ship prior to Avalons tentative shipping date as of right now.  Although the more I look at the documents Avalon provided and other information out there, I think they may be optimistic... but time will tell there.

Keep in mind that just because I don't have positive confirmation with regards to the date from the fab, it doesn't mean things aren't moving along there... it just means I haven't gotten positive confirmation from the people who have the final say in what the date will be.  The engineers run on a different schedule than bureaucracy, unfortunately (or fortunately).  I posted that other thread in lieu of a BFL update until I have something concrete to offer... ugh, I have a giant pack of information I want to spill, but I'm really hesitant to spill it right now, because if anything changes I catch seven kinds of hell!  Until everything is finalized and in the pipe, I don't want to put it out there and have to retract it later.

There's going to be lots of juicy information that will affect a lot of people for the better.

I promise I'm not pulling a Tom here and saying there's lots of good information coming soon and then never delivering - I will deliver on it.  There are definitely no 11th hour rugs being pulled out from under anyone without explanation either.

"Earliest date to expect delivery January 25th?"

Link: https://forums.butterflylabs.com/bfl-forum-miscellaneous/511-earliest-date-expect-delivery-january-25th.html#post7581


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 09, 2012, 12:59:01 PM
BFL_Josh might just as well have said...yeah we expect Avalon to be first and eat our appetizer, though we're still on track to have a portion of our own lunch at some point. 8)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 09, 2012, 02:09:49 PM
Ahaha, so now us, Avalon are the optimistic ones? I'll address BFL later, but I'm worried about bASIC now.

tom made an interesting response here: https://www.btcfpga.com/forum/index.php?topic=214.msg1478#msg1478

Quote
In response, I think Avalon means well. I do however find it interesting that they posted this in the bitcointalk forum under a basically anonymous moniker. I know some people involved with Avalon - although maybe only casually they know who I am and how to get a hold of me, it's obvious they used this generic account to post this and frankly it seems a little unprofessional maybe even a bit cowardly to post this based on partial and incomplete information - I guess I just I wish they had contacted me first and asked some questions before coming to these incorrect conclusions.

I do not see any area where they have been more transparent or released any more information than we have, there's bad things I could say to them but I don't think that's the right way to do business and I really dont have time for it. I just feel this post is unfair and It was posted from a generic account for a reason.

Currently we are doing all the right things behind the scenes right now and I think when you look at us and the competition in a months time - our customers will be glad they chose BTCFPGA/BitcoinASIC as their Bitcoin mining hardware provider.

Other than that I wish Avalon, BFL and anyone else attempting to bring to market an ASIC product, in this very challenging and demanding industry.

Since when I am a moniker? the BitSyncom name has been around the Bitcoin scene early as April 2011, many public face in the Bitcoin world can vouch, in additional to my name being Yifu G. It also has been in the signature since I started posting for Avalon ASIC, there are only 2 people represent the Avalon Project in public, one is Me, another is ngzhang. Neither of us know you. So, tell me who are these people involved with Avalon you know? This could pose a big problem.

Such as there are people pretending to be working on the Avalon project, and I can't begin the image the potential damage this could cause for the both projects. Either that or bASIC is lying, I'd like some names if possible.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 09, 2012, 03:35:57 PM
I'll address BFL later, but I'm worried about bASIC now.

tom made an interesting response here: https://www.btcfpga.com/forum/index.php?topic=214.msg1478#msg1478

Quote
In response, I think Avalon means well. I do however find it interesting that they posted this in the bitcointalk forum under a basically anonymous moniker. I know some people involved with Avalon - although maybe only casually they know who I am and how to get a hold of me, it's obvious they used this generic account to post this and frankly it seems a little unprofessional maybe even a bit cowardly to post this based on partial and incomplete information - I guess I just I wish they had contacted me first and asked some questions before coming to these incorrect conclusions.

I do not see any area where they have been more transparent or released any more information than we have, there's bad things I could say to them but I don't think that's the right way to do business and I really dont have time for it. I just feel this post is unfair and It was posted from a generic account for a reason.

Currently we are doing all the right things behind the scenes right now and I think when you look at us and the competition in a months time - our customers will be glad they chose BTCFPGA/BitcoinASIC as their Bitcoin mining hardware provider.

Other than that I wish Avalon, BFL and anyone else attempting to bring to market an ASIC product, in this very challenging and demanding industry.

I'm surprised he responded at all.

It's too bad the response has no substance.  It pretty much just calls Avalon a bunch of meanies, and says nothing at all about the bASIC (or Avalon) products.

I want to see them succeed (I have orders with bASIC as well as with Avalon), but I have to agree that things look really bad over there right now.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 09, 2012, 03:44:33 PM
Actually I think the darkest days are in the rear view for bASIC, but time will tell. Recent posts have been far more encouraging and detailed.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on December 09, 2012, 03:46:01 PM
BitSyncom,

Just let it go..There is no sense to loose your time for it...just personal opinion.  I do like tom very much indeed but i am wondering why he avoids simple yes/no answer if he had the chips - asked over and over from his own customers in his own forum (as long people like him so much of his openness and frankness)? The second thing i just can not understand as long as he was about to deliver week ago (if the chips were ok), why he is getting the pcb schematics from his engineers yesterday (famous powers of two  - bla bla - it was just a trick to reduce refunds, because by that time he knew that he will not deliver)? If i were him and i was waiting for the chips i wold have schematics revised many times + full populated PCB mounts ago in hands of software developers. It seems that his PCB (Asic board) is not produced yet. Let us say that he had the asics chips OK. How can he promise that he will deliver a couple of days after, when it is obvious that the board did not enter factory yet? What about the software for mining it needs at least some time to be developed also? Or this is just me thinking like that?  What about testing hardware itself (it needs at least a couple of days) and fixing hardware bugs if any? Adding all even chips were ok a week ago makes his delivery in as he stated 15 of January - just my math ..In general tom is not telling the whole truth - personal opinion...That is all



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 09, 2012, 04:08:38 PM
..In general tom is not telling the whole truth - personal opinion...That is all

Clearly, and he's lost some customers because of it. At least two of the three major developers of ASIC products for sale in the near future have withheld information at best and lied at worst. Interesting times ahead.

Avalon has been the only manufacturer to remain above the fray and that's in jeopardy as mud slinging ramps up and their own release date approaches. 


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: abeaulieu on December 09, 2012, 07:08:58 PM
..In general tom is not telling the whole truth - personal opinion...That is all

Clearly, and he's lost some customers because of it. At least two of the three major developers of ASIC products for sale in the near future have withheld information at best and lied at worst. Interesting times ahead.

Avalon has been the only manufacturer to remain above the fray and that's in jeopardy as mud slinging ramps up and their own release date approaches. 

Avalon has participated in the mudslinging though.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cedivad on December 09, 2012, 07:24:39 PM
If only I had paid my order with Avalon...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Mikej0h on December 09, 2012, 07:55:03 PM
As paid customer of Avalon I was very content BitSyncom/Avalon was not mixing in the word-fight with BFL and bASIC.
However with the latest "update" a turn was made, and I've been honest a bit disappointed about it.

Don't get me wrong, I'm damn happy everything is still on schedule and was happy to see the documents of TSMC.
And I'm very optimistic about the Avalon ASIC, and can't wait to start mining on it.

I do would love if the Avalon-team just for 110% focusses on the development of their product as I know it will be fantastic, and not wastes any time on their opponents.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on December 09, 2012, 08:00:32 PM

I do would love if the Avalon-team just for 110% focusses on the development of their product as I know it will be fantastic, and not wastes any time on their opponents.
+1
I'd love to if you can respond to this message BitSyncom.
-1
No need for that as long this will continue the "word-fight" right? No one needs it...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Mikej0h on December 09, 2012, 08:14:43 PM
I'd love to if you can respond to this message BitSyncom.
-1
No need for that as long this will continue the "word-fight" right? No one needs it...

Agreed & changed, I'm always a "confirm you read this" guy, so thats why I wrote that...
No flaming intended or what so ever.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 09, 2012, 11:55:37 PM
..In general tom is not telling the whole truth - personal opinion...That is all

Clearly, and he's lost some customers because of it. At least two of the three major developers of ASIC products for sale in the near future have withheld information at best and lied at worst. Interesting times ahead.

Avalon has been the only manufacturer to remain above the fray and that's in jeopardy as mud slinging ramps up and their own release date approaches. 

Avalon has participated in the mudslinging though.

What I'm sayin'.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: fcmatt on December 10, 2012, 12:45:33 AM
If only I had paid my order with Avalon...

I am in the same boat. But lets face it. Most of us were not the first to mine with gpu and that worked out for all involved last year who
got involved later on.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 10, 2012, 01:03:24 PM
Doesn't Avalon have their own forum site, like the other vendors?  You might have better luck there.

I can't remember the site offhand...

Found it:

http://forum.bitsyn.com/

Not much activity tho.

Still as I mentioned before, currently doing website overhaul, but understandably with the recent developments ( ASICs aside ), the mere website has been put into the back burner, but I am drafting up news letters for people with the next round of hardware updates, in addition with the recent paperwork update I gave out.
Are the newsletters written up?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kaerf on December 11, 2012, 06:22:00 AM
OKAY...When I ordered from Avalon in October, I didn't think there was a chance in hell that Avalon would come out before BFL and bASIC. I now fully expect Avalon to be the first out the gate. Good for you guys.

Here's my take on the big 3.

BFL can talk a good game, but IMO their engineering team (Nasser) probably isn't experienced enough in developing ASICs. I believe they've had several set backs due to errors in design. I think the engineering team (Nasser) is stringing Josh along and not being fully truthful to Josh. Josh is in the unfortunate position of being teamed with people that have a habit of dropping the ball... These type of people like to set expectations high, but rarely deliver on time nor will they deliver a quality product (it will be buggy or not live up to expectations).

Tom seems to mean well, but is either taking on too much by himself or is poorly organized. I do not know which it is. If it's the former, then hiring a competent technical lead/manager will make his life a whole lot easier, though more expensive. Since he doesn't have the technical experience himself to make the best decisions about his products, it's not totally unexpected that he chose his first (outsourced) team poorly. The sooner he hires a technical lead to validate the progress of his engineering team, the sooner he can be assured that he is on the right track. Without the technical validation, he is taking on a big risk for a second time...that would not be acceptable. Fortunately, it looks like Tom is about to hire a new technical lead (assuming his new hire has the appropriate experience).

IMO, Avalon is the team with the true engineers that do things the way engineers do things. That is - they plan, they model, they set appropriate (conservative) approximations, and do not say/report something unless they are very confident in those facts. This is the way competent engineers work. Avalon's engineering team is comprised of academics who pride themselves on technical correctness. This team appears to be the best organized and most technically competent of the 3.

I have orders with all 3 companies, so I'd like to think I'm not really biased against any of them, but with BFL's lates announcement, it's clear their engineering team is a joke (no, it's not entirely due to the chip plant). Unfortunately, my smallest order is with Avalon...due to timing and cost.


So all that said...going forward, I'll still go with the company that offers the best bang for the buck. IF all 3 companies eventually release real (reliable) products, I'll base most of my purchasing decision based on performance, initial price and long term power usage/ROI.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 11, 2012, 05:40:16 PM
Posted recently on the BFL forums:

Quote from: Fjordbit;7871
> When pressed for a reason why, I have been told that because this is a very dense, hand routed design they are afraid of making a mistake and have required extra checking and sign offs which has slowed down the whole process considerably. They don't want to be on the hook financially for having to redo the whole order. It sounds reasonable to me and I have no reason to doubt this

It sounds reasonable to me, but I implore you to not allow these guys to just coast until the next deadline. You need to

1) get a full project plan, including all of the checking and sign offs that need to occur
2) follow up on the status of those items in that project plan

On November 26th, you said "While I can't give a hard date and say "absolutely" this is the date, it looks like the week of the 11th, but that's the "fuzzy" date I have at the moment and I'm waiting on confirmation on a not-fuzzy date from the foundry right now." This appears to be an 11th hour change to that early commitment and you need to be a lot more aggressive with them now on meeting the deadline. Even though that was fuzzy, they still are missing that date by a wide margin. As such you really do not have any reason to trust there new date.

I am telling you now that the future of your entire company probably rests on making this date. While upgrade customers are a little locked in at this time, if Avalon ships, then you can expect a large number of cancellations to follow.

@ Avalon, how that update going? Isn't it your time to shine?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 11, 2012, 05:52:52 PM

@ Avalon, how that update going? Isn't it your time to shine?

Update is expected to release on Thursday, or two days from now. We are currently waiting for this round of updates from TSMC for this week which comes tomorrow.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ldrgn on December 11, 2012, 10:16:58 PM
I have orders with all 3 companies, so I'd like to think I'm not really biased against any of them, but with BFL's lates announcement, it's clear their engineering team is a joke (no, it's not entirely due to the chip plant). Unfortunately, my smallest order is with Avalon...due to timing and cost.

In addition to everything kaerf's mentioned I think it's worth bringing up that Avalon are superior strategists.  Anyone remember when BFL improved their numbers days after the competition bumped theirs?  BFL fell hook, line and sinker for the release date and stats games from their competition.  Avalon appears to have taken The Art of War to heart.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bce on December 12, 2012, 05:26:27 AM
I have orders with all 3 companies, so I'd like to think I'm not really biased against any of them, but with BFL's lates announcement, it's clear their engineering team is a joke (no, it's not entirely due to the chip plant). Unfortunately, my smallest order is with Avalon...due to timing and cost.

In addition to everything kaerf's mentioned I think it's worth bringing up that Avalon are superior strategists.  Anyone remember when BFL improved their numbers days after the competition bumped theirs?  BFL fell hook, line and sinker for the release date and stats games from their competition.  Avalon appears to have taken The Art of War to heart.

I would rather have had my pre-orders running at 30GH/s shipping in October than this.  I only hope that BFL hasn't held back on releasing something that could have run at a lower clock, in order to match the promised specs. Something working is better than something perfect, when time is of the essence.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 12, 2012, 07:29:29 AM
I have orders with all 3 companies, so I'd like to think I'm not really biased against any of them, but with BFL's lates announcement, it's clear their engineering team is a joke (no, it's not entirely due to the chip plant). Unfortunately, my smallest order is with Avalon...due to timing and cost.

In addition to everything kaerf's mentioned I think it's worth bringing up that Avalon are superior strategists.  Anyone remember when BFL improved their numbers days after the competition bumped theirs?  BFL fell hook, line and sinker for the release date and stats games from their competition.  Avalon appears to have taken The Art of War to heart.

I would rather have had my pre-orders running at 30GH/s shipping in October than this.  I only hope that BFL hasn't held back on releasing something that could have run at a lower clock, in order to match the promised specs. Something working is better than something perfect, when time is of the essence.
Thats exactly what I think happened.

They kept trying to compete. Kept raising the bar, kept improving the design. Hell, they are still doing it right now.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bitboyben on December 12, 2012, 08:02:55 AM
I have orders with all 3 companies, so I'd like to think I'm not really biased against any of them, but with BFL's lates announcement, it's clear their engineering team is a joke (no, it's not entirely due to the chip plant). Unfortunately, my smallest order is with Avalon...due to timing and cost.

In addition to everything kaerf's mentioned I think it's worth bringing up that Avalon are superior strategists.  Anyone remember when BFL improved their numbers days after the competition bumped theirs?  BFL fell hook, line and sinker for the release date and stats games from their competition.  Avalon appears to have taken The Art of War to heart.

I would rather have had my pre-orders running at 30GH/s shipping in October than this.  I only hope that BFL hasn't held back on releasing something that could have run at a lower clock, in order to match the promised specs. Something working is better than something perfect, when time is of the essence.
Thats exactly what I think happened.

They kept trying to compete. Kept raising the bar, kept improving the design. Hell, they are still doing it right now.

Any chance Avalon's subsequent batches will move to smaller node and reduce power use? I think they could do well if they are first to market and follow up with lower power consumption.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: michaelmclees on December 12, 2012, 01:47:39 PM
I would rather have had my pre-orders running at 30GH/s shipping in October than this.  I only hope that BFL hasn't held back on releasing something that could have run at a lower clock, in order to match the promised specs. Something working is better than something perfect, when time is of the essence.

Everyone was trying to win the hash race instead of trying to win the time race.  I keep saying it, but no one listens.  The winner of the time race, unless 2 or more manufacturers ship at about the same time, win ALL the marbles.  If BFL could have delivered a mere 15GH at $700, but back in October, they'd be so flooded with pre-orders right now the other folks wouldn't have a chance to catch up.  And while they try, BFL would be jumping ahead by doing nothing more than stacking ASIC's on ASIC's for diminishing costs, leaving Tom and Avalon in their wake.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 12, 2012, 05:06:34 PM
Update

There are several news:

1. The process of our rest layers are significantly faster, we are now in QC and expecting to have the wafer arrived at our packaging service next week. Then the slicing, packaging, and testing will start immediately.

2. The shares are under processing. Shareholders (determined per e-mail address) offering different addresses to GLBSE and to us will receive a confirmation mail asking which to use or whether changing to a newer one. And we also hope to identify the shareholders who claim both different e-mail addresses and different addresses as many as possible. The principle would basically be:
  1) If the shareholder has both claimed to GLBSE and to us, we will use the share number provided from GLBSE.
  2) If during analysis, the shareholder hasn't claimed to GLBSE but claimed to us, we will keep a separate list and see if it should be merged.
  3) If the shareholder hasn't claimed to us but claimed to GLBSE, we will of course use the GLBSE data.

Only important and relevant parts are:

1) When those chips are ready, is it guaranteed they actually work or will there be a random testing?

2) Will this happen before or after the shipping to ASICMINER team?

3) How many chips (%) to you think will be lemons?

Do not get too exited about the rest :)
1) There will be QC guaranteeing offering basic qualification, but the testing(functional, electronic, thermo) will be first done by us. After that, part of the testing (functional) will be done by the same company that does packaging for us.

2) After the shipping.

3) They would consider a 2/3 yield rate a non-failed one. However in most circumstances the rates are much higher than this bottom line. Made-in-China of course are connected with the impression of lower quality, but calculating with a whole project should put the overall cost into consideration. TSMC has higher threshold for newcomer clients and is less affordable.

As far as I remember, friedcat considered building a proprietary ASICMINER platform for listing and trading shares. As listing on all the alternitve centralized exchanges with their ponzis comes with risk, I think a proprietary platform is the best solution. We don't even know the exact reasons why glbse went down! Do you really want to ride the same horse again?

A proprietary exchange sounds great.

I think it's going to be important to get shares listed and actively available to trade before anything is produced by the company.

Right now it's in a state of limbo and no shareholders have any proof of ownership at all. This will change once it's listed somewhere. I think it's important to fully establish share ownership prior to the production of any ASIC devices / mining activity.
Yes. And we are working towards it. First we need to sort the actual data out from what we have now. We have a close partner working on a new platform that is considerably safer than GLBSE due to its more secure structure. And of course existing platforms like btc.co are also sound options. It is also optional for each shareholder to join the platform or to lock the shares in with us.

Link: https://bitcointalk.org/index.php?topic=99497.msg1394701#msg1394701


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kaerf on December 12, 2012, 07:00:44 PM
not sure exactly how much time is needed to qc and package, but it looks like by around christmas time asicminer should have chips?


avalon should have theirs around the same time too, right? or even before then if the demo is to occur late Dec.

Yifu, can you comment on your demo timelines? and what will occur between demo and shipping?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 13, 2012, 05:55:13 AM
not sure exactly how much time is needed to qc and package, but it looks like by around christmas time asicminer should have chips?


avalon should have theirs around the same time too, right? or even before then if the demo is to occur late Dec.

Yifu, can you comment on your demo timelines? and what will occur between demo and shipping?

I understood that the demo would be based on a chips coming from a MPW.  Then, if this is successful, a new maskset would be made and full wafers produced using the design, which would go into the products we would receive.

I find it hard to believe that a new tapeout and wafer production can happen in between then and Jan 14, much less board production and everything else that will be needed to ship out the door on Jan 14th.

How has Avalon been able to shortcut this process?  Are they also taking the 'cajones de acero' approach, and like BFL, producing full wafers from the start?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ngzhang on December 13, 2012, 06:42:07 AM
not sure exactly how much time is needed to qc and package, but it looks like by around christmas time asicminer should have chips?


avalon should have theirs around the same time too, right? or even before then if the demo is to occur late Dec.

Yifu, can you comment on your demo timelines? and what will occur between demo and shipping?

I understood that the demo would be based on a chips coming from a MPW.  Then, if this is successful, a new maskset would be made and full wafers produced using the design, which would go into the products we would receive.

I find it hard to believe that a new tapeout and wafer production can happen in between then and Jan 14, much less board production and everything else that will be needed to ship out the door on Jan 14th.

How has Avalon been able to shortcut this process?  Are they also taking the 'cajones de acero' approach, and like BFL, producing full wafers from the start?

yes

no one use MPW this time. include us, BFL ,bASIC, asicminer, etc.

just like a Chinese network catchword: we are all fighting without pants. (我们都已经脱了裤子干了)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kaerf on December 13, 2012, 07:07:02 AM
bASIC has said they have had demo chips (initial prototype burned out, but they have more chips than were in the prototype), so they have done MPW.

ngzhang, so after you've validated a few initial chips and demo, it's straight to production? hope you guys pull off an ahead of schedule shipping time!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ngzhang on December 13, 2012, 10:55:50 AM
bASIC has said they have had demo chips (initial prototype burned out, but they have more chips than were in the prototype), so they have done MPW.

sorry, we simply disbelieve it.  :)

ngzhang, so after you've validated a few initial chips and demo, it's straight to production? hope you guys pull off an ahead of schedule shipping time!

thank you. ;D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 13, 2012, 04:21:49 PM
Newsletter time?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 13, 2012, 05:06:04 PM
Updating as promised,

Let's be frank. We ran into a potential delay of 4-7 days.

What does this mean?

We when taped out the chips to TSMC we had a "projected out date" of Jan 3, 2013 which is on schedule with our late dec. / early jan. demonstration dates. Now however after this week's website update our "projected out date" has changed to Jan 7th, 2013 and "committed date" has been revealed to be Jan 10th, 2013. TSMC did not give us a reason for this, but as a small customer you are really at the mercy of bigger customers running higher priority lots. e.g. "super hot lot"  The "committed date" is the promised date of delivery, it is very unusual for TSMC to break their "committed date", so we expect our chips to ship on or before Jan 10th, 2013.

Another potential problem is Customs clearing, the packaging company Fujitsu is located in Shanghai's Export Processing Zone (EPZ), while the packaging itself will not see delays, it may take an additional 2-3 days to clear Customs. To make up for this, if it occurs, we will be flying down to Shanghai to the demonstration in the EPZ instead of waiting for the shipping to the factory for assembly.

With all this happening, it has burned through the 1 week additional leeway time we originally left out. I must say it will be difficulty for us to ship on Jan 14th, we however expect to ship around Jan 18 ~ 20.


Since some people were wondering how many chips are on a wafer earlier in the thread after we posted the MT forms I'll tell you, each wafer contains 4055 chips.
Code:
TSMC
TMEM91
================================================
Chip Size :   X = 3.9760 ,Y = 4.0560 mm
Reticle Size :   X/cell =  3 ,Y/cell =  3
Offset Value :   X = -3.7668 ,Y = -2.2990 mm
Alignment Mark :   (118.80,83.20),(-118.80,-83.20)
Alignment Mark Tolerant Distance :      1.6 mm
Notch Reserved Distance :   7.75 mm
Start Distance :   7.75 mm
Ring Edge :   3.0 mm
Photo Die Number:    4055

and this is the chip layout.
http://i.imgur.com/0xYrks.jpg (http://i.imgur.com/0xYrk.jpg)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on December 13, 2012, 05:09:34 PM
Updating as promised,

Let's be frank. We ran into a potential delay of 4-7 days.

What does this mean?

We when taped out the chips to TSMC we had a "projected out date" of Jan 3, 2013 which is on schedule with our late dec. / early jan. demonstration dates. Now however after this week's website update our "projected out date" has changed to Jan 7th, 2013 and "committed date" has been revealed to be Jan 10th, 2013. TSMC did not give us a reason for this, but as a small customer you are really at the mercy of bigger customers running higher priority lots. e.g. "super hot lot"  The "committed date" is the promised date of delivery, it is very unusual for TSMC to break their "committed date", so we expect our chips to ship on or before Jan 10th, 2013.

Another potential problem is custom clearing, the packaging company Fujitsu is located in Shanghai's Export Processing Zone (EPZ), while the packaging itself will not see delays, it may take an additional 2-3 days to clear customs. To make up for this, if it occurs, we will be flying down to Shanghai to the demonstration in the EPZ instead of waiting for the shipping to the factory for assembly.

With all this happening, it has burned through the 1 week additional leeway time we originally left out. I must say it will be difficulty for us to ship on Jan 14th, we however expect to ship around Jan 18 ~ 20.


Since some people were wondering how many chips are on a wafer earlier in the thread after we posted the MT forms I'll tell you, each wafer contains 4055 chips.
Code:
TSMC
TMEM91
================================================
Chip Size :   X = 3.9760 ,Y = 4.0560 mm
Reticle Size :   X/cell =  3 ,Y/cell =  3
Offset Value :   X = -3.7668 ,Y = -2.2990 mm
Alignment Mark :   (118.80,83.20),(-118.80,-83.20)
Alignment Mark Tolerant Distance :      1.6 mm
Notch Reserved Distance :   7.75 mm
Start Distance :   7.75 mm
Ring Edge :   3.0 mm
Photo Die Number:    4055

and this is the chip layout.
http://i.imgur.com/0xYrks.jpg (http://i.imgur.com/0xYrk.jpg)
Very interesting, thanks for the update.
Do you know how many chips will be in each Avalon yet, or do you have a date for when you'll know that information?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 13, 2012, 05:19:55 PM
Very interesting, thanks for the update.
Do you know how many chips will be in each Avalon yet, or do you have a date for when you'll know that information?

We don't plan to release this information, any information regarding our unit's internal you will have to find from pictures our customers who feels like uploading. This is our trade secret as we feel we designed a truly unique and innovative unit.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Dagger75 on December 13, 2012, 05:50:47 PM
Thank you for the Honest as well as Informative post. 


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: miter_myles on December 13, 2012, 06:02:19 PM
excellent information and updating going on here..  ALL the other ASIC sellers should be taking notes and following along the same line with the detail and information being passed.  Sadly, at this point they are not even in the same ballpark..


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: squeept on December 13, 2012, 06:15:53 PM
So I take that picture of the chip layout, print it out on my inkjet printer, glue it to a heatsink, then plug it in to the wall, right? Then I've got gigahashes?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on December 13, 2012, 06:34:12 PM
So I take that picture of the chip layout, print it out on my inkjet printer, glue it to a heatsink, then plug it in to the wall, right? Then I've got gigahashes?
Don't forget to overclock.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bitcoindaddy on December 13, 2012, 06:44:53 PM
We don't plan to release this information, any information regarding our unit's internal you will have to find from pictures our customers who feels like uploading. This is our trade secret as we feel we designed a truly unique and innovative unit.

Wait, it's your trade secret, but it's okay for customers to divulge?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 13, 2012, 06:49:42 PM
How would they even begin to prevent customers from exploring the workings of their own hardware? A "warranty void if removed" sticker isn't all that menacing to many.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 13, 2012, 06:58:50 PM
We don't plan to release this information, any information regarding our unit's internal you will have to find from pictures our customers who feels like uploading. This is our trade secret as we feel we designed a truly unique and innovative unit.

Wait, it's your trade secret, but it's okay for customers to divulge?
How would they even begin to prevent customers from exploring the workings of their own hardware? A "warranty void if removed" sticker isn't all that menacing to many.

It is like creativex said, I'm just delaying the inevitable, there is absolutely zero benefits for us to release this information, we will happily provide any information after release though, when it is no longer relevant to our competitors.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ngzhang on December 13, 2012, 07:03:51 PM
We don't plan to release this information, any information regarding our unit's internal you will have to find from pictures our customers who feels like uploading. This is our trade secret as we feel we designed a truly unique and innovative unit.

Wait, it's your trade secret, but it's okay for customers to divulge?
How would they even begin to prevent customers from exploring the workings of their own hardware? A "warranty void if removed" sticker isn't all that menacing to many.

It is like creativex said, I'm just delaying the inevitable, there is absolutely zero benefits for us to release this information, we will happily provide any information after release though, when it is no longer relevant to our competitors.

I think, reserve some surprises are important too.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Raize on December 13, 2012, 07:13:35 PM
He's basically saying they understand the nature of trying to enforce Intellectual Property in this world. It's impossible. So because of that, they are just going to focus on making the best product they can, and get it out to as many people as they can so that once it is reverse-engineered, their customers will already be so far ahead of the game it won't really benefit anyone to try to duplicate their product, because they'll have raised enough money to work on a redesign for a "Generation 2" product.

If the other ASIC devs were smart, they'd be buying orders of Avalons once we know they are legit, IMHO, specifically for the reverse-engineering opportunities. What's probably the saddest about the situation is that it looks like Avalon isn't only going to be the best designed, but it also looks like it might end up being the first to hit the network, too. So that means everyone else is going to be playing catch-up.

I was hoping for the sake of the Bitcoin network that there would be at least two competitors, one with a better product and one with more timely delivery. Not sure how this is all going to play out in the end.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 13, 2012, 07:26:16 PM
We don't plan to release this information, any information regarding our unit's internal you will have to find from pictures our customers who feels like uploading. This is our trade secret as we feel we designed a truly unique and innovative unit.

Wait, it's your trade secret, but it's okay for customers to divulge?
How would they even begin to prevent customers from exploring the workings of their own hardware? A "warranty void if removed" sticker isn't all that menacing to many.

It is like creativex said, I'm just delaying the inevitable, there is absolutely zero benefits for us to release this information, we will happily provide any information after release though, when it is no longer relevant to our competitors.

I think, reserve some surprises are important too.
How many wafers are you two waiting on at this time?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 13, 2012, 07:29:33 PM
He's basically saying they understand the nature of trying to enforce Intellectual Property in this world. It's impossible. So because of that, they are just going to focus on making the best product they can, and get it out to as many people as they can so that once it is reverse-engineered, their customers will already be so far ahead of the game it won't really benefit anyone to try to duplicate their product, because they'll have raised enough money to work on a redesign for a "Generation 2" product.

If the other ASIC devs were smart, they'd be buying orders of Avalons once we know they are legit, IMHO, specifically for the reverse-engineering opportunities. What's probably the saddest about the situation is that it looks like Avalon isn't only going to be the best designed, but it also looks like it might end up being the first to hit the network, too. So that means everyone else is going to be playing catch-up.

I was hoping for the sake of the Bitcoin network that there would be at least two competitors, one with a better product and one with more timely delivery. Not sure how this is all going to play out in the end.
You mean...300 hundred lucky individuals will mine like crazy while the other thousands are stuck waiting in line? Say it ain't so!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on December 13, 2012, 07:32:04 PM
You mean...300 hundred lucky individuals will mine like crazy while the other thousands are stuck waiting in line? Say it ain't so!
They had 300 units for pre-order, and I doubt they only sold 1 per person. I'm guessing it'll prolly be all 20TH/s divided up between 100-150 people.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 13, 2012, 07:41:09 PM
Quote from: BFL_Josh;8108
Looks like the Avalon delays are just getting started.  (https://bitcointalk.org/index.php?topic=120184.msg1397668#msg1397668 (https://bitcointalk.org/index.php?topic=120184.msg1397668#msg1397668)) ... I'm not surprised of course.  I think we're going to see a lot more delays once they actually get the chips and realize the magnitude of their error(s).  Maybe they can find away around it, but I'm having trouble envisioning how they can easily and quickly fix the problem they are going to be facing, which forced us to delay as well. 

Regardless, to answer some questions:



For the chip delivery, but I will be walking the chips through the rest of the process, so ~1 week for that.



Yes, I am meeting with the assembly house guy today as a matter of fact (headed to the airport in about 30 minutes).



What software are you referring to?  Mining software?  BFGminer and (likely) CGMiner will be ready. EasyMiner is mining, but still has some bugs that are being worked on daily... once I show you the new EasyMiner, you'll understand why it's taken so long.

For the pogopin assembly, it goes along with EasyMiner... it has nothing to do with the boards in a Minirig.  [/COLOR]

Link: https://forums.butterflylabs.com/bfl-forum-miscellaneous/519-10-dec-2012-bfl-asic-update-18.html#post8108

The BFL rep says you guys will have "clock buffer" issues. Any truth to that?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 13, 2012, 07:42:30 PM
And...any change in the power/hash numbers?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: michaelmclees on December 13, 2012, 08:20:51 PM
BFL says someone else will have delays?  Seems spurious...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: abeaulieu on December 13, 2012, 10:59:23 PM
BFL says someone else will have delays?  Seems spurious...

Well Avalon just announced a "potential" delay. Doesn't seem like BFL was too far off.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: michaelmclees on December 13, 2012, 11:28:30 PM
BFL says someone else will have delays?  Seems spurious...

Well Avalon just announced a "potential" delay. Doesn't seem like BFL was too far off.

It just seems like BFL has a backpedal mode that always looks the same - "The other guys have delays too... or might have delays... why are you all up in our face about ours?"

I just don't think that BFL has any room to speak of any delays from the other companies.  BFL is reigns supreme as the ASIC delay champion.  I hope that title does not continue, but it looks as though it will for the foreseeable future.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: miter_myles on December 13, 2012, 11:30:34 PM
BFL says someone else will have delays?  Seems spurious...

Well Avalon just announced a "potential" delay. Doesn't seem like BFL was too far off.

It just seems like BFL has a backpedal mode that always looks the same - "The other guys have delays too... or might have delays... why are you all up in our face about ours?"

I just don't think that BFL has any room to speak of any delays from the other companies.  BFL is reigns supreme as the ASIC delay champion.  I hope that title does not continue, but it looks as though it will for the foreseeable future.

well - one would assume if they didn't go into "defensive/look at them delaying too" mode that the refund door may receive more traffic..



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Aseras on December 14, 2012, 12:30:21 AM
So I take that picture of the chip layout, print it out on my inkjet printer, glue it to a heatsink, then plug it in to the wall, right? Then I've got gigahashes?

That's essentially how chips are made. Not precisely but they are basically printed on glass and the printing places the circuits and layers are added incrementally.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Vicus on December 14, 2012, 01:53:43 AM
So I take that picture of the chip layout, print it out on my inkjet printer, glue it to a heatsink, then plug it in to the wall, right? Then I've got gigahashes?
Don't forget to overclock.
And add more clock buffers!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bitboyben on December 14, 2012, 02:48:25 AM
So, for future batches are you guys going to have to wait for the foundry to slot you in again?
Cool photo btw


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 14, 2012, 03:32:56 AM
Link: https://forums.butterflylabs.com/bfl-forum-miscellaneous/519-10-dec-2012-bfl-asic-update-18.html#post8108

The BFL rep says you guys will have "clock buffer" issues. Any truth to that?

lol, of course they're going to say that.

Avalon has the odds in their favor when it comes to "clock buffer issues" vs BFL because of a couple of factors.  Mainly, the standard-cell based design vs going full custom, and also the choice of 110nm technology instead of 65nm.  Both of these things serve to reduce the difficulty of producing a working chip, vs choosing as BFL has to "shoot the moon".

With that said, I understand that producing any ASIC is still a very hard thing to do.  I thought that even the seasoned pros always first produced designs on MPW, and that the chances of an ASIC design working right the first time it's brought forth into silicon are near zero.

I question the wisdom of going directly to full wafer production.  BFL did and it cost them.  Why was the plan changed from what was laid out when the Avalon project was announced? (MPW first, then full wafers.)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 14, 2012, 02:10:36 PM
MPW = ?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on December 14, 2012, 02:18:51 PM
MPW = ?
Multi project wafer.
http://en.wikipedia.org/wiki/Multi-project_wafer_service


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: michaelmclees on December 14, 2012, 02:52:19 PM
BFL says someone else will have delays?  Seems spurious...

Well Avalon just announced a "potential" delay. Doesn't seem like BFL was too far off.

It just seems like BFL has a backpedal mode that always looks the same - "The other guys have delays too... or might have delays... why are you all up in our face about ours?"

I just don't think that BFL has any room to speak of any delays from the other companies.  BFL is reigns supreme as the ASIC delay champion.  I hope that title does not continue, but it looks as though it will for the foreseeable future.

well - one would assume if they didn't go into "defensive/look at them delaying too" mode that the refund door may receive more traffic..



That could be the case, but then they are already walking a fine line between not offering refunds until after January 1st, 2013 and offering to refund anyone who wants one because after all, they didn't use any preorder money to fund this venture.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Aseras on December 14, 2012, 03:10:14 PM
or having the whole lot fail and go bankrupt and leave everyone hanging.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on December 14, 2012, 03:25:58 PM
or having the whole lot fail and go bankrupt and leave everyone hanging.
You are talking about BFL ;) Right?
They know their business and that is why i am sticking to them. However shit happens. But let us think positive.  :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: server on December 14, 2012, 03:30:16 PM
I updated the bitcoin hardware wiki (https://en.bitcoin.it/wiki/Mining_hardware_comparison#ASICs) for Avalon ASIC.

Nothing new but I changed 60 -> 66 and the availability from Q2-2013 to Jan and Q1.

Have a great weekend y'all :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 15, 2012, 12:41:43 PM
If Avalon has 4055 chips per wafer and 2/3 turn out bad, then to service 300 customers they would only have about 1,350 ASICs per wafer. They would need multiple wafers (4 actually).

If each Avalon would have about 4 chips. Each would have to run at about 16.5 GH/s.

--------------------
We know it won't be that few because Avalon has already commented that they believe that their competitors claims of 7.5Gh/s per chip is "unrealistic".

So, I will revise my numbers and go on what they originally have planned in the past.

--------------------

In the past, Avalon claimed they were going to design a device with up to 15 chips. They later said that plan was out.

But assuming they originally planned for 15 chips lets do the math....

60Gh/s \ 15 = 4Gh/s per chip.

So by their original ideas at their original spec of 60Gh/s, they had planned for 4Gh/s chips.
At 4Gh per chip, they would require about 4.500 chips to fulfill their first batch (of 300). That is currently more than a single wafer holds. (Assuming 100% working chips, which is just unlikely)

------------------------

Assuming their old design used anywhere from 60 to 600 watts as one of their reps stated, the original chips had a power use of anywhere from

Best case: 1 watt per Gh/s
Worst case: 10 watts per Gh/s

Of course this is not including all the other electronics and various kinds of inefficiencies of a normal Power Supply.

Their current revision is now at 400 watts.
Which means their current guesstimate is somewhere in the neighborhood of 6 watts per Gh/s. Probably less considering all the other onboard electronics. Probably somewhere in the range of 5 watts.

---------------------------

I am going to make a forecast that they are using an even number of chips rather than an odd number of chips.

So either they are probably using 12 ASICs at 5.5Gh/s each. In 2 clusters?

or 16 ASICs at 4.1 GH/s. 4 clusters?

or 24 ASICs at 2.75Gh/s. 8 Clusters?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 15, 2012, 01:00:41 PM
As the Avalon reps previously stated that 60Gh/s itself was a very conservative value. I am going to further guess they had envisioned using less efficient chips than 7.5Gh/s and that they were using a shotgun approach of many chips to compensate for the inefficiency.

If they are actually using 4.5Gh/s chips. Then by increasing the number of chips, they increase the performance. (as well as the power use)

4.5Gh/s seems to be a conservative enough number to me. Not as high as 7.5Gh/s per chip which caused "disbelief" of competitors claims by Avalon representatives for various reasons.

Assuming 4.5 is the Avalon standard per ASIC:

2 chips =  9 Gh/s @ 5 watts per Gh/s power consumption is --> 45 watts
4 chips = 18 Gh/s @ 5 watts per Gh/s power consumption is --> 90 watts
6 chips = 27 Gh/s @ 5 watts per Gh/s power consumption is --> 135 watts
8 chips = 36 Gh/s @ 5 watts per Gh/s power consumption is --> 180 watts
10 chips = 45 Gh/s @ 5 watts per Gh/s power consumption is --> 225 watts
12 chips = 54 Gh/s @ 5 watts per Gh/s power consumption is --> 270 watts
14 chips = 63 Gh/s @ 5 watts per Gh/s power consumption is --> 315 watts
16 chips = 72 Gh/s @ 5 watts per Gh/s power consumption is --> 360 watts
18 chips = 81 Gh/s @ 5 watts per Gh/s power consumption is --> 405 watts
20 chips = 90 Gh/s @ 5 watts per Gh/s power consumption is --> 450 watts
22 chips = 99 Gh/s @ 5 watts per Gh/s power consumption is --> 495 watts
24 chips = 108 Gh/s @ 5 watts per Gh/s power consumption is --> 540 watts


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on December 15, 2012, 04:02:12 PM
As the Avalon reps previously stated that 60Gh/s itself was a very conservative value. I am going to further guess they had envisioned using less efficient chips than 7.5Gh/s and that they were using a shotgun approach of many chips to compensate for the inefficiency.

If they are actually using 4.5Gh/s chips. Then by increasing the number of chips, they increase the performance. (as well as the power use)

4.5Gh/s seems to be a conservative enough number to me. Not as high as 7.5Gh/s per chip which caused "disbelief" of competitors claims by Avalon representatives for various reasons.

Assuming 4.5 is the Avalon standard per ASIC:

2 chips =  9 Gh/s @ 5 watts per Gh/s power consumption is --> 45 watts
4 chips = 18 Gh/s @ 5 watts per Gh/s power consumption is --> 90 watts
6 chips = 27 Gh/s @ 5 watts per Gh/s power consumption is --> 135 watts
8 chips = 36 Gh/s @ 5 watts per Gh/s power consumption is --> 180 watts
10 chips = 45 Gh/s @ 5 watts per Gh/s power consumption is --> 225 watts
12 chips = 54 Gh/s @ 5 watts per Gh/s power consumption is --> 270 watts
14 chips = 63 Gh/s @ 5 watts per Gh/s power consumption is --> 315 watts
16 chips = 72 Gh/s @ 5 watts per Gh/s power consumption is --> 360 watts
18 chips = 81 Gh/s @ 5 watts per Gh/s power consumption is --> 405 watts
20 chips = 90 Gh/s @ 5 watts per Gh/s power consumption is --> 450 watts
22 chips = 99 Gh/s @ 5 watts per Gh/s power consumption is --> 495 watts
24 chips = 108 Gh/s @ 5 watts per Gh/s power consumption is --> 540 watts


I will eat my hat if Avalon hits 4.5GH/s per chip. The latest information post here shows a 4mmx4mm die, or 16mm^2. BFL's die is 7.5mmx7.5mm, or 56.25mm^2. The BFL chip is physically ~3.5x larger than Avalon. BFL is also on a 65nm node vs the 110nm of Avalon. Looking at minimum sized transistors BFL should be able to get 2.8x as many transistors in the same die area. Even say that BFL's custom design is inefficient and they can only get 2x as many transistors per mm^2 as Avalon. That still means the BFL has 7 times as many transistors per chip to work with as Avalon does. Unless BFL's design is absolute crap or Avalon is clocked way higher than BFL, they won't be that close to BFL.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: michaelmclees on December 15, 2012, 07:49:44 PM
In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: punin on December 15, 2012, 08:25:16 PM
In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.
That would give out too much valuable information to other people claiming to have hats.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bce on December 15, 2012, 08:53:50 PM
In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.
That would give out too much valuable information to other people claiming to have hats.

I remember seeing a picture of a tin-foil hat someplace, but I think it was deleted. 


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: punin on December 15, 2012, 09:03:26 PM
In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.
That would give out too much valuable information to other people claiming to have hats.

I remember seeing a picture of a tin-foil hat someplace, but I think it was deleted. 
It was a non-working dummy.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bce on December 15, 2012, 09:24:10 PM
In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.
That would give out too much valuable information to other people claiming to have hats.

I remember seeing a picture of a tin-foil hat someplace, but I think it was deleted.  
It was a non-working dummy.

You're a non-working dummy!  :D  (in the current spirit of BFL interactions)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Phinnaeus Gage on December 15, 2012, 10:01:15 PM
In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.
That would give out too much valuable information to other people claiming to have hats.

I remember seeing a picture of a tin-foil hat someplace, but I think it was deleted.  
It was a non-working dummy.

You're a non-working dummy!  :D  (in the current spirit of BFL interactions)

In the spirit of Phinnaeus Gage, I found the hat:

http://thesmolderingremnants.files.wordpress.com/2011/06/dunce-cap.jpg


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Unacceptable on December 15, 2012, 10:21:40 PM
In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.
That would give out too much valuable information to other people claiming to have hats.

I remember seeing a picture of a tin-foil hat someplace, but I think it was deleted.  
It was a non-working dummy.

You're a non-working dummy!  :D  (in the current spirit of BFL interactions)

In the spirit of Phinnaeus Gage, I found the hat:

http://thesmolderingremnants.files.wordpress.com/2011/06/dunce-cap.jpg

Here's my prototype,use it free of charge,I want all to prosper with my technology  8)

http://i146.photobucket.com/albums/r263/Seulman/tinfoilhat.jpg


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on December 15, 2012, 11:37:02 PM
(PS: the number of chips per Avalon is mostly irrevelant to these price estimations. I estimate you will have about 500mm² of die area per Avalon device. Whether it is 10 x 50mm² chips or 20 x 25 mm² chips is irrelevant to my numbers. 500mm² of wafer space will cost $40 regardless.)

Now that we know there will be 4055 chips per wafer, and that the die area is 16mm², I can refine my math and prediction:
- each Avalon chip will have 1/10th the number of transistors of the BFL chips (16mm² at 110nm vs. 56.25mm² at 65nm)
- BFL chips are 7.5Ghash/s, therefore Avalon chips should do 0.75Ghash/s (approximately, since the clock will be somewhat different)
- an Avalon wafer will therefore provide 4055*.75 = 3040 Ghash/s of mining power
- an Avalon wafer will go into the production of about 50 Avalon devices (~60 Ghash/s each)
- the raw cost of a wafer is $4,xxx per the partially-obscured price in the TSMC document published by the team, let's say $4500, that means $90 of wafer space per Avalon device (up from my prediction of $40)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Mikej0h on December 16, 2012, 12:08:20 AM
Now that we know there will be 4055 chips per wafer, and that the die area is 16mm², I can refine my math and prediction:
- each Avalon chip will have 1/10th the number of transistors of the BFL chips (16mm² at 110nm vs. 56.25mm² at 65nm)
- BFL chips are 7.5Ghash/s, therefore Avalon chips should do 0.75Ghash/s (approximately, since the clock will be somewhat different)
<cut>

You do realize that based on your calculation for a single Avalon device, which is advertised as 66Gh/sec, they would need 88 chips.
That sounds very unlikely to me...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on December 16, 2012, 12:38:21 AM
It's not unlikely at all... depending on power factors, we estimate between 64 and 128 chips per device.  88 is an odd number (not impossible of course), but given the propensity for the Avalon team to like nice round figures, I suspect a multiple of 8.  My thoughts are they are going to have to go with more than 64 chips to overcome the particular issues they haven't run into quite yet.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on December 16, 2012, 12:44:26 AM
Now that we know there will be 4055 chips per wafer, and that the die area is 16mm², I can refine my math and prediction:
- each Avalon chip will have 1/10th the number of transistors of the BFL chips (16mm² at 110nm vs. 56.25mm² at 65nm)
- BFL chips are 7.5Ghash/s, therefore Avalon chips should do 0.75Ghash/s (approximately, since the clock will be somewhat different)
<cut>

You do realize that based on your calculation for a single Avalon device, which is advertised as 66Gh/sec, they would need 88 chips.

Yes. Strange, but yes.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on December 16, 2012, 12:50:16 AM
I suppose that will mean they will miss their original goal of 15-30 chips per unit, unless BFL's chips are smaller than they say, or the Avalon chips can be clocked much more aggressively, or Avalon has a much better design.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 2112 on December 16, 2012, 01:59:46 AM
they would need 88 chips. That sounds very unlikely to me...
For a Chinese designers 88 would be a doubly prosperous number or joy number. Sounds likely to me...

http://en.wikipedia.org/wiki/Numbers_in_Chinese_culture#Eight


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on December 16, 2012, 06:03:41 AM
they would need 88 chips. That sounds very unlikely to me...
For a Chinese designers 88 would be a doubly prosperous number or joy number. Sounds likely to me...

http://en.wikipedia.org/wiki/Numbers_in_Chinese_culture#Eight


Wow good point!  That would be a pretty cool thing to design into/around.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ab8989 on December 16, 2012, 07:19:43 AM
I am sort of remembering the 7.5*7.5mm number for BFL was the size of the package and not the die size. I am not sure the die size was never revealed but it must be much smaller to fit into the package.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on December 16, 2012, 07:39:39 AM
I am sort of remembering the 7.5*7.5mm number for BFL was the size of the package and not the die size. I am not sure the die size was never revealed but it must be much smaller to fit into the package.

As I recall, the BFL package size was 11mm*11mm.

How would one organise 88 chips? Would it be a good idea to put them all on one PCB, or stack PCBs with 22 or 44 chips?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cedivad on December 16, 2012, 08:06:01 AM
Inaba, when I readed your post I couldn't belive you where not trolling.
I'm really happy of it.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: irritant on December 16, 2012, 08:59:24 AM
Inaba, when I readed your post I couldn't belive you where not trolling.
I'm really happy of it.

i had to read it two/three times  :D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Unacceptable on December 16, 2012, 09:35:56 AM
Inaba, when I readed your post I couldn't belive you where not trolling.
I'm really happy of it.

i had to read it two/three times  :D

Thats nothing,Frizzzzzzzzzz has to read most everything 5-6 times  :D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bce on December 16, 2012, 10:06:48 AM
Inaba, when I readed your post I couldn't belive you where not trolling.
I'm really happy of it.

i had to read it two/three times  :D

Thats nothing,Frizzzzzzzzzz has to read most everything 5-6 times  :D

That's nothing.  I usually read things even more times - lots of times.  It's pretty easy to do, really.  :)   <---- positive vibes


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 16, 2012, 01:28:24 PM
I am sort of remembering the 7.5*7.5mm number for BFL was the size of the package and not the die size. I am not sure the die size was never revealed but it must be much smaller to fit into the package.

As I recall, the BFL package size was 11mm*11mm.

How would one organise 88 chips? Would it be a good idea to put them all on one PCB, or stack PCBs with 22 or 44 chips?
I doubt there are 88 chips. But if there were, the slightest overclocking of that group of chips would incur one hell of a performance gain. (And lots of extra electrical use)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on December 16, 2012, 08:11:35 PM
But if there were, the slightest overclocking of that group of chips would incur one hell of a performance gain. (And lots of extra electrical use)

This is nonsense. Overclocking by x% always brings a constant x% performance gain, whether it is 88 small chips or, say, 4 large chips.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 16, 2012, 09:06:17 PM
But if there were, the slightest overclocking of that group of chips would incur one hell of a performance gain. (And lots of extra electrical use)

This is nonsense. Overclocking by x% always brings a constant x% performance gain, whether it is 88 small chips or, say, 4 large chips.
Not exactly true, there are interconnect/bus issues and firmware issues that might stop that from being true. If you have overclocked a normal CPU you know that something other than the main chip itself might limit a decent performance gain. Chips are usually a part of a system and not a standalone device.

Talking in terms of ASIC being overclocked, it depends on a number of design decisions. Overclocking 8 massive chips from 60 to 120 Gh/s is not the "exactly" the same deal as overclocking 88 chips that subdivide the work.

As long as you are dividing the heat load across a wider array of chips with more surface area [88 for example] and as long as your cooling is sufficient for all 88 (and you have enough space for all the chips), no single die should experience the same heat load as 1 in a group of 8. You can double the clock on a group of 88, but the heat is shared across a wider area.

In modern computing the idea is to create hyper efficient chips at a decent clock rate and stack them in as tiny a package as you possibly can. In fact, these days most CPU vendors are trying to compact as many cores as possible into one socket.

AMD has 32 per socket as an experimental design while intel is aiming for 50.

----------------

In the ASICs coming from the vendors, depending on the design decisions being made, you don't have to go with that logic. You can spread it out into clusters/modules with their own heatsink (like bASIC did).

Anyway, overclocking is much more than just changing the rate of the clock if you are designing the hardware. Perhaps Avalon has gone with the "shot gun" approach where the chips are all very inefficient but they make up the difference by:

1) Perhaps in their simplicity. (reliable, easy to produce dies?)
2) Perhaps by being so tiny alot of them can be packaged together like a mini rig?

I dunno. But there is more than one way to build a system. As long as you change the principles of the design enough that it makes practical sense.

BFL went with the idea of creating dense "Full custom" chips with high performance in a low nm process. But they are no "Intel" or "AMD". God knows how many failures they might face per wafer if their fab bakes the chips just slightly off.

Intel and AMD have their fabs set up to try tons of different combinations in one go. As the fab proceeds they get good data on what worked great and what works terrible as the layers are checked and baked. Therefore the first chips out of their fabs are usually the worst. While the last runs are their best and most efficient chips (and highly overclockable).

etc...



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on December 16, 2012, 09:26:24 PM
But if there were, the slightest overclocking of that group of chips would incur one hell of a performance gain. (And lots of extra electrical use)
This is nonsense. Overclocking by x% always brings a constant x% performance gain, whether it is 88 small chips or, say, 4 large chips.
Not exactly true, there are interconnect/bus issues and firmware issues that might stop that from being true.

In the context of Bitcoin mining, an x% overclock does bring an x% performance gain, because mining is an embarrassingly parallel workload that requires very little bandwidth, so it is trivial to design the interconnect so as to not make it a bottleneck. This specific argument is certaintly not going to explain that 88 chips will perform better than 4 large chips when overclocked (if interconnect was even an issue, it would be more a problem for 88 chips than for 4 chips).

As long as you are dividing the heat load across a wider array of chips with more surface area [88 for example] and as long as your cooling is sufficient for all 88 (and you have enough space for all the chips), no single die should experience the same heat load as 1 in a group of 8. You can double the clock on a group of 88, but the heat is shared across a wider area.

Then you should have said "it is easier to overclock 88 small chips than 4 large chips" (which I agree with). Your sentence "the slightest overclocking of that group of chips would incur one hell of a performance gain" does not convey this idea at all. You need to communicate your ideas more clearly if you want to be understood.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 16, 2012, 11:58:27 PM
@ Mrb

I'll try better next time.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on December 17, 2012, 12:55:05 AM
 "because mining is an embarrassingly parallel workload that requires very little bandwidth, so it is trivial to design the interconnect so as to not make it a bottleneck."

Sorry I would have to disagree with this, if you take a look at some of the RTL floating about,  a solution is provided every clock cycle.
That solution has to be tested and extracted, therefore the more engines you have working on solutions, the higher the probability of generating multiple nonces during the same clock phase that satisfy the rules you are looking for.

lets say that for the sake of argument you have 4 cores running independently at 100Mhz or 100MHs and all four cores produce a solution at the same time (rare but it can happen).
The internal silicon must then be capable of dealing with those 4 results during the same clock cycle. (how you gonna do that?), run the combiner logic at 4* the system clock?, so that you can process the 4 results is a "single" 100Mhz clk cycle, but 4 cycles at 400Mhz?
yep you could split the design down into groups of two engines and process the results in parallel at 200Mhz, but eventually it all has to be combined to get it out of the chip. Now multiply that by the number of cores some of these designs are running (6?)
or are we just going to "pretend" there was only 1 result and discard the other solutions.

Then you have to FIFO all this crap so that you can get it out of the chip, so the more cores you have on the chip, the more problems you have as regards raw silicon design, that is before you even think about HOW you are going to get work into the chip.

For interest take a look at one of the ASICS floating about, they have given a proposed pinout showing 8 data lines and some strobes.
WTF.... even the nonce will require 4 CLK cycles just to get it out of the chip and they are claiming this design is good into the GH/S range?




Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mem on December 17, 2012, 01:16:25 AM
It's not unlikely at all... depending on power factors, we estimate between 64 and 128 chips per device.  88 is an odd number (not impossible of course), but given the propensity for the Avalon team to like nice round figures, I suspect a multiple of 8.  My thoughts are they are going to have to go with more than 64 chips to overcome the particular issues they haven't run into quite yet.



Why dont you spend less time "guessing" what your competition is doing, what stages they are at and how further behind than you they are and spend more time answering the multitude of questions people have surrounding your shitty company ?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mrb on December 17, 2012, 01:52:07 AM
"because mining is an embarrassingly parallel workload that requires very little bandwidth, so it is trivial to design the interconnect so as to not make it a bottleneck."

Sorry I would have to disagree with this, if you take a look at some of the RTL floating about,  a solution is provided every clock cycle.
That solution has to be tested and extracted, therefore the more engines you have working on solutions, the higher the probability of generating multiple nonces during the same clock phase that satisfy the rules you are looking for.

lets say that for the sake of argument you have 4 cores running independently at 100Mhz or 100MHs and all four cores produce a solution at the same time (rare but it can happen).
The internal silicon must then be capable of dealing with those 4 results during the same clock cycle. (how you gonna do that?), run the combiner logic at 4* the system clock?, so that you can process the 4 results is a "single" 100Mhz clk cycle, but 4 cycles at 400Mhz?
yep you could split the design down into groups of two engines and process the results in parallel at 200Mhz, but eventually it all has to be combined to get it out of the chip. Now multiply that by the number of cores some of these designs are running (6?)
or are we just going to "pretend" there was only 1 result and discard the other solutions.

Then you have to FIFO all this crap so that you can get it out of the chip, so the more cores you have on the chip, the more problems you have as regards raw silicon design, that is before you even think about HOW you are going to get work into the chip.

For interest take a look at one of the ASICS floating about, they have given a proposed pinout showing 8 data lines and some strobes.
WTF.... even the nonce will require 4 CLK cycles just to get it out of the chip and they are claiming this design is good into the GH/S range?

No, a solution is not provided every clock cycle. A mining logic block will drop non-solutions without requiring any communication with any external logic: it just has to look if the high 32-bits are zero or not.

The end-result is that a a ~7.5 Ghash/sec chip, for example, is going to output a difficulty-1 solution every half second, on average. That's only a few hundred bytes transmitted every second. Hardly "rocket science".


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on December 17, 2012, 02:19:49 AM
or are we just going to "pretend" there was only 1 result and discard the other solutions

Yes. I don't care if 0.000001% of results are lost.

Edit: What failure rate would be acceptable to a "serious" miner? I'm guessing that 0.1% would not even be noticeable.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 2112 on December 17, 2012, 02:55:27 AM
No, a solution is not provided every clock cycle. A mining logic block will drop non-solutions without requiring any communication with any external logic: it just has to look if the high 32-bits are zero or not.

The end-result is that a a ~7.5 Ghash/sec chip, for example, is going to output a difficulty-1 solution every half second, on average. That's only a few hundred bytes transmitted every second. Hardly "rocket science".
I think I understand what hardcore-fs has on his mind. He is saying that with multiple hashing pipelines you may miss more valuable difficulty-n (n>1) share if your glue hardware is occupied with transmiting a difficulty-1 share that had just been found by another pipeline. This situation is probably infrequent, but he insists on a synchronous FIFO to handle it properly.

I had similar problem back in school, where we had to handle quite improbable fault conditions but we didn't wanted to lose track of them. We simply used asynchronous S/R flip-flops and interrupts. Software would single-step backtrack the faulty channels if more than one fault occured nearly simultaneously.

I think the same approach can be used for hashing chip: don't bother catching exact nonce; since you know the order in which nonces are tried you can check couple of previous nonces in software. Even if the hashing chip cannot reliably use asynchronous S/R flip-flops it could for sure use synchronous J/K flip-flops.

Basically, it is a hardware/software tradeoff in handling rare, but important, conditions.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bce on December 17, 2012, 02:56:16 AM
It's not unlikely at all... depending on power factors, we estimate between 64 and 128 chips per device.  88 is an odd number (not impossible of course), but given the propensity for the Avalon team to like nice round figures, I suspect a multiple of 8.  My thoughts are they are going to have to go with more than 64 chips to overcome the particular issues they haven't run into quite yet.



Why dont you spend less time "guessing" what your competition is doing, what stages they are at and how further behind than you they are and spend more time answering the multitude of questions people have surrounding your shitty company ?


This thread is about Avalon ASIC Development Status, and Inaba is staying on topic.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 17, 2012, 03:41:49 AM
No, a solution is not provided every clock cycle. A mining logic block will drop non-solutions without requiring any communication with any external logic: it just has to look if the high 32-bits are zero or not.

The end-result is that a a ~7.5 Ghash/sec chip, for example, is going to output a difficulty-1 solution every half second, on average. That's only a few hundred bytes transmitted every second. Hardly "rocket science".
I think I understand what hardcore-fs has on his mind. He is saying that with multiple hashing pipelines you may miss more valuable difficulty-n (n>1) share if your glue hardware is occupied with transmiting a difficulty-1 share that had just been found by another pipeline. This situation is probably infrequent, but he insists on a synchronous FIFO to handle it properly.

These chips crunch near a billion hashes per second.  Losing a small handful of those each second is miniscule.

Mine along on your CPU if you wanna make up the difference and then some.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Syke on December 17, 2012, 04:12:57 AM
It's not unlikely at all... depending on power factors, we estimate between 64 and 128 chips per device.  88 is an odd number (not impossible of course), but given the propensity for the Avalon team to like nice round figures, I suspect a multiple of 8.  My thoughts are they are going to have to go with more than 64 chips to overcome the particular issues they haven't run into quite yet.

Why dont you spend less time "guessing" what your competition is doing, what stages they are at and how further behind than you they are and spend more time answering the multitude of questions people have surrounding your shitty company ?

This thread is about Avalon ASIC Development Status, and Inaba is staying on topic.

Inaba has no idea whatsoever how Avalon is doing things, so he has no useful info to add to the thread, therefore he's just trolling as usual.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: abeaulieu on December 17, 2012, 04:52:19 AM
It's not unlikely at all... depending on power factors, we estimate between 64 and 128 chips per device.  88 is an odd number (not impossible of course), but given the propensity for the Avalon team to like nice round figures, I suspect a multiple of 8.  My thoughts are they are going to have to go with more than 64 chips to overcome the particular issues they haven't run into quite yet.

Why dont you spend less time "guessing" what your competition is doing, what stages they are at and how further behind than you they are and spend more time answering the multitude of questions people have surrounding your shitty company ?

This thread is about Avalon ASIC Development Status, and Inaba is staying on topic.

Inaba has no idea whatsoever how Avalon is doing things, so he has no useful info to add to the thread, therefore he's just trolling as usual.

Just as much useful information as you or I may have...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Syke on December 17, 2012, 05:04:50 AM

Inaba has no idea whatsoever how Avalon is doing things, so he has no useful info to add to the thread, therefore he's just trolling as usual.

Just as much useful information as you or I may have...

Actually, no. You or I are somewhat impartial. Inaba is a competitor. Any information he might put forth is extremely biased and anti-useful.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mem on December 17, 2012, 06:04:14 AM
On second thought, don't talk to me Inaba.

Talk to me when you actually have delivered 100 [ASIC] units of a product your company sells. Until that time shooo....I disown you as a legitimate vendor. Begone from my sight!

Edit: and uh, best of luck.

Wonderful PuertoLibre, does this mean you will leave this BFL thread and go to the actual ASIC vendor's thread? We will be deeply saddened by this loss.

abeaulieu is a hypocrite that knows exactly what he is doing and only does an average job of trying to hide it.
Your goal spread FUD against avalon while propping up the polished turd BFL.
Shill is a Shill is a Shill.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bce on December 17, 2012, 07:53:07 AM
On second thought, don't talk to me Inaba.

Talk to me when you actually have delivered 100 [ASIC] units of a product your company sells. Until that time shooo....I disown you as a legitimate vendor. Begone from my sight!

Edit: and uh, best of luck.

Wonderful PuertoLibre, does this mean you will leave this BFL thread and go to the actual ASIC vendor's thread? We will be deeply saddened by this loss.

abeaulieu is a hypocrite that knows exactly what he is doing and only does an average job of trying to hide it.
Your goal spread FUD against avalon while propping up the polished turd BFL.
Shill is a Shill is a Shill.

so... troll, reverse troll, counter troll, counter reverse troll, triple sow cow double hypocrisy back flip =  useful thread?  

I think it's better to keep things on topic.   Back on topic about the ASIC design of The Avalon Team - Thanks, Inaba for the thoughtful feedback.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: abeaulieu on December 17, 2012, 01:48:24 PM
On second thought, don't talk to me Inaba.

Talk to me when you actually have delivered 100 [ASIC] units of a product your company sells. Until that time shooo....I disown you as a legitimate vendor. Begone from my sight!

Edit: and uh, best of luck.

Wonderful PuertoLibre, does this mean you will leave this BFL thread and go to the actual ASIC vendor's thread? We will be deeply saddened by this loss.

abeaulieu is a hypocrite that knows exactly what he is doing and only does an average job of trying to hide it.
Your goal spread FUD against avalon while propping up the polished turd BFL.
Shill is a Shill is a Shill.

I'm actually quite impartial, and most certainly not being paid by BFL. You're just an idiot, mem, and there's no cure for that.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 17, 2012, 03:12:00 PM
Well, I was enjoying the technical talk between the three others. I actually want to hear what they have to say.

I want to see what they hash out [pun intended] between themselves on how they think the process should be handled. I dunno about anyone else, but at the end of that discussion I am going to ask Avalon teams members...."So your thoughts on this technical discussion is...?"

Then they will say something clever (one hopes) and let us in on some insight into how they handled the problem at the firmware or silicon level. That will benefit all of us, don't you think?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 2112 on December 17, 2012, 03:26:55 PM
These chips crunch near a billion hashes per second.  Losing a small handful of those each second is miniscule.

Mine along on your CPU if you wanna make up the difference and then some.
I get a feeling that a longer explanation is required for those unfamiliar with digital logic design.

The issue isn't really about losing one in billions of hashes. It is about gaining the timing margin (a.k.a. overclocking headroom) in the design.

Of course Avalon's logic is secret, but I'm going to discuss the problem based on one of the open-source FPGA hashers. It had a critical timing path in the logic that latched the "golden nonce". Since the design was 125-deep pipelined it had a hardware that subtracted constant 125 from the nonce counter before sending it out of the chip.

Now we have two ways to speed up the above design:

1) remove the 32-bit wide constant subtractor. This will gain a fraction of a nanosecond on every hash tried. It is very easy to subtract 125 in software from the nonce downloaded from the chip.

2) acknowledge that the timing violation may occur and the nonce latched may not be the exact one that solved the block, but a next one or previous one, depending on the details of the latching logic. It is somewhat more involved, but still easily doable in software: recompute the hashes for nonce values n-126,n-125,n-124 and use the one that solved the block. Again this will make the design more tolerant to overclocking for every hash tried inside the chip.

Obviously 1) cannot be applied to the ASIC chip or closed-source FPGA bitstream. But the method 2) remains applicable, just use a different set of test values.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on December 17, 2012, 04:08:45 PM
2) acknowledge that the timing violation may occur and the nonce latched may not be the exact one that solved the block, but a next one or previous one, depending on the details of the latching logic. It is somewhat more involved, but still easily doable in software: recompute the hashes for nonce values n-126,n-125,n-124 and use the one that solved the block. Again this will make the design more tolerant to overclocking for every hash tried inside the chip.

Obviously 1) cannot be applied to the ASIC chip or closed-source FPGA bitstream. But the method 2) remains applicable, just use a different set of test values.

With proper design, #2 need not even be apparent to the miner software. The microcontrollers that handle communications and control of the ASICs should be more than powerful enough to verify the hash returned by the ASIC and test the range around it should it not be valid. Even at 66GH/s that's what, around 15 diff1 shares per second? No reason that cgminer would even need to know about it.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 17, 2012, 07:11:47 PM
@ Avalon

Hardcore FS release some interesting documents in this thread on actual ASIC devices:

http://hardcoreforensics.com/blog/2012/12/10/bitcoin-mining-publicly-available-vhdl-source-code-and-the-xilinx-xupv5/
http://rijndael.ece.vt.edu/sha3/chip/sha3-asic-userguide.pdf
http://www.risec.aist.go.jp/project/sasebo/


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mem on December 18, 2012, 01:48:09 AM
On second thought, don't talk to me Inaba.

Talk to me when you actually have delivered 100 [ASIC] units of a product your company sells. Until that time shooo....I disown you as a legitimate vendor. Begone from my sight!

Edit: and uh, best of luck.

Wonderful PuertoLibre, does this mean you will leave this BFL thread and go to the actual ASIC vendor's thread? We will be deeply saddened by this loss.

abeaulieu is a hypocrite that knows exactly what he is doing and only does an average job of trying to hide it.
Your goal spread FUD against avalon while propping up the polished turd BFL.
Shill is a Shill is a Shill.

I'm actually quite impartial, and most certainly not being paid by BFL. You're just an idiot, mem, and there's no cure for that.



Hilarious - I have highlighted you being the very definition of a hypocrite and yet you side step the issue - still this is what BFL shills are known for.

In case you are to simple minded to realise when your own actions betray you I will break it down for you.

Wonderful PuertoLibre, does this mean you will leave this BFL thread and go to the actual ASIC vendor's thread? We will be deeply saddened by this loss.


Inaba has no idea whatsoever how Avalon is doing things, so he has no useful info to add to the thread, therefore he's just trolling as usual.

Just as much useful information as you or I may have...

Actually, no. You or I are somewhat impartial. Inaba is a competitor. Any information he might put forth is extremely biased and anti-useful.

You support Inaba trolling an Avalon thread but then ask PuertoLibre to stop trolling BFL, You are a hypocrite and an extremely transparent one at that.

Given that Inaba is an idiot prone to abusive rants deception and blatant lies even the best of days while PuertoLibre is direct and to the point.
Id argue that it makes for a very convincing argument that you are just another BFL shill.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: abeaulieu on December 18, 2012, 03:02:57 AM
@mem, you really need to find something better to do with your time. I won't bother quoting your attacks because I don't really think there is anything substantive there to quote. Coloring my text red does not add some polarizing quality to make phrases contradict, much less does the content itself contradict. I'm unsure of which "issue" I have sidestepped. I have stated plainly that I am not a "shill" as you call it, and I will expound by telling you that I am in no way a representative or someone who has received compensation from BFL and I will remain an impartial member much more interested in the technology than all of this meaningless drama.

I realize you do not like Butterfly Labs, and I do suspect that one day you will get over that. Whether it simply be lapse of time or by way of you screaming from the mountain "I was right, Butterfly Labs was a scam and will never deliver."

At that note, can we please give Avalon back their thread.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mem on December 18, 2012, 03:26:03 AM
@mem, you really need to find something better to do with your time. I won't bother quoting your attacks because I don't really think there is anything substantive there to quote.

It cant be made any clearer as I have provided direct quotes citing your hypocrisy.

You refuse to acknowledge, ask for substance when its slapping you in the face and then attempt to side step yet again.
You a hypocrite that suffers self delusion, dont expect others to indulge your fantasy.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on December 18, 2012, 04:42:03 AM
@mem, you really need to find something better to do with your time. I won't bother quoting your attacks because I don't really think there is anything substantive there to quote. Coloring my text red does not add some polarizing quality to make phrases contradict, much less does the content itself contradict. I'm unsure of which "issue" I have sidestepped. I have stated plainly that I am not a "shill" as you call it, and I will expound by telling you that I am in no way a representative or someone who has received compensation from BFL and I will remain an impartial member much more interested in the technology than all of this meaningless drama.

I realize you do not like Butterfly Labs, and I do suspect that one day you will get over that. Whether it simply be lapse of time or by way of you screaming from the mountain "I was right, Butterfly Labs was a scam and will never deliver."

At that note, can we please give Avalon back their thread.

Haha dude, it's like arguing with a wall, that one.  If you search back (a few months I think), there's a post somewhere about how he was declared mentally incompetent in Australia by the government.  I think he lives out in the boonies somewhere Ted Kaczynski style... You can't argue the crazy out of him.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mem on December 18, 2012, 04:44:11 AM
@mem, you really need to find something better to do with your time. I won't bother quoting your attacks because I don't really think there is anything substantive there to quote. Coloring my text red does not add some polarizing quality to make phrases contradict, much less does the content itself contradict. I'm unsure of which "issue" I have sidestepped. I have stated plainly that I am not a "shill" as you call it, and I will expound by telling you that I am in no way a representative or someone who has received compensation from BFL and I will remain an impartial member much more interested in the technology than all of this meaningless drama.

I realize you do not like Butterfly Labs, and I do suspect that one day you will get over that. Whether it simply be lapse of time or by way of you screaming from the mountain "I was right, Butterfly Labs was a scam and will never deliver."

At that note, can we please give Avalon back their thread.

Haha dude, it's like arguing with a wall, that one.  If you search back (a few months I think), there's a post somewhere about how he was declared mentally incompetent in Australia by the government.  I think he lives out in the boonies somewhere Ted Kaczynski style... You can't argue the crazy out of him.


Hey its my favourite delusional idiot agreeing without another delusional idiot :)
You 2 chaps should compare notes on your flawed argument methods.

abeaulieu is a proven hypocrite who is also not above blatant lies despite his own words being quoted.

And Inaba, well - calling you a delusional idiot is quite harmful to regular people with delusions, you are something rather special.

Good to see you have stopped cowering in the BFL forums and come online to agree with your sock puppet.
Care to share what Avalon or Basic is currently up to ?, You seem to have more "facts" on their own development than your own.... assuming it even exists outside your delusions.





Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bce on December 18, 2012, 06:30:46 AM
Can't we all just get along?  Remember, Santa is watching everything you do :) .


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on December 18, 2012, 06:39:45 AM
Can't we all just get along?  Remember, Santa is watching everything you do :) .
http://24.media.tumblr.com/tumblr_lwll2d4f5z1qkld3fo1_500.gif


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on December 18, 2012, 06:58:41 AM
2) acknowledge that the timing violation may occur and the nonce latched may not be the exact one that solved the block, but a next one or previous one, depending on the details of the latching logic. It is somewhat more involved, but still easily doable in software: recompute the hashes for nonce values n-126,n-125,n-124 and use the one that solved the block. Again this will make the design more tolerant to overclocking for every hash tried inside the chip.

Obviously 1) cannot be applied to the ASIC chip or closed-source FPGA bitstream. But the method 2) remains applicable, just use a different set of test values.

With proper design, #2 need not even be apparent to the miner software. The microcontrollers that handle communications and control of the ASICs should be more than powerful enough to verify the hash returned by the ASIC and test the range around it should it not be valid. Even at 66GH/s that's what, around 15 diff1 shares per second? No reason that cgminer would even need to know about it.

I'm not having a go at anyone, but rather pointing out an issue that effects ANY multi-cored logic design.
The issue I have with all this, is that it went:

CPU->GPU->FPGA->ASIC

and now here we are talking about:
ASIC+CPU to correct for possible piss poor logic design, next it will be "HAY, I have an Idea, Let's use ASIC+GPU to find possible missed nonces ,when we might have dropped one"

At a fundamental level, loosing a "nonce" is not just a case of hay its only .00000000016% of the nonces I generated, but the fact that you wasted the resources AND its not scaleable. (all so any figure thrown about like this is unverifiable, since you would need to know ALL the nonces that were generated to obtain the figure)
Anyway  bit-coin mining is not a static field any design that does not take poor logic design into account now at this stage of the game, is going to be severely shafted as the hashing rates of the devices climb, because both the number of cores and speed is only going to climb.

My point is not that a miner is going to loose a shit load of money because of lost nonces, BUT rather a fundamental flaw in the thinking of a designer, because there is a fundamental race condition.




Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on December 18, 2012, 07:34:12 AM

Of course Avalon's logic is secret, but I'm going to discuss the problem based on one of the open-source FPGA hashers. It had a critical timing path in the logic that latched the "golden nonce". Since the design was 125-deep pipelined it had a hardware that subtracted constant 125 from the nonce counter before sending it out of the chip.

Now we have two ways to speed up the above design:

1) remove the 32-bit wide constant subtractor. This will gain a fraction of a nanosecond on every hash tried. It is very easy to subtract 125 in software from the nonce downloaded from the chip.

2) acknowledge that the timing violation may occur and the nonce latched may not be the exact one that solved the block, but a next one or previous one, depending on the details of the latching logic. It is somewhat more involved, but still easily doable in software: recompute the hashes for nonce values n-126,n-125,n-124 and use the one that solved the block. Again this will make the design more tolerant to overclocking for every hash tried inside the chip.

Obviously 1) cannot be applied to the ASIC chip or closed-source FPGA bitstream. But the method 2) remains applicable, just use a different set of test values.

Or we could just do something stupid like this in the combinational logic:

currnonce <= nonce - 131;

and end up with a potential race condition, that does this:

LX110T:00000002d0bf3e4cd39201f1c70ff8c81c4f4d600405e89341df64ea00000163000000003ed5887 4bfd5ab6a7e30d6948d8d08bd620145fc52be75c6a9e0171801994b3250d015401a04fa62
   Got H-not-zero share 2d8ab702

0000000268558236d58cb3c63c0cf4a63edf7dc8315fa103866447710000043400000000deeb696 f29559d6319c87be74f077c369cbbc9afc9d344c97ae6ba55d201b7a650d00ae81a04fa62
Got H-not-zero share 2c04ea5f

When the core temp changes from 65 deg c to 66 deg c, as the temp increases by each degree so does the number of defects.
BUT.... and here is the million $ pinch.......,
There was not a SINGLE error last week when the ambient temperature of the room was 14 deg c now it is 21 deg. c

and this is with a core that is only 200MH/S from a single core.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on December 18, 2012, 12:12:58 PM
Well there may be a fix for errors, however the actual number of errors is easily seen to be small.

Good example is in the Icarus FPGA, we know the expected performance, we know the number of valid shares submitted, we know the number of invalid shares returned by the device and we ALSO know the expected number of valid shares for the given device performance.
It's not some run-away large wasted amount of work done - it IS very small.

Hmm, what is this 'golden nonce' ?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ab8989 on December 18, 2012, 01:40:35 PM
2) acknowledge that the timing violation may occur and the nonce latched may not be the exact one that solved the block, but a next one or previous one, depending on the details of the latching logic.

I am not at all familiar with the what is the specific individual nature of the calculation being done in here, so my opinion may be garbage, just replying based on general digital design principles.

It is somewhat common misconception that if clock speed is being increased to cause timing violations in digital logic sense of the word, the result is somewhat predictable to be either the earlier or later value. In general this is not true, the result of the 32 bit word is not any of the right, ealier or later, but it is total garbage. This even what happens in practice. You are not going to get any predictability what the result is going to be.

The reason is that not all bits of a word are finished at the same time in the calculation logic before the latch, some of the bits are going much later to settle to their correct values when you have some bits that arrived much earlier to their new values. Which bits arrive late and which arrive early can also change quite dramatically. The logic can be much faster going from '0' to '1' than going the other way etc.. So in practice the 32 bit word contains some bits that correspond to the correct result and some bits that are from the earlier result. Or it can be even more complex than that. The output bits can fluctuate wildly at the end of the logic doing the calculations and be in transition when the latching occurs. It is possible that some bit that has value '0' in both the correct and earlier result, but is going to have value '1' as some intermediate calculation value before it settles to its new value '0' from the earlier value '0'. It is even possible in theory that the output of the latch after the timing violation is neither '0' or '1'. The latch might become metastable and this metastability could propagate further to the ASIC so big portions of the ASIC could become metastable ( in theory ).

I am not sure you applied these characteristics of what happens in generic timing violations when talking about this specific instance and case.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on December 18, 2012, 02:25:07 PM
I'm not having a go at anyone, but rather pointing out an issue that effects ANY multi-cored logic design.
The issue I have with all this, is that it went:

CPU->GPU->FPGA->ASIC

and now here we are talking about:
ASIC+CPU to correct for possible piss poor logic design, next it will be "HAY, I have an Idea, Let's use ASIC+GPU to find possible missed nonces ,when we might have dropped one"
We already have that kind of combination, and it's no like ASIC will directly interface the network any time soon. Baring some pool op correcting me, I don't think any pools are using GPGPU code on their backend, and Bitcoind is obviously using CPU cycles to deal with the output of the mining device.

Anyway, regarding piss-poor design, I really can't speak on this case (and honestly neither can you). We don't know how Avalon has implemented their design, all we know is that they have a serial interface and there's no reason to think that will be a bottleneck in their design, even will multiple devices sharing the bus.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: beekeeper on December 18, 2012, 05:01:18 PM
Hmm, what is this 'golden nonce' ?
Lol man, you ever were curious to look over HDL files from those public FPGA projects?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on December 18, 2012, 08:31:43 PM
Hmm, what is this 'golden nonce' ?
Lol man, you ever were curious to look over HDL files from those public FPGA projects?
No, I just remember the golden nonce (that xiangfu put) in the Icarus code that I replaced with a better one - so I'm curious about there being some 'generic' golden nonce being referred to since it was indeed named above without reference.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: beekeeper on December 18, 2012, 11:31:01 PM
Hmm, what is this 'golden nonce' ?
Lol man, you ever were curious to look over HDL files from those public FPGA projects?
No, I just remember the golden nonce (that xiangfu put) in the Icarus code that I replaced with a better one - so I'm curious about there being some 'generic' golden nonce being referred to since it was indeed named above without reference.

One example ( fpgaminer_top.v):
Code:
// Check to see if the last hash generated is valid.
is_golden_ticket <= (hash2[255:224] == 32'h00000000) && !feedback_d1;
if(is_golden_ticket)
begin
// TODO: Find a more compact calculation for this
if (LOOP == 1)
golden_nonce <= nonce - 32'd131;
else if (LOOP == 2)
golden_nonce <= nonce - 32'd66;
else
golden_nonce <= nonce - GOLDEN_NONCE_OFFSET;
end


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on December 19, 2012, 05:24:40 AM
loosing a "nonce" is not just a case of hay its only .00000000016% of the nonces I generated

To an end-user, that's exactly what it is. If lost nonces (even if they happen in pairs) are a less common failure mode than internet dropouts, pools going offline and stale shares, then only logic-purists will care.

you wasted the resources

Look at it this way: If a 1GH/W chip has a 1% nonce loss rate, and a 0.5GH/W chip has a 0% nonce loss rate, then one would be wasting power by using the latter chip, even if it is logically perfect.

Tldr;
http://cdn.memegenerator.net/instances/400x/22789752.jpg


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: fpf on December 19, 2012, 10:42:27 AM
Hmm, what is this 'golden nonce' ?

The one (or more) out of the 4294967296 nonces that solve the work and can be submitted & can/will be accepted by the pool server for the task/workload received.

About loosing some nonces because of hardware errors, yes that can happen, and I don't think that is some new issue, should also have been the case with GPUs especially when you overclocked them...

@The one concerned (Forgot where I read this)
using & loosing a clock cycle or multiple clock cycles, to read out the found "golden" nonce from any dedicated mining hardware is totally no issue at the clock rates they run on...

A lot of the current hardware on the market looses a lot more time doing that than "4 clock cycles" and I really mean a loooot more.
Let's take the Icarus as an example, even if it can latch the result in one clock cycle it will need a lot of actual clock cycles until the result is finally at it's destination. At the end of the day, does it matter? no.... because for a full range scan you need 4294967296 clockcycles... (assuming the device does 1 nonce per clock cycle and scans the whole range)
4294967.296 clock cycles would cost 0.1% of the performance of the device.... It's still totally insignificant.

Icarus Response:
(4 bytes + 4 x start and 8 x stop bits at 115200 bps (it uses 2 stop bits for each byte if I remember right) or twice this time in case the nonce came from the cascaded FPGA and the nonce gets "forwarded" + the delays by the USB to uart chip + the delays caused by the USB system itself (package based) and the drivers for the usb to uart chip.. + the operating system + the actual miner software + the whole thing again even longer this time because uploading a new "task" takes even longer... - at the end of the day, does it matter? no.... - now you know why even thousands of "clock cycles" are still totally insignificant for such devices...

About multiple cores on a single chip - there are 2 ways - either each of them get their own "work" or the range gets split, it's possible that there is more than 1 "golden nonce" to the "work" - however having more than one golden nonce at the exactly same clock cycle is very unlikely.

FPF




Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: fpf on December 19, 2012, 10:56:47 AM
1) remove the 32-bit wide constant subtractor. This will gain a fraction of a nanosecond on every hash tried. It is very easy to subtract 125 in software from the nonce downloaded from the chip.

2) acknowledge that the timing violation may occur and the nonce latched may not be the exact one that solved the block, but a next one or previous one, depending on the details of the latching logic. It is somewhat more involved, but still easily doable in software: recompute the hashes for nonce values n-126,n-125,n-124 and use the one that solved the block. Again this will make the design more tolerant to overclocking for every hash tried inside the chip.

Yes, would be great if Cgminer would have such a option, where we could manually define such prefixed nonce modifications or even a certain range for a "rescan" over the PC's CPU in a defined range. As I know, Cgminer checks already if the "golden nonce" submitted to it is valid and if not counts it as hardware error, so a implementation should be rather easy and also work with any hardware supported by Cgminer...

FPF


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: beekeeper on December 19, 2012, 11:06:32 AM
1) remove the 32-bit wide constant subtractor. This will gain a fraction of a nanosecond on every hash tried. It is very easy to subtract 125 in software from the nonce downloaded from the chip.

2) acknowledge that the timing violation may occur and the nonce latched may not be the exact one that solved the block, but a next one or previous one, depending on the details of the latching logic. It is somewhat more involved, but still easily doable in software: recompute the hashes for nonce values n-126,n-125,n-124 and use the one that solved the block. Again this will make the design more tolerant to overclocking for every hash tried inside the chip.

Yes, would be great if Cgminer would have such a option, where we could manually define such prefixed nonce modifications or even a certain range for a "rescan" over the PC's CPU in a defined range. As I know, Cgminer checks already if the "golden nonce" submitted to it is valid and if not counts it as hardware error, so a implementation should be rather easy and also work with any hardware supported by Cgminer...

FPF

2112 is talking about modifications in FPGA bitstream, ofc software modification to cope with new bitstream would be trivial.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: fpf on December 19, 2012, 11:19:19 AM
I know that, but the consequence of those changes is the fix/option in the mining software - Cgminer is just an example here. It's actually the best location for that task since all the functions are already implemented, there is just a special option needed to re-purpose those functions. (such as the nonce validation)

The first option would be to deduct a certain fixed value from the nonce, it's much more efficient for the mining software to do that than it's done in some of the current bitstreams. The next option would be allowing Cgminer a certain range for the nonce validation. (To do a few nonce calculations on the CPU is not a big deal and it could save that (only slightly) corrupted nonce from being ignored and regarded as hardware error...)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: beekeeper on December 20, 2012, 12:49:07 AM
In my humble opinion..
There is a wall.. one side, regular BTC developer, the other side people who understand the hardware..
Stop trying to bridge, it is not worth..


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Frequency on December 20, 2012, 12:52:32 AM
Any real news yet or some project update !!!!!  ???


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on December 20, 2012, 04:01:41 AM
I know that, but the consequence of those changes is the fix/option in the mining software - Cgminer is just an example here. It's actually the best location for that task since all the functions are already implemented, there is just a special option needed to re-purpose those functions. (such as the nonce validation)

The first option would be to deduct a certain fixed value from the nonce, it's much more efficient for the mining software to do that than it's done in some of the current bitstreams. The next option would be allowing Cgminer a certain range for the nonce validation. (To do a few nonce calculations on the CPU is not a big deal and it could save that (only slightly) corrupted nonce from being ignored and regarded as hardware error...)

You mean like adding lubricant to your tiers so you can go down hill faster.

Quote
The first option would be to deduct a certain fixed value from the nonce, it's much more efficient for the mining software to do that than it's done in some of the current bitstreams.

You sir are a fucking idiot.
FPGA's process in true parallel.
 I can process thousands....(nay tens of thousands) of 32 bit subtractions in an FPGA, before you have even fucking read the numbers into your CPU registers.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 20, 2012, 04:14:06 AM
Hmm, what is this 'golden nonce' ?

I think if you catch the golden nonce, it's worth 150 points and the match is over.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on December 20, 2012, 07:56:28 AM
Hmm, what is this 'golden nonce' ?

I think if you catch the golden nonce, it's worth 150 points and the match is over.

They really ought to nerf that down to 15 points. Then the rest of the team would matter.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: fpf on December 20, 2012, 09:14:35 AM
Of course Avalon's logic is secret, but I'm going to discuss the problem based on one of the open-source FPGA hashers. It had a critical timing path in the logic that latched the "golden nonce". Since the design was 125-deep pipelined it had a hardware that subtracted constant 125 from the nonce counter before sending it out of the chip.

Now we have two ways to speed up the above design:

1) remove the 32-bit wide constant subtractor. This will gain a fraction of a nanosecond on every hash tried. It is very easy to subtract 125 in software from the nonce downloaded from the chip.

2) acknowledge that the timing violation may occur and the nonce latched may not be the exact one that solved the block, but a next one or previous one, depending on the details of the latching logic. It is somewhat more involved, but still easily doable in software: recompute the hashes for nonce values n-126,n-125,n-124 and use the one that solved the block. Again this will make the design more tolerant to overclocking for every hash tried inside the chip.

Obviously 1) cannot be applied to the ASIC chip or closed-source FPGA bitstream. But the method 2) remains applicable, just use a different set of test values.


@hardcore-fs
Please read the context in which things were said:

The 32-bit wide constant subtractor in that design limits the whole speed of the design, you can speed up the whole design by removing that subtractor and simply deduct the constant later from the "nonce" received from the chip to get the "golden nonce"...
It's simply about gaining some overhead, the weakest link breaks the chain.

If you can gain even more overhead by assuming that the latched nonce in the chip is not the "golden" one but very close by as stated by him, a few nonce validity checks nearby will finally reveal the "golden nonce" this way you can push the chip in terms of clock and internal timings to its limits and even a bit beyond.

If this can improve the maximum speed that can be reached for the device significantly - in exchange for a bit of insignificant cpu time every nonce found (we talk about crosschecking only a hand full of nonces here vs. the workload, and that roughly every 10.7 seconds for a 200 mhz core) than yes - it's an acceptable way.

Quote
You mean like adding lubricant to your tiers so you can go down hill faster.


You need grip to make use of the car's engine, no point.. but IF the task is to get the car down the hill the fastest way possible with engaged breaks, without the need of being able to stop it and all you have is an unlimited supply of lubricant - than yes adding lubricant to both the street and the tiers to accomplish the task is the way to go.

Quote
You sir are a fucking idiot.
FPGA's process in true parallel.
 I can process thousands....(nay tens of thousands) of 32 bit subtractions in an FPGA, before you have even fucking read the numbers into your CPU registers.

Posting insults & very basic / unrelated facts (of actually any logic or programmable logic) doesn't help here.
"In the land of the blind, the one-eyed man is king"

Quote
For interest take a look at one of the ASICS floating about, they have given a proposed pinout showing 8 data lines and some strobes.
WTF.... even the nonce will require 4 CLK cycles just to get it out of the chip and they are claiming this design is good into the GH/S range?

Here we go 8) a "truly parallel" 8bit Data-bus
Of course it's good into the GH/s range, the traffic is low since only the results ("golden nonces") need to be collected, everything else gets discarded already in the chip... The only way to make it faster than it is right now would be having a 32bit databus to get the whole nonce out of the chip in one CLK cycle, would it matter? no... waste of resources and space, 24 more pins/tracks to deal with for no real benefit... the same is true for getting the "work" to the chip of course (which is of course more than 4 bytes...)

Edit: Should be said for the sake of completeness, those 4 clock cycles needed to collect the nonce will be from an external controller and are not directly related to the internal clock used by the hashing chip, further, the clock for collecting the data will be slower than the internal clock used by the hashing chip. Changes nothing about the situation though.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on December 20, 2012, 01:40:26 PM
As regards the
Quote
Posting insults & very basic / unrelated facts (of actually any logic or programmable logic) doesn't help here.
"In the land of the blind, the one-eyed man is king"

Is the above even English?

you made a hardcore statement about 'nonces/golden nonces'
Quote
The first option would be to deduct a certain fixed value from the nonce, it's much more efficient for the mining software to do that than it's done in some of the current bitstreams.

it is irrelevant in "what" context it was made,no matter how you try to spin it, A VERY clear statement was made and I cannot think of ANY situation where the "mining software" is going to be able to do that in a more efficient way than pure logic.
EVEN IF the value was subtracted at EVERY stage of the nonce calculation.
In fact in at least one public core IT IS done this way, and do you know what... the  calculation as regards time is ABSOLUTELY FREE.

Quote
The 32-bit wide constant subtractor in that design limits the whole speed of the design, you can speed up the whole design by removing that subtractor and simply deduct the constant later from the "nonce" received from the chip to get the "golden nonce"...
It's simply about gaining some overhead, the weakest link breaks the chain.

nope!!!!, it does not "limit the speed", because the subtraction CAN be done at the SAME TIME INSIDE the logic, because you ALREADY KNOW THE VALUE OF THE NONCE BEFORE you start the SHA256(SHA256(x)) Hash.

http://postimage.org/image/e885j7xy3/

Notice "nonce" & "currnonce" & clock, one lags the other by 131 in this case , because that is the depth of the current nonce calculations, but we can clearly see the calculation between the two nonces  occurs & ends on the same clock cycles, making it effectively "free" to calculate the difference.


if you cannot understand the basic principles of digital logic, then I'm not going to waste my time trying to explain it further.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Dhomochevsky on December 20, 2012, 06:46:21 PM
I don't mean to interrupt this most interesting and totally not boring argument, but I feel like I need to second Frequency above: Are there any chances to get another update soon? Maybe one last update before christmas? Also, as far as I understood it, there was a test/demo planned for the end of December. Is that still the case? Or has the demo been moved to January?

Thanks.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 20, 2012, 07:15:21 PM
I don't mean to interrupt this most interesting and totally not boring argument, but I feel like I need to second Frequency above: Are there any chances to get another update soon? Maybe one last update before christmas? Also, as far as I understood it, there was a test/demo planned for the end of December. Is that still the case? Or has the demo been moved to January?

Thanks.
Seconded, great question.

Add to that, is the schedule looking good so far?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tacotime on December 20, 2012, 08:48:43 PM
Hmm, what is this 'golden nonce' ?

I think if you catch the golden nonce, it's worth 150 points and the match is over.

http://www.youtube.com/watch?v=HPVhmZodaLA#t=1m35s


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on December 20, 2012, 09:43:56 PM
Hmm, what is this 'golden nonce' ?

The one (or more) out of the 4294967296 nonces that solve the work and can be submitted & can/will be accepted by the pool server for the task/workload received.
...
Well that's just using the term 'golden' to mean 'valid' or 'share'

(yes I have spent a lot of time looking at nonces :P)

I was meaning that: Was there a specific 'test' nonce that had been referred to as 'THE golden nonce'?
I take all the replies to mean the answer is 'no' - it's just being used as a term for a valid nonce.
Your device generates ~20,116 of them per day per GH/s - so 'golden' seems a bit of an over zealous name :P

In Icarus, what happens to detect the device, is to send specific work to the device and expect a reply with an expected nonce value
Xiangfu called this nonce the 'golden_nonce'
What I did on the cgminer code was find a faster (better) one that took ~0.53ms to calculate so when Xiangfu had roughly 40 Icarus it didn't take long to test them all - only a few seconds.
I just didn't know that people referred to the valid values, in general, as 'golden' - I was wondering if there was a specific work+nonce that was called 'golden' due to some special attributes of it (which the answer is 'no')


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on December 21, 2012, 04:26:40 AM
I don't mean to interrupt this most interesting and totally not boring argument, but I feel like I need to second Frequency above: Are there any chances to get another update soon? Maybe one last update before christmas? Also, as far as I understood it, there was a test/demo planned for the end of December. Is that still the case? Or has the demo been moved to January?

Thanks.
Seconded, great question.

Add to that, is the schedule looking good so far?

Its all the same, Everyone says a 'demo' is coming soon , OCT,NOV,DEC, Jan?
and yet we do not EVEN see ANY prototype devices or simulations, If I can simulate "non-existant" logic on a PC, then surely people with designs should be able to show some "waveform" diagrams..... and yet we see nothing.


I'm going to be releasing my own ASIC product and unlike the competition I will release a die picture.
http://postimage.org/image/5jqixucf3/

4 cores  divided up into 20*2 engines each core giving ~250Ghs or about 25GHs each engine, which is well within the figures currently being bounce about by various teams.
These 4 cores are going to be multiplexed by 8 internal FIFO's, and whilst I won't be delivering product until early April 2013, I think it is well worth getting involved in the investment now.




Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 21, 2012, 05:19:30 AM
I'm going to be releasing my own ASIC product and unlike the competition I will release a die picture.
http://postimage.org/image/5jqixucf3/

A die picture, you say?  It even shows the purdy rainbow diffraction effect.

You would seem to imply that the described die has already been produced.

Surely our collective leg is being pulled...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on December 21, 2012, 08:58:30 AM
Its all the same, Everyone says a 'demo' is coming soon , OCT,NOV,DEC, Jan?

Really? I've only noticed Avalon having a specific, clear goal of demonstrating a working chip around the end of the year.

and yet we do not EVEN see ANY prototype

If they had one, then that would be the demo...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 24, 2012, 01:34:19 AM
@ Team Avalon

What happened to the last Thursday update? (from TSMC?)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ngzhang on December 24, 2012, 01:45:17 AM
@ Team Avalon

What happened to the last Thursday update? (from TSMC?)

everything is going well, everything is going on time.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on December 24, 2012, 08:14:04 AM
@ Team Avalon

What happened to the last Thursday update? (from TSMC?)

everything is going well, everything is going on time.

Great! Any chance of pictures of chips or PCBs any time soon?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 24, 2012, 12:36:48 PM
I see the website has a countdown to shipping time now.

http://www.avalon-asics.com/


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 24, 2012, 12:46:21 PM
@ Team Avalon

What happened to the last Thursday update? (from TSMC?)

everything is going well, everything is going on time.

Great! Any chance of pictures of chips or PCBs any time soon?

They've already said they wouldn't publish this information, but that they wouldn't attempt to prevent customers from doing so. Seems we'll have to wait till they're in the wild to obtain this information.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on December 24, 2012, 01:02:27 PM
@ Team Avalon

What happened to the last Thursday update? (from TSMC?)

everything is going well, everything is going on time.

Great! Any chance of pictures of chips or PCBs any time soon?

They've already said they wouldn't publish this information, but that they wouldn't attempt to prevent customers from doing so. Seems we'll have to wait till they're in the wild to obtain this information.

:(


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: CoinHoarder on December 24, 2012, 05:10:38 PM
I see the website has a countdown to shipping time now.

http://www.avalon-asics.com/

Cool stuff, 27 days.

Good luck team Avalon on reaching your release date! I hope you guys make it!

*** doesn't have anything on team Avalon... maybe you guys should send a few of your employees over to help them out!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 24, 2012, 05:25:56 PM
I see the website has a countdown to shipping time now.

http://www.avalon-asics.com/

Cool stuff, 27 days.

Good luck team Avalon on reaching your release date! I hope you guys make it!


I don't have any orders in with Avalon, but I hope they make it too. If only to light a fire under the companies that can't seem to get out of their own way.

Quote
*** doesn't have anything on team Avalon... maybe you guys should send a few of your employees over to help them out!

Please don't. Let the weak companies fend for themselves or die off. ;D BTC will be better off without them if they can't swim.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 420 on December 24, 2012, 08:15:22 PM
27 days...but can they get one to a customer before February 1?

http://betsofbitco.in/item?id=1003


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 24, 2012, 09:55:42 PM


Quote
*** doesn't have anything on team Avalon... maybe you guys should send a few of your employees over to help them out!

Please don't. Let the weak companies fend for themselves or die off. ;D BTC will be better off without them if they can't swim.
Survival of the most competent!? Wait, where does that leave Inaba?

Seems like your stacking a [un]fair deck. The other companies will need a handicrap handicap at least.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: libertybuck on December 24, 2012, 11:48:45 PM
They've already said they wouldn't publish this information, but that they wouldn't attempt to prevent customers from doing so. Seems we'll have to wait till they're in the wild to obtain this information.

I think you are correct. They should not publish this information. This might lead themselves into mud.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on December 25, 2012, 03:27:03 AM
Survival of the most competent!? Wait, where does that leave Inaba?

It obviously leaves me so far ahead of you that you can't even see me flash my ass at you.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 25, 2012, 06:42:24 AM
Survival of the most competent!? Wait, where does that leave Inaba?

It obviously leaves me so far ahead of you that you can't even see me flash my ass at you.

Of course, that is what the slingshot was for. Your only hope of crossing the finish line!

http://www.pixiepalace.com/bookblog/wp-content/uploads/2009/02/thetortoiseandthehare.jpg


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: libertybuck on December 25, 2012, 06:50:46 AM

Even so creative picture in the world !  :o


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on December 25, 2012, 04:02:35 PM
Survival of the most competent!? Wait, where does that leave Inaba?

It obviously leaves me so far ahead of you that you can't even see me flash my ass at you.

Of course, that is what the slingshot was for. Your only hope of crossing the finish line!

http://www.pixiepalace.com/bookblog/wp-content/uploads/2009/02/thetortoiseandthehare.jpg

OWNED! lol


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cosurgi on December 25, 2012, 06:42:56 PM
I see the website has a countdown to shipping time now.

http://www.avalon-asics.com/
maybe we could make bets whether they ship or not?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mobodick on December 25, 2012, 07:31:22 PM
These chips crunch near a billion hashes per second.  Losing a small handful of those each second is miniscule.

Mine along on your CPU if you wanna make up the difference and then some.
I get a feeling that a longer explanation is required for those unfamiliar with digital logic design.

The issue isn't really about losing one in billions of hashes. It is about gaining the timing margin (a.k.a. overclocking headroom) in the design.

Of course Avalon's logic is secret, but I'm going to discuss the problem based on one of the open-source FPGA hashers. It had a critical timing path in the logic that latched the "golden nonce". Since the design was 125-deep pipelined it had a hardware that subtracted constant 125 from the nonce counter before sending it out of the chip.

Now we have two ways to speed up the above design:

1) remove the 32-bit wide constant subtractor. This will gain a fraction of a nanosecond on every hash tried. It is very easy to subtract 125 in software from the nonce downloaded from the chip.

2) acknowledge that the timing violation may occur and the nonce latched may not be the exact one that solved the block, but a next one or previous one, depending on the details of the latching logic. It is somewhat more involved, but still easily doable in software: recompute the hashes for nonce values n-126,n-125,n-124 and use the one that solved the block. Again this will make the design more tolerant to overclocking for every hash tried inside the chip.

Obviously 1) cannot be applied to the ASIC chip or closed-source FPGA bitstream. But the method 2) remains applicable, just use a different set of test values.


Since it's a pipelined design, wouldn't removing the subtractor just reduce the latency of the pipeline instead of increasing the throughput?
Even if this subtractor would prevent the re-loading of the pipeline than you could pipeline the pipeline and the subtractor.
Since the pipeline will not (i presume) produce a nounce to be latched on every clock you have more than enough time to store the previous nounce on chip and subtract the number before sending it out to the controller.
At least i would make my 'store' circuit parallel to the actual pipeline so it can operate asynchonously.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 2112 on December 25, 2012, 08:27:24 PM
Since it's a pipelined design, wouldn't removing the subtractor just reduce the latency of the pipeline instead of increasing the throughput?
The overall speed of a pipelined logic design is limited by the speed of the slowest stage. In the design I mentioned the last pipeline stage did what every other stage did plus it did the zero comparator, subtractor and a latch.
Even if this subtractor would prevent the re-loading of the pipeline than you could pipeline the pipeline and the subtractor.
Since the pipeline will not (i presume) produce a nounce to be latched on every clock you have more than enough time to store the previous nounce on chip and subtract the number before sending it out to the controller.
At least i would make my 'store' circuit parallel to the actual pipeline so it can operate asynchonously.
I don't think you've ever tried to use Xilinx ISE or something similar. The problem isn't: come up with a different, potentially faster design. The problem is: come up with a working design, the one that the available tools will be capable of synthesizing, and placing/routing sensibly. The overall structure of SHA-2 (which makes every output bit depend on every input bit in each round) is apparently hitting some worst case behavior in the Xilinx toolchain. It takes close to a full day to run a single full implementation. And in many cases the the toolchain either fails to converge to a working implementation or converges to something shamefully inefficient.

On this board 2^256 is frequently thrown around as a number so high that nobody will be able check all of them. Compare this with the work demanded from the Xilinx placing tool: 23038 SLICEs in XC6SLX150 can be permuted in 23028! ways (I'm making a gross simplification of the "place" step) which is about 10^90499. Obviously all digital synthesis tools have to take some heuristic shortcuts through that vast space of available solutions.

So the human art required from the designer is to figuratively take the poor toolchain by the hand an lead it/them to some safe place.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mobodick on December 25, 2012, 09:16:37 PM
Since it's a pipelined design, wouldn't removing the subtractor just reduce the latency of the pipeline instead of increasing the throughput?
The overall speed of a pipelined logic design is limited by the speed of the slowest stage. In the design I mentioned the last pipeline stage did what every other stage did plus it did the zero comparator, subtractor and a latch.
Even if this subtractor would prevent the re-loading of the pipeline than you could pipeline the pipeline and the subtractor.
Since the pipeline will not (i presume) produce a nounce to be latched on every clock you have more than enough time to store the previous nounce on chip and subtract the number before sending it out to the controller.
At least i would make my 'store' circuit parallel to the actual pipeline so it can operate asynchonously.
I don't think you've ever tried to use Xilinx ISE or something similar.
true enough..

Quote
The problem isn't: come up with a different, potentially faster design. The problem is: come up with a working design, the one that the available tools will be capable of synthesizing, and placing/routing sensibly. The overall structure of SHA-2 (which makes every output bit depend on every input bit in each round) is apparently hitting some worst case behavior in the Xilinx toolchain. It takes close to a full day to run a single full implementation. And in many cases the the toolchain either fails to converge to a working implementation or converges to something shamefully inefficient.
lol.,  sorry i even mentioned it.. And no way to work around this?
Quote
On this board 2^256 is frequently thrown around as a number so high that nobody will be able check all of them. Compare this with the work demanded from the Xilinx placing tool: 23038 SLICEs in XC6SLX150 can be permuted in 23028! ways (I'm making a gross simplification of the "place" step) which is about 10^90499. Obviously all digital synthesis tools have to take some heuristic shortcuts through that vast space of available solutions.
Well, thats why you program that thing, right?. The information you give the synthesis tools reduces this space by very much.

Anyway, it would be too off-topic to discuss it here. I take it it is not an easy task.

Quote
So the human art required from the designer is to figuratively take the poor toolchain by the hand an lead it/them to some safe place.

The blackbox art of FPGA programming... :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 420 on December 25, 2012, 11:56:35 PM
I see the website has a countdown to shipping time now.

http://www.avalon-asics.com/
maybe we could make bets whether they ship or not?

Here: http://betsofbitco.in/item?id=1003

and here: http://betsofbitco.in/item?id=1016


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hardcore-fs on December 26, 2012, 04:21:42 AM
These chips crunch near a billion hashes per second.  Losing a small handful of those each second is miniscule.

Mine along on your CPU if you wanna make up the difference and then some.
I get a feeling that a longer explanation is required for those unfamiliar with digital logic design.

The issue isn't really about losing one in billions of hashes. It is about gaining the timing margin (a.k.a. overclocking headroom) in the design.

Of course Avalon's logic is secret, but I'm going to discuss the problem based on one of the open-source FPGA hashers. It had a critical timing path in the logic that latched the "golden nonce". Since the design was 125-deep pipelined it had a hardware that subtracted constant 125 from the nonce counter before sending it out of the chip.

Now we have two ways to speed up the above design:

1) remove the 32-bit wide constant subtractor. This will gain a fraction of a nanosecond on every hash tried. It is very easy to subtract 125 in software from the nonce downloaded from the chip.

2) acknowledge that the timing violation may occur and the nonce latched may not be the exact one that solved the block, but a next one or previous one, depending on the details of the latching logic. It is somewhat more involved, but still easily doable in software: recompute the hashes for nonce values n-126,n-125,n-124 and use the one that solved the block. Again this will make the design more tolerant to overclocking for every hash tried inside the chip.

Obviously 1) cannot be applied to the ASIC chip or closed-source FPGA bitstream. But the method 2) remains applicable, just use a different set of test values.


Since it's a pipelined design, wouldn't removing the subtractor just reduce the latency of the pipeline instead of increasing the throughput?
Even if this subtractor would prevent the re-loading of the pipeline than you could pipeline the pipeline and the subtractor.
Since the pipeline will not (i presume) produce a nounce to be latched on every clock you have more than enough time to store the previous nounce on chip and subtract the number before sending it out to the controller.
At least i would make my 'store' circuit parallel to the actual pipeline so it can operate asynchonously.


for Christ sake.
Why the hell do people assume you need to do a subtraction when  a 'nonce' is found, this is C programming at its worse, by people incapable of thinking in parallel.
Once again for the noobs:
The nonce is calculated BEFORE the SHA256(SHA256(x)), the product of this function is what is evaluated and dictates IF the nonce is a golden value.
Therefore you have ATLEAST 120 clk cycles to calculate the nonce correction (subtraction), before it is needed (if at  all)

The subtraction is only an issue for people that should not be programming logic chips in the first place.

If you have unused gates just "sitting around", please use them.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on December 26, 2012, 05:15:37 AM
Therefore you have ATLEAST 120 clk cycles to calculate the nonce correction (subtraction), before it is needed (if at  all)

Put it through a pipeline the same length as the main calculation - no subtraction at all!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 2112 on December 26, 2012, 06:39:56 PM
Put it through a pipeline the same length as the main calculation - no subtraction at all!
I know that the above was meant to be a joke, but it helps to explain some salient choices that the designer has to make.

Most of the FPGA designers for Bitcoin hashing used the XC6SLX150 chip that has about 150k "gates" and costs about $200.

hardcore-fs is working on XC5VLX110T chip that has about 110k "gates" and costs about $2000.

So where's the catch? Spartan-6 has much less "wires" than Virtex-5, the designs on Spartan-6 are quite oftern routing-constrained: there is enough "gates", but not enough "wires" to connect them. And even if there is enough "wires" then the gate interconnections may be longer and slower than in a design that uses less "gates".

Check out the extreme example of the routing-resource limitation: eldentyrell started working on his "hand-placed, auto-routed" design in October'11. He complained about auto-routing failing and being forced to hand-route until about March'12 when he disclosed that he started using DSP slices for some adders to relieve the congestion of the routing for the general-purpose SLICEs.

https://bitcointalk.org/index.php?topic=49971.msg793740#msg793740

The very same conceptual limitations will apply to the ASIC synthesis. One can spend a lot of time optimizing performance for the particular design flow. Or one can accept most of the default choices to optimize the time it takes to start the manufacturing.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mem on December 27, 2012, 02:17:39 AM
Survival of the most competent!? Wait, where does that leave Inaba?

It obviously leaves me so far ahead of you that you can't even see me flash my ass at you.


It leaves him gnashing his teeth, poor guy So much ego and so little to justify it.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Vicus on December 27, 2012, 08:52:18 AM
If my memory is correct, Team Avalon said, that they will release system image for their hardware at the end of December. End of Dec. is here...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on December 27, 2012, 05:56:43 PM
If my memory is correct, Team Avalon said, that they will release system image for their hardware at the end of December. End of Dec. is here...
+1
You memory is perfectly correct:)

I would like to have it with quick build instructions how to build it from cvs open-wrt


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 28, 2012, 01:22:02 AM
Wasn't there to be a demo of some sort also?

Can't wait for it.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on December 28, 2012, 01:59:13 AM
Wasn't there to be a demo of some sort also?

Can't wait for it.

Yep. If they're on track, we should expect it within the next week or so.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: libertybuck on December 28, 2012, 02:58:41 AM
Hurry up Avalon ! 

ASICMiner has got their ASIC chip. Check this please:  https://bitcointalk.org/index.php?topic=91173.msg1422891#msg1422891


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 28, 2012, 09:43:50 AM
Hurry up Avalon ! 

ASICMiner has got their ASIC chip. Check this please:  https://bitcointalk.org/index.php?topic=91173.msg1422891#msg1422891

Huh, only just now? I thought they taped out early as September, we actually expected them to be online and mining since November. Looks like we over estimated all of our competition.

If my memory is correct, Team Avalon said, that they will release system image for their hardware at the end of December. End of Dec. is here...

Yes, work is progressing on this end, I think I'll get you guys an update within this weekend or so. If anything we will release the openWRT image first and release the updated miner later. but it is not really any different than other Atheros AR7240 CPU, Atheros AR9331 Chipset routers.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on December 28, 2012, 10:27:04 AM
Hurry up Avalon ! 

ASICMiner has got their ASIC chip. Check this please:  https://bitcointalk.org/index.php?topic=91173.msg1422891#msg1422891

Huh, only just now? I thought they taped out early as September, we actually expected them to be online and mining since November. Looks like we over estimated all of our competition.

If my memory is correct, Team Avalon said, that they will release system image for their hardware at the end of December. End of Dec. is here...

Yes, work is progressing on this end, I think I'll get you guys an update within this weekend or so. If anything we will release the openWRT image first and release the updated miner later. but it is not really any different than other Atheros AR7240 CPU, Atheros AR9331 Chipset routers.
Will the USB be like Icarus (PL2303) or something else?
I've been (very slowly) rewriting the cgminer drivers to use libusb, done MMQ, working on BFL, then if there is also a need Icarus.
The new ASIC drivers will of course be based on these USB versions (when I write them)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: spiccioli on December 28, 2012, 10:31:48 AM
Hurry up Avalon !  

ASICMiner has got their ASIC chip. Check this please:  https://bitcointalk.org/index.php?topic=91173.msg1422891#msg1422891

Huh, only just now? I thought they taped out early as September, we actually expected them to be online and mining since November. Looks like we over estimated all of our competition.

If my memory is correct, Team Avalon said, that they will release system image for their hardware at the end of December. End of Dec. is here...

Yes, work is progressing on this end, I think I'll get you guys an update within this weekend or so. If anything we will release the openWRT image first and release the updated miner later. but it is not really any different than other Atheros AR7240 CPU, Atheros AR9331 Chipset routers.
Will the USB be like Icarus (PL2303) or something else?
I've been (very slowly) rewriting the cgminer drivers to use libusb, done MMQ, working on BFL, then if there is also a need Icarus.
The new ASIC drivers will of course be based on these USB versions (when I write them)

kano,

if I'm not wrong, Avalon, is a stand alone unit with an ethernet connection, it is not externally controlled by a miner.

spiccioli


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on December 28, 2012, 10:36:44 AM
Hurry up Avalon !  

ASICMiner has got their ASIC chip. Check this please:  https://bitcointalk.org/index.php?topic=91173.msg1422891#msg1422891

Huh, only just now? I thought they taped out early as September, we actually expected them to be online and mining since November. Looks like we over estimated all of our competition.

If my memory is correct, Team Avalon said, that they will release system image for their hardware at the end of December. End of Dec. is here...

Yes, work is progressing on this end, I think I'll get you guys an update within this weekend or so. If anything we will release the openWRT image first and release the updated miner later. but it is not really any different than other Atheros AR7240 CPU, Atheros AR9331 Chipset routers.
Will the USB be like Icarus (PL2303) or something else?
I've been (very slowly) rewriting the cgminer drivers to use libusb, done MMQ, working on BFL, then if there is also a need Icarus.
The new ASIC drivers will of course be based on these USB versions (when I write them)

kano,

if I'm not wrong, Avalon, is a stand alone unit with an ethernet connection, it is not externally controlled by a miner.

spiccioli

No, it's got a miner in it already :) Which is most likely to be cgminer.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on December 28, 2012, 11:20:03 AM
Yes, work is progressing on this end, I think I'll get you guys an update within this weekend or so. If anything we will release the openWRT image first and release the updated miner later. but it is not really any different than other Atheros AR7240 CPU, Atheros AR9331 Chipset routers.

Any update on avalon flash (will be good also 4/8/16 MB)/RAM(16/32/64/128) memory size (i guess there will be no HDD inside :)

The best will be flash > 4 and RAM >=64 personal opinion. With 8 Flash and 64 or 128 RAM we will be able to do whatever we like install php,web server, vpn or whatever comes handy
10X
PS: If i find a way to make proper cooling for asic unit and there is a hack (which will come with a time)  so that ASIC can be plugged in regular Linux PC i will take that route personally. But this option will not be available from day one though


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on December 28, 2012, 02:38:41 PM
I have a few TL-WR703Ns around already, with their 4MB of flash.  I suppose I could add USB storage if more is needed.

I guess it's possible to solo mine without having to download and store the entire blockchain somewhere.  I've just never seen it done.  I imagine Avalon will just hook up to a pool server or a regular bitcoind node, and not by itself be capable of solo mining, correct?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Raize on December 28, 2012, 03:50:55 PM
I have a few TL-WR703Ns around already, with their 4MB of flash.  I suppose I could add USB storage if more is needed.

I guess it's possible to solo mine without having to download and store the entire blockchain somewhere.  I've just never seen it done.  I imagine Avalon will just hook up to a pool server or a regular bitcoind node, and not by itself be capable of solo mining, correct?

My guess is they'll have a configuration page where you can make edits to the parameters passed to cgminer. I do hope they'll let us ssh into it. If the past firmwares for OpenWRT for Icarus mining is any indication, ngzhang has always went the "be more open" route. I wonder if xiangfu is still around, he had a custom firmware for the 1043ND I used that I really enjoyed.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on December 28, 2012, 04:04:17 PM
PS: If i find a way to make proper cooling for asic unit and there is a hack (which will come with a time)  so that ASIC can be plugged in regular Linux PC i will take that route personally. But this option will not be available from day one though.

Why not, take out the USB cord and plug it into your computer instead, not sure if you want to do this though considering openWRT runs the miners just fine. e.g. cgminer. not to mention there are other airflow reasons you do not want to change the unit, unless you want to run a USB cord out of the unit to an external PC for example.

I have a few TL-WR703Ns around already, with their 4MB of flash.  I suppose I could add USB storage if more is needed.

the openWRT controller is very similar to the TL-WR703n, you can plug in a USB storage if you want.

My guess is they'll have a configuration page where you can make edits to the parameters passed to cgminer. I do hope they'll let us ssh into it. If the past firmwares for OpenWRT for Icarus mining is any indication, ngzhang has always went the "be more open" route. I wonder if xiangfu is still around, he had a custom firmware for the 1043ND I used that I really enjoyed.

We are working with xiangfu, and you are correct. We have always practiced what we preach when it comes to open source. This time will be no different.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 28, 2012, 11:41:06 PM
@ Avalon team

Will there be any demos before you ship out the product?

Have there been any changes to the power usage specs?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: allinvain on December 29, 2012, 05:21:43 AM
Any news/update regarding how much power the final product will consume?



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on December 31, 2012, 06:28:30 PM
Is it my imagination or is this thread sort of abandoned by the Avalon Team?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: DutchBrat on December 31, 2012, 06:30:12 PM
Is it my imagination or is this thread sort of abandoned by the Avalon Team?
Lol you only have to look 3 posts up to find an Avalon Team Member :-)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 01, 2013, 01:04:14 AM
Is it my imagination or is this thread sort of abandoned by the Avalon Team?
Lol you only have to look 3 posts up to find an Avalon Team Member :-)

That's like 3 days ago - practically years in Internet Time!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 01, 2013, 01:07:49 AM
Is it my imagination or is this thread sort of abandoned by the Avalon Team?
Lol you only have to look 3 posts up to find an Avalon Team Member :-)

That's like 3 days ago - practically years in Internet Time!
Well, it's been more than once that I have asked a question but it has gone unanswered. Perhaps they are busy? <shrug>


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Frequency on January 01, 2013, 01:27:33 AM
Is it my imagination or is this thread sort of abandoned by the Avalon Team?
Lol you only have to look 3 posts up to find an Avalon Team Member :-)

That's like 3 days ago - practically years in Internet Time!
Well, it's been more than once that I have asked a question but it has gone unanswered. Perhaps they are busy? <shrug>

Oeoehoe maybe they run the fu(k ... (Sarcasm)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: thorvald on January 01, 2013, 01:48:09 AM
Happy new year 2013 and all the best for you!! Let all dreams come true for every one of You


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on January 01, 2013, 02:19:01 AM
I think the next official update is us shipping out a device. needless to say, we are at the end and is pretty busy at the moment, soon major team members are actually going to stay and live in the factory housing for a few days to make sure everything works out smoothly.

I do not think we will be providing any power consumption/final hashrate prior to shipping the units because we will be tweaking the numbers until we feel it's ready. Soon as we ship everything will become clear.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ninjaboon on January 01, 2013, 02:36:27 AM
Happy new year 2013 and all the best for you!! Let all dreams come true for every one of You


Happy new year 2013 to all ...let's make lots of bitcoins this year...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on January 01, 2013, 02:41:53 AM
Happy new year 2013 and all the best for you!! Let all dreams come true for every one of You


Happy new year 2013 to all ...let's make lots of bitcoins this year...
Approximately 1,314,000 BTC :)
(though since we are expecting diff rises, a diff rise of any reasonable amount at the end of 2013 means that number goes up a bit)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Third Way on January 01, 2013, 07:22:54 AM
I'd love to invest in an ASIC but I only ever really wanted something tiny like one of those Jalapeño types like BFL has.

Still, good luck to everyone that invested in any asic company.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kaerf on January 01, 2013, 10:04:49 AM
I think the next official update is us shipping out a device. needless to say, we are at the end and is pretty busy at the moment, soon major team members are actually going to stay and live in the factory housing for a few days to make sure everything works out smoothly.

I do not think we will be providing any power consumption/final hashrate prior to shipping the units because we will be tweaking the numbers until we feel it's ready. Soon as we ship everything will become clear.

no demo?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on January 02, 2013, 03:16:41 AM
Just thought I'd point out the obvious ...
Since neither myself or ckolivas are involved in the cgminer version you guys are going to put in the Avalon ...
You cannot release your device without also releasing the source code for the cgminer in your device.
Thanks.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 02, 2013, 06:48:18 AM
I think the next official update is us shipping out a device. needless to say, we are at the end and is pretty busy at the moment, soon major team members are actually going to stay and live in the factory housing for a few days to make sure everything works out smoothly.

I do not think we will be providing any power consumption/final hashrate prior to shipping the units because we will be tweaking the numbers until we feel it's ready. Soon as we ship everything will become clear.

no demo?

But I like demos :(


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: gmaxwell on January 02, 2013, 12:01:53 PM
Since neither myself or ckolivas
Would you really endorse a closed source release of cgminer in any case?  And do you really think you can?  There is a lot of code written by other people in cgminer under GPLv2 and GPLv3— including code by Jeff.

Other than avoiding providing source to the general public before the device's actual realize I can't imagine the avalon team having _any_ motivation to release a binary only miner and they can solve that by only distributing the source to the device recipients in order to maximally delay their competition seeing it.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on January 02, 2013, 12:29:53 PM
Since neither myself or ckolivas
Would you really endorse a closed source release of cgminer in any case?  And do you really think you can?  There is a lot of code written by other people in cgminer under GPLv2 and GPLv3— including code by Jeff.

Other than avoiding providing source to the general public before the device's actual realize I can't imagine the avalon team having _any_ motivation to release a binary only miner and they can solve that by only distributing the source to the device recipients in order to maximally delay their competition seeing it.

WTF are you talking about?
There would never be a closed source cgminer.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: gmaxwell on January 02, 2013, 01:19:39 PM
WTF are you talking about?
There would never be a closed source cgminer.
Good to hear. I thought what I was talking about was clear enough.

Let me try talking a bit louder:
Quote from: kano
Since neither myself or ckolivas are involved in the cgminer version you guys are going to put in the Avalon ...
You cannot release your device without also releasing the source code for the cgminer in your device.
Is it more clear now? It sounds like you were saying that if and only if you or ckolivas were involved a vendor could release a cgminer based product without source. I don't believe this is correct, and I'm glad to hear you wouldn't consider it.  I suppose instead you meant "since we're not involved maybe thats evidence you were not planning on releasing the source"? I don't see how that follows, but OKAY. In any case, perhaps now you can see how your message could be read another way?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: gyverlb on January 02, 2013, 02:08:37 PM
WTF are you talking about?
There would never be a closed source cgminer.
Good to hear. I thought what I was talking about was clear enough.

Let me try talking a bit louder:
Quote from: kano
Since neither myself or ckolivas are involved in the cgminer version you guys are going to put in the Avalon ...
You cannot release your device without also releasing the source code for the cgminer in your device.
Is it more clear now? It sounds like you were saying that if and only if you or ckolivas were involved a vendor could release a cgminer based product without source. I don't believe this is correct, and I'm glad to hear you wouldn't consider it.  I suppose instead you meant "since we're not involved maybe thats evidence you were not planning on releasing the source"? I don't see how that follows, but OKAY. In any case, perhaps now you can see how your message could be read another way?

I guess that if both ckolivas and kano were involved, as they are by far the main contributors to the source, given enough time they could replace any code commited by other contributors in cgminer by a brand new reimplementation. They would then be able to licence the resulting code the way they want. That's theoretical though and could prove difficult in practice (some parts of cgminer might need a clean-room reimplementation that neither ckolivas and kano would be suitable developers for given their knowledge of it) and this theoretical possibility is only used by kano as a demonstration argument given his later answer.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: gmaxwell on January 02, 2013, 03:06:43 PM
I guess
Well, I actually went through the codebase and history some before commenting.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: gyverlb on January 02, 2013, 04:01:56 PM
I guess
Well, I actually went through the codebase and history some before commenting.
I did too and didn't find much in recent history: contributors in December essentially brought device specific code which could be removed for an ASIC specific cgminer. I guess ;) you were more thorough in your codewalk.

That's one reason I used "theoretical" for this approach: it's hard to evaluate the amount of work needed to remove past contributions when you want to relicense a codebase. From a purely ideological point of view I must say I think this is a good thing: when you originally use the GPL and grow a community of developers around your project it shouldn't be easy to remove past contributions that helped the project mature to profit on your own from the codebase.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on January 02, 2013, 05:35:46 PM
Not disparaging the Avalon team, as I have no idea what they are planning... but it's not like China has a great track record when it comes to IP and copyrights.  If they did release it without the source, realistically, what is the recourse?  Pretty much zip.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 02, 2013, 05:40:42 PM
Other than avoiding providing source to the general public before the device's actual realize I can't imagine the avalon team having _any_ motivation to release a binary only miner

A binary release will need to be shipped in the Avalon device itself (compiled to run on Atheros MIPS), if it's to be ready to operate out-of-the-box.

I trust that they will release the source also.  I believe they have commented saying that they will.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 02, 2013, 09:30:20 PM
Not disparaging the Avalon team, as I have no idea what they are planning... but it's not like China has a great track record when it comes to IP and copyrights.  If they did release it without the source, realistically, what is the recourse?  Pretty much zip.


Your statement lacks some degree of context and thus it is difficult to see what exactly you are driving at.  It almost looks like kind of a random flailing against an 'adversary' (I have not yet determined if BFL and Avalon are 'competitors'.)  But anyway...

One dis-advantage of their not adhering to open-source principles to a realistic degree would be loss of sales and support by at least a segment of the community.

My observation is that the 'problem' of intellectual property theft in many areas is diminishing.  I believe that a primary reason for this is that the open-source world offers superior solutions in many cases.  Much of the closed-source world is actually a lot of hot air and/or deeply troubled code which would be dis-advantageous to employ for long-term value projects.

Anyway, I'm not buying shit from anyone until they can demonstrate a working solution, and then I'll determine whether what they are selling is worth having.  And open-source will be a HUGE part of who I send my BTC/USD to.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on January 02, 2013, 10:58:14 PM
How is that "flailing against an adversary" exactly?  Either it applies to the Avalon team and there's jack all anyone can/will do about it or it does not apply to the Avalon team so it doesn't matter.  Or are you seriously trying to deny the fact that China has a piss poor record of honoring IP protection laws?  Or... are you just being an apologist for the poor adherence to IP laws?




Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Syke on January 02, 2013, 11:13:33 PM
How is that "flailing against an adversary" exactly?  Either it applies to the Avalon team and there's jack all anyone can/will do about it or it does not apply to the Avalon team so it doesn't matter.  Or are you seriously trying to deny the fact that China has a piss poor record of honoring IP protection laws?  Or... are you just being an apologist for the poor adherence to IP laws?

What "China" does is irrelevent. The Avalon team has a known history of releasing Open Source stuff. That's what matters.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: meowmeowbrowncow on January 02, 2013, 11:15:57 PM
Not disparaging the Avalon team, as I have no idea what they are planning... but it's not like China has a great track record when it comes to IP and copyrights.  If they did release it without the source, realistically, what is the recourse?  Pretty much zip.




Troll spotted.  Shields up.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kaerf on January 02, 2013, 11:42:11 PM

What "China" does is irrelevent. The Avalon team has a known history of releasing Open Source stuff. That's what matters.

+1. Such broad sterotyping of chinese people/groups is getting close to racism. Like Syke said, Avalon should be judged by their past actions.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 02, 2013, 11:45:23 PM
How is that "flailing against an adversary" exactly?  Either it applies to the Avalon team and there's jack all anyone can/will do about it or it does not apply to the Avalon team so it doesn't matter.  Or are you seriously trying to deny the fact that China has a piss poor record of honoring IP protection laws?  Or... are you just being an apologist for the poor adherence to IP laws?



The USA has large community of people not honoring IP protection laws, despite many laws on the books. You can't search Google without tripping over these English sites.

The rate of convictions is very tiny compared to the size of the offenders.

Take a look at three links that you can find on Google.

http://www.slyck.com/ <--- One community hub found on google.com
http://torrentfreak.com/ <--- Another community hub found on google.com
http://forum.doom9.org/ <-- I am actually a member here. Great technical discussion(s) of all kinds. Some of the forum members here cracked Bluray encryption when it first came out. (Publicly!)

Doom9 forums is also where that particular community pushed for Google Server operators to upgrade their use of Vp6 and Vp7 (Flash) and H.263/H.264 open source code software. Resulting in Googles upgrade of their YouTube platform to "Youtube HD". (Just because they asked an operator why they were still using an old buggy version).

So if you use Youtube, the encoding software was designed and discussed on those forums.

-----------------------

I do not know if Youtube publishes their various components that make use of open software in their services. I believe they only provide the link to the source code if you request it. (Per the GPL rules)

That is just one tiny example.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on January 03, 2013, 12:04:50 AM

What "China" does is irrelevent. The Avalon team has a known history of releasing Open Source stuff. That's what matters.

+1. Such broad sterotyping of chinese people/groups is getting close to racism. Like Syke said, Avalon should be judged by their past actions.

Yes, because commenting on well established facts (http://www.eetimes.com/electronics-news/4396272/Innovations--borrowed--digested-and-re-invented--are-legit-) about a country (http://online.wsj.com/article/SB10001424052702303624004577339351934437474.html) is stereotyping of Chinese people... That makes perfect sense.  Fucking idiot.

The whole point is that even if Avalon decided to release a binary only version of CGMiner, what are the developers going to do about it?  Nothing.. zip.  Nada.  There's nothing they can do realistically.  That is the point, besides the one on the top of your and PuertoIdiot's head.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Carlton Banks on January 03, 2013, 12:12:30 AM

What "China" does is irrelevent. The Avalon team has a known history of releasing Open Source stuff. That's what matters.

+1. Such broad sterotyping of chinese people/groups is getting close to racism. Like Syke said, Avalon should be judged by their past actions.

Be fair on him, he probably forgot which trolling account he was logged into and accidentally went into super offensive mode. Must be difficult having to juggle so many different personas without them leaking into each other, even for an outright professional troll. I applaude you for your commitment Josh, you're the most hard working troll I've seen in the wild. Don't take this the wrong way either, you really are very good a being an absolute dick.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kaerf on January 03, 2013, 12:14:04 AM

What "China" does is irrelevent. The Avalon team has a known history of releasing Open Source stuff. That's what matters.

+1. Such broad sterotyping of chinese people/groups is getting close to racism. Like Syke said, Avalon should be judged by their past actions.

Yes, because commenting on well established facts (http://www.eetimes.com/electronics-news/4396272/Innovations--borrowed--digested-and-re-invented--are-legit-) about a country (http://online.wsj.com/article/SB10001424052702303624004577339351934437474.html) is stereotyping of Chinese people... That makes perfect sense.  Fucking idiot.


whoa...there. calling your customer of multiple orders a fucking idiot is not good business practice. i made a point (even took your name out of the quote) of not outright calling your statement racist to give you the benefit of the doubt and give you the opportunity to clarify your statement.

josh, we're not talking about China. We're talking about the Avalon team (who happen to be chinese). Are you a 300 lb american that reeks of BO (http://en.wikipedia.org/wiki/Obesity_in_the_United_States)?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: DirtAddsHP on January 03, 2013, 12:17:37 AM
looking forward to seeing these in use.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on January 03, 2013, 12:23:52 AM

What "China" does is irrelevent. The Avalon team has a known history of releasing Open Source stuff. That's what matters.

+1. Such broad sterotyping of chinese people/groups is getting close to racism. Like Syke said, Avalon should be judged by their past actions.

Yes, because commenting on well established facts (http://www.eetimes.com/electronics-news/4396272/Innovations--borrowed--digested-and-re-invented--are-legit-) about a country (http://online.wsj.com/article/SB10001424052702303624004577339351934437474.html) is stereotyping of Chinese people... That makes perfect sense.  Fucking idiot.


whoa...there. calling your customer of multiple orders a fucking idiot is not good business practice. i made a point of not outright calling your statement racist to give you the benefit of the doubt and give you the opportunity to clarify your statement.

josh, we're not talking about China. We're talking about the Avalon team (who happen to be chinese). Are you a 300 lb american that reeks of BO (http://en.wikipedia.org/wiki/Obesity_in_the_United_States)?

Then don't write stupid shit and try to paint me as a racist and I won't call you a fucking idiot.  Pretty simple, huh? 

There is no clarification of my statement needed.  If you're not capable understanding the basic written word, I can't help you.  Trying to couch what I wrote, which is an established and acknowledged fact about the laws in a given country as somehow racist, then you are far beyond help and hope.  How the hell you got from talking about the laws of China to racism, I can not fathom, but it's probably some deep seated latent racism on your part, since typically the most racist people tend to see racism everywhere.

To answer your question, no I'm not a 300 lb American that reeks of BO, are you?  I'm not sure what that has to do with anything that's being discussed, but perhaps, again, it's something you have a deep seated, latent fear of or trouble with?
 


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 03, 2013, 12:32:46 AM

What "China" does is irrelevent. The Avalon team has a known history of releasing Open Source stuff. That's what matters.

+1. Such broad sterotyping of chinese people/groups is getting close to racism. Like Syke said, Avalon should be judged by their past actions.

Yes, because commenting on well established facts (http://www.eetimes.com/electronics-news/4396272/Innovations--borrowed--digested-and-re-invented--are-legit-) about a country (http://online.wsj.com/article/SB10001424052702303624004577339351934437474.html) is stereotyping of Chinese people... That makes perfect sense.  Fucking idiot.

The whole point is that even if Avalon decided to release a binary only version of CGMiner, what are the developers going to do about it?  Nothing.. zip.  Nada.  There's nothing they can do realistically.  That is the point, besides the one on the top of your and PuertoIdiot's head.

Focusing in on one nationality does look racist.

The reality is Human beings misappropriate IP or simply don't adhere to the philosophy of Intellectual Property. Beyond the fact that there are 1.2 or 1.1 Billion Chinese and only 300 Million-ish Americans probably throws those statistics out of proportion. I have no clue how many European or Eurasians there are...but they also do pirate and steal IP. (Even at a corporate level)

All I can tell you for certain is that focusing in on Chinese people is improper as Humanity as a whole does it. Most of the software being misappropriated is coming from a ton of different regions and nationalities.

The Chinese people have no more propensity to steal IP (Intellectual Property) than the rest of Humanity.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kaerf on January 03, 2013, 12:38:36 AM
josh, you're too funny. i'll elect to discontinue this particular conversation with you since it does not appear it will get anywhere. i myself am not a fan of minority activist groups for the same reason you said (people that are minority activists are often racist themselves). however, we must agree to disagree here. you don't see your statement as a sterotype, i do. we do not need to fling profanities at each other in an attempt to change our minds.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Syke on January 03, 2013, 12:45:01 AM
The whole point is that even if Avalon decided to release a binary only version of CGMiner, what are the developers going to do about it?  Nothing.. zip.  Nada.  There's nothing they can do realistically.  That is the point, besides the one on the top of your and PuertoIdiot's head.

What are people going to do when BFL declares bankrupcy after having spent all the pre-order funds? Nada. There's nothing they can do realistically.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 03, 2013, 12:48:50 AM
Here is a good example:

There was once a company called CoreCodec who had designed the fastest H.264 decoder (http://en.wikipedia.org/wiki/H.264/MPEG-4_AVC). They opened some of the code if I recall correctly. Then they stopped and closed sourced it.

The open source folks used their designs to incorporate some of the techniques and to gather ideas as to how it was done. The Open Source folks progressive efforts eventually paid off (through hard work) and eventually designed better decoders with higher efficiency.

That lead to widespread adoption of H.264 which until then was very near impossible to play on a normal PC without serious stuttering in the picture and playback. That spawned off dedicated "encoders" who worked with the pirates to rip thousands and thousands of movies into a highly compressed and efficient formats using the [open source] H.264 encoders and decoders.

That spawned alot of the big companies use of Online Video.

----------------------

The Closed Source company tried to sue the open source people a few times under the allegations of stealing IP. The Open Source folks laughed at them (some of the time) because they found out through reverse engineering of the software that they cut many corners to achieve their incredible performance. (Lots of allegations abound)

The closed source company CoreCodec eventually went on to sell their codec software and (I think) they were sufficiently successful. But what did they find when they went CES? (You know, where BFL is demoing non-existent ASICs)

They found that quite a few demo'ing companies in the other booths were using derivatives of their software. How did they know this? They figured it out because they put in easter eggs in their own software. While playing with the demonstration software, several companies were found to be using their IP....without payment...at CES.

They first asked and later persued some of them for misappropriation of their IP.

------------------------------

Big or small, corporate or individual, some people do not honor IP. It's not a Chinese issue. It is all over the world.

Last I recall the Chinese Government was working pretty hard to crack down on IP violations and piracy in their hopeful admittance to the WTO (World Trade Organization) and becoming a member of something...which I do not recall what it was anymore.

Edit: Forgot what the WTO was called. It's been years!
http://en.wikipedia.org/wiki/WTO


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on January 03, 2013, 02:05:48 AM
Kaerf and PuertoLibre, you two are the only ones focusing in on people.  I made mention of Chinese IP laws (or lack thereof, or lack of enforcement, take your pick) and made absolutely no mention of people.

How the two of you go from this:

Quote
but it's not like China has a great track record when it comes to IP and copyrights.  If they did release it without the source, realistically, what is the recourse?  Pretty much zip.

to

OMG RACISM!  is truly a mystery, and one best left unplumbed I would wager.  I'm frightened as to what I might find in the minds of people who can't connect two simple dots sitting right next to each other.

PS -

Quote
Last I recall the Chinese Government was working pretty hard to crack down on IP violations and piracy in their hopeful admittance to the WTO (World Trade Organization) and becoming a member of something...which I do not recall what it was anymore.

Why would they be doing this if it's not a huge problem in China?  If it was just as rampant all over the world, how could they be rejected from the WTO on those grounds and why would they need to curb it?  Logic fail.




Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mem on January 03, 2013, 02:39:44 AM
josh, we're not talking about China. We're talking about the Avalon team (who happen to be chinese). Are you a 300 lb american that reeks of BO (http://en.wikipedia.org/wiki/Obesity_in_the_United_States)?

http://gifsoup.com/webroot/animatedgifs4/3415857_o.gif

Josh is typing an angry reply right now.

Then don't write stupid shit and try to paint me as a racist and I won't call you a fucking idiot.  Pretty simple, huh? 
You are the twerp making broad sweeping generalizations against a nation.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 03, 2013, 03:30:36 AM
The Chinese people have no more propensity to steal IP (Intellectual Property) than the rest of Humanity.

I think his point is that the GPL has held up well in some courts (such as in the US and Europe) but some quick Googling shows that this may not be the case in China.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 03, 2013, 03:42:17 AM
Is it more clear now? It sounds like you were saying that if and only if you or ckolivas were involved a vendor could release a cgminer based product without source.

How on earth did you manage to interpret it that way?

The prior probability of an open source developer and long term community member offering a closed source version for a hardware vendor seems to be very low...low enough that an ambiguous forum post should not be sufficient evidence to believe that this may be the case. It is significantly more probable, before even reading the post, that he wants to make sure the source is available, quite possibly so that it can be merged into the main branch.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: greyhawk on January 04, 2013, 09:03:26 AM
This is the best Avalon thread.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ewibit on January 04, 2013, 09:50:09 PM
I hope this clock is true:
http://www.avalon-asics.com/
and here we see what was and is:
http://www.timeanddate.com/countdown/to?iso=20121126T10&p0=405&fg1=ea0606&fg2=808080&msg=BFL+|+ASIC+-+FIRST+SHIPMENT
...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: repentance on January 06, 2013, 12:34:27 AM

Seriously can people stop posting non Avalon crap in here so that others don't have to reply to the crap.

Others don't have to reply to the crap and it would probably be a good idea for each of the vendors to start a locked update thread so that people don't need to hunt around in the discussion threads to find the latest information.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 06, 2013, 01:17:44 AM
I think the next official update is us shipping out a device. needless to say, we are at the end and is pretty busy at the moment, soon major team members are actually going to stay and live in the factory housing for a few days to make sure everything works out smoothly.

I do not think we will be providing any power consumption/final hashrate prior to shipping the units because we will be tweaking the numbers until we feel it's ready. Soon as we ship everything will become clear.

Can we get confirmation that this means no demo? :(


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Raize on January 06, 2013, 07:42:27 PM
Quote
In fact, it is within our schedule to release the controller ( openWRT ) image.iso before the end of the year to give eager developers a head start to spin your own custom mining setups. Embrace open source!

Does anyone know if the ISO for OpenWRT has been released? I can't find it in this thread.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: punin on January 06, 2013, 08:11:42 PM
Thank you gmaxwell for cleaning this thread up.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on January 08, 2013, 01:16:07 PM
So I've been neglecting emails a bit mostly because I am on the road and there has been tons of people recently asking when the second batch will be on sale, mixed with actual support problems I am sorting through, so I apologize in advance for any emails that should've been replied to but have yet to hear from. There's no doubt that crunch time is now and everyone inolved with Avalon is currently extremely busy. I will do my best to answer as much email as possible, once I am stationary on the 10th I suspect only then I'll be able to catch up.

Here's some notes:
1. please stop asking when Avalon will be available again for purchase, we will make an announcement when that happens.

2. We've mentioned before we will try to ship as much as possible before CNY, just exactly how many we can ship out can only be revealed when we start shipping and making estimates based on workflow. There will be another update regarding this matter once shipping starts, we at Avalon currently do not have the answer to this question unfortunately.

3. It is extremely important for our existing customer to verify that your Order's Address, Name and such shipping information is correct. In addition if your Order is still not marketed as "Completed" on our site please get in touch with me immediately, failure to do this will delay your shipping.

4. Regarding openWRT image, this is still a working progress, but I suspect in the next few days it will be ready, regardless it will and it have to be released before the actual product ships, so it is only a matter of time.

5. there's currently no problem that can cause change in delivery date, everything else is on schedule.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: spiccioli on January 08, 2013, 01:35:34 PM

3. It is extremely important for our existing customer to verify that your Order's Address, Name and such shipping information is correct. In addition if your Order is still not marketed as "Completed" on our site please get in touch with me immediately, failure to do this will delay your shipping.


Hi BitSyncom,

My order is listed as "Order #200000nnn - Bitcoin Payment Completed", so I take it as it is "Completed" for you, am I right?

Thanks

spiccioli.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on January 08, 2013, 01:51:18 PM
Correct, if your order status does not include the word Completed in it, you should get in touch with me ASAP.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Baphomet on January 08, 2013, 01:58:40 PM
Thanks for the update. Hopefully getting in on the second wave of orders isn't just going to be luck of being online at the right time but i can't imagine many other ways to do it.
Compared to all the other ASIC producers Avalon seem far more organised and transparent/honest with information and customer relations and it makes me want to spend my money here rather than anywhere else.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Dhomochevsky on January 08, 2013, 02:47:56 PM
I wanted to ask how can I get you guys to ship my order using EMS Expedited instead of DHL. I used DHL for some imports from China last fall and I got into all sorts of problems at customs because of them. EMS worked just fine for me back when I ordered my Icarus boards from Zhang, and they took about a week - a week and a half to arrive. I also had some questions regarding invoices. Do I need to send you a mail at the address I received updates from? Or is there some other I should use?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Vicus on January 08, 2013, 03:32:08 PM
I wanted to ask how can I get you guys to ship my order using EMS Expedited instead of DHL. I used DHL for some imports from China last fall and I got into all sorts of problems at customs because of them. EMS worked just fine for me back when I ordered my Icarus boards from Zhang, and they took about a week - a week and a half to arrive. I also had some questions regarding invoices. Do I need to send you a mail at the address I received updates from? Or is there some other I should use?
Yes, very good question. Shipment date is near and we need to make a choice.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: thorvald on January 08, 2013, 03:42:24 PM
I have a question regarding the value submitted to customs .
Can you submit a different value than the payed value ?
I have to pay over 35% in vat+tax.
Regards
Thorvald


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on January 08, 2013, 03:45:59 PM
I wanted to ask how can I get you guys to ship my order using EMS Expedited instead of DHL. I used DHL for some imports from China last fall and I got into all sorts of problems at customs because of them. EMS worked just fine for me back when I ordered my Icarus boards from Zhang, and they took about a week - a week and a half to arrive. I also had some questions regarding invoices. Do I need to send you a mail at the address I received updates from? Or is there some other I should use?

I've updated the thread to reflect that DHL and EMS are choices, as it stands the unit is more heavy than what we originally expected because we want to built a nice solid product, due to it's size, DHL is in fact cheaper than EMS at this moment. In the next few days, I expect to sent out a News Letter with a form which allow the users to pick their Carrier of Choice, currently all Orders are defaulted to DHL.

I understand invoicing will be an issue, we are still speaking with some companies in HK/Shenzhen that specialize in  exporting products from china to selected countries, I believe they will be handling the product invoices, the news letter will also address this issue.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on January 08, 2013, 03:58:50 PM
About Invoicing...
The best option will be to name AVALON as "Computer Configuration" in the invoice

1. There are no additional taxes involved in my country when importing computers except VAT which can not be avoided
2. There will be no issues because it is crypto equipment named like "ordinary PC" and no additional customs check will be applied if it is double purpose or not. When speaking of Cryptography Import/Export rules, they are very strict in my country (and all over EU) and it may happen that some of the EU customers will not be able to get the unit at all from the customs
What about it BitSyncom?
Anyone to have something against naming our units as "Computer Configuration"? If we all agree on that it will be eraser for BitSyncom to handle invoices because all of them will be same for "Computer Configuration"?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Aseras on January 08, 2013, 04:08:01 PM
I think that since it's the first batch, they should all be sent out as engineering sample or demo units.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: greyhawk on January 08, 2013, 04:11:06 PM
Yes, please try to circumvent customs duties. This is going to end well.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on January 08, 2013, 04:12:12 PM
I think that since it's the first batch, they should all be sent out as engineering sample or demo units.



Dude,
If they can send them as demo units this mean no VAT:) But custom officers are very suspicious in my country so i personally prefer to pay 20% VAT on top just to be on a safe side.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ewibit on January 08, 2013, 04:14:52 PM
About Invoicing...
The best option will be to name AVALON as "Computer Configuration" in the invoice

1. There are no additional taxes involved in my country when importing computers except VAT which can not be avoided
2. There will be no issues because it is crypto equipment named like "ordinary PC" and no additional customs check will be applied if it is double purpose or not. When speaking of Cryptography Import/Export rules, they are very strict in my country (and all over EU) and it may happen that some of the EU customers will not be able to get the unit at all from the customs
What about it BitSyncom?
Anyone to have something against naming our units as "Computer Configuration"? If we all agree on that it will be eraser for BitSyncom to handle invoices because all of them will be same for "Computer Configuration"?
this is a good idea to declare it as a computer
and what is the best choice for shipping? (DHL or EMS or another for prices, customs check and shipping time) for EU (D, A,...etc.)
TIA


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: spiccioli on January 08, 2013, 05:10:04 PM

In the next few days, I expect to sent out a News Letter with a form which allow the users to pick their Carrier of Choice, currently all Orders are defaulted to DHL.


BitSyncom,

I've never received a mail from you (previous updates) even if inside store.avalon-asic.com my email address is correctly spelled.

Is there some other place where you're taking email addresses from?

spiccioli


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Tinua on January 08, 2013, 05:26:37 PM
If it is not marked as an engineering sample or demo, you can have great problems on custom because of the missing CE mark!
Or i'm wrong?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: SolarSilver on January 08, 2013, 05:34:09 PM
I have a question regarding the value submitted to customs .
Can you submit a different value than the payed value ?
Please don't do this, it will only create problems with customs and it will delay your order while they sort out the real price.

I had 4 packages stuck for over 6 weeks because the listed prices were wholesale and customs argued it undercut the official listed prices on the website (end-user prices).

Trying to ship items as samples or gifts will only attract unwanted attention, and at this point I'd prefer things to breeze through customs instead of getting them after March....

Anyways, this has been addressed in this thread before


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Raize on January 08, 2013, 06:10:05 PM
I think the reason why everyone is emailing you directly asking about preorders for the second batch is because several of us signed up for the email notifications and did not get notified when the preorders for the first batch went online. I didn't care about this for my own sake, because I was planning on waiting for a far future batch to get involved, but I have a very upset client that very much wanted at least one of the first batch ASICs for me to mine for him. I can assure you, the second batch is going to sell out in less than 15 minutes if you just "go online" with it, even if the quantities are in the thousands, because your company appears to be the first to market.

Yifu, I implore you to get an honest estimate of the demand for the product from the community for a second batch when you are comfortably ready to tackle this, because you guys are going to need to be able to scale your production very quickly. I can assure you that 300 units isn't going to be anywhere near enough. It doesn't have to be an estimate of "guaranteed preorders", but you should be getting the email & phone number (SMS) of anyone interested in ordering for the second batch, and an estimate of how many products they would like. Then you can determine how big your next batch should be, and open up the actual preordering and send emails and text notifications accordingly. You should also lower the price slowly instead of quickly, but that might be a discussion for another time, you can hire staff to tell you how to best do this shortly.

At the very least I'd recommend committing to the same price till you have a batch order that comes in at a smaller size than the previous order. Some of us will be waiting for future batches or buying ASIC miners secondhand after the enormous price spike and bubble burst that is likely to happen because of this, but the one thing you want to do is to always meet expectations, let people make their own financial mistakes themselves.

I honestly think this is going to be the equivalent of a gold rush, so your best move is to assist the fools in their demise. The Bitcoin network will get stronger because of it, either way.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ewibit on January 08, 2013, 06:34:57 PM
If it is not marked as an engineering sample or demo, you can have great problems on custom because of the missing CE mark!
Or i'm wrong?
there have been a few people in EU that have still bought FPGA's from this company. How have these done this? Perhaps they should share their experiences with this deals (shipping, custom, invoice etc.)...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 08, 2013, 07:12:06 PM
About Invoicing...
The best option will be to name AVALON as "Computer Configuration" in the invoice

1. There are no additional taxes involved in my country when importing computers except VAT which can not be avoided
2. There will be no issues because it is crypto equipment named like "ordinary PC" and no additional customs check will be applied if it is double purpose or not. When speaking of Cryptography Import/Export rules, they are very strict in my country (and all over EU) and it may happen that some of the EU customers will not be able to get the unit at all from the customs
What about it BitSyncom?
Anyone to have something against naming our units as "Computer Configuration"? If we all agree on that it will be eraser for BitSyncom to handle invoices because all of them will be same for "Computer Configuration"?
I highly recommend you all make these suggestions (on importation declarations) in private and away from BFL's prying eyes.

Unless you want possible trouble.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Tinua on January 08, 2013, 07:57:21 PM
If it is not marked as an engineering sample or demo, you can have great problems on custom because of the missing CE mark!
Or i'm wrong?
there have been a few people in EU that have still bought FPGA's from this company. How have these done this? Perhaps they should share their experiences with this deals (shipping, custom, invoice etc.)...
The FPGAs were a PCB with chip!
The Avalons come as a stand-aloneminer in a large sealed enclosure!
Thus this, it is a finished unit and may need to meet CE policies for EU!
But, i'm not expert in this!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 08, 2013, 08:13:05 PM
http://i49.tinypic.com/rwv1hi.jpghttp://i46.tinypic.com/bfmcya.jpg

Courtesy of:

http://www.mathcats.com/explore/elapsedtime.html

Just re-posted to make a strong point.

The Avalon Team is as far ahead of schedule as BFL is behind in their own schedule.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: dust on January 08, 2013, 08:25:48 PM
3. It is extremely important for our existing customer to verify that your Order's Address, Name and such shipping information is correct. In addition if your Order is still not marketed as "Completed" on our site please get in touch with me immediately, failure to do this will delay your shipping.
I checked my account and my order was listed as "cancelled", despite having paid for it immediately after ordering in September.  I looks like I failed to confirm my order.  I have created a support ticket (#25).

<panic>EDIT:  Re-reading this thread, it looks like I may be screwed.  I really hope I don't get kicked out of the first batch due to not wading through a troll-filled thread enough to realize that not responding to email = spot given up.  Here was the email:

Quote
Your order # 2000001XX has been updated to
Pending.

You can check the status of your order by logging into your account.

Can you provide the Bitcoin Order ID as well as the Bitcoin Address of payment so I may confirm this order?

If you have any questions, please feel free to contact us at info@avalon-asic.com

I logged into my account, saw the status as pending and the correct payment address listed and with coins received, then took no action.  I must have felt that the bitcoin order ID and address already being in Avalons system and paid for did not require me to provide additional information (as in, I had "confirmed" it was correct).  I unfortunately was never told specifically my order would be CANCELLED if this was not done and no coins were ever sent back to me.

I hope this gets resolved.

This + the bASIC delay has made today a pretty bad day >:(</panic>


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on January 09, 2013, 06:30:15 AM
@dust

if you recall there some server problem when the site first launched, please send me a email/PM with your bitcoin order ID and payment address so I may manually check aganist the system.

The system was automatically set orders to cancel if they have not been paid, and since due to server errors some order which got paid never got the call back to mark them as completed thus were in turn canceled.

No worries though, we keep all the records so we can double check aganist this.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: klondike_bar on January 10, 2013, 10:41:03 PM
Still on track for the 20th?

I assume this will be when pre-orders go out (or start to). When will general sales start?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 10, 2013, 10:57:19 PM
When will general sales start?

I do believe that no more are planned to be produced (or even available to pre-order I think) until after the Chinese New Year.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: jiangchun on January 11, 2013, 02:07:04 AM
When will general sales start?

I do believe that no more are planned to be produced (or even available to pre-order I think) until after the Chinese New Year.

the CNY is 2.10 ,so the chinese worker  not work and  go home 2.5-2.25.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: dust on January 12, 2013, 05:43:32 AM
@dust

if you recall there some server problem when the site first launched, please send me a email/PM with your bitcoin order ID and payment address so I may manually check aganist the system.

The system was automatically set orders to cancel if they have not been paid, and since due to server errors some order which got paid never got the call back to mark them as completed thus were in turn canceled.

No worries though, we keep all the records so we can double check aganist this.
Any update on this?  I sent a PM within 15 minutes of your reply and have received no response or update to my ticket  I'm sure the team is busy :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 12, 2013, 05:47:41 AM
Will tracking numbers be shown on the website order status page or be emailed to customers when they ship?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cedivad on January 12, 2013, 05:53:45 AM
Anyway... Not to break the Avalon's Gold Eggs...

But where is the prototype scheduled to be released on video 20 days ago? 20 - 10 days of "possible delay" = 10 days without our video!

:D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: server on January 12, 2013, 12:28:38 PM
@dust

if you recall there some server problem when the site first launched, please send me a email/PM with your bitcoin order ID and payment address so I may manually check aganist the system.

The system was automatically set orders to cancel if they have not been paid, and since due to server errors some order which got paid never got the call back to mark them as completed thus were in turn canceled.

No worries though, we keep all the records so we can double check aganist this.
Any update on this?  I sent a PM within 15 minutes of your reply and have received no response or update to my ticket  I'm sure the team is busy :)

+1

Why no pm and no answers Yifu ?
Some of us are worried about this and you asked us to respond a.s.a.p....


3. It is extremely important for our existing customer to verify that your Order's Address, Name and such shipping information is correct. In addition if your Order is still not marketed as "Completed" on our site please get in touch with me immediately, failure to do this will delay your shipping.




Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on January 12, 2013, 04:24:33 PM
It will cause delay once we start shipping, it was pretty much a heads up before the 20th. I'll get to you guys early next week. I simply haven't gotten around to double check yet due to being swarmed.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: server on January 12, 2013, 04:26:58 PM
It will cause delay once we start shipping, it was pretty much a heads up before the 20th. I'll get to you guys early next week. I simply haven't gotten around to double check yet due to being swarmed.

Ok, clear, thanks and good luck :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 12, 2013, 04:32:15 PM
Will tracking numbers be shown on the website order status page or be emailed to customers when they ship?

Well I hope so.

The day it's to arrive I plan to take off from work to receive it in case it requires a signature.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on January 12, 2013, 04:33:43 PM
Will tracking numbers be shown on the website order status page or be emailed to customers when they ship?

Well I hope so.

The day it's to arrive I plan to take off from work to receive it in case it requires a signature.

Yes of course, it'll be updated both on the site as well as emailed to you.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on January 12, 2013, 07:11:50 PM
BitSyncom,

It is very important for me to sort out the invoicing in advance before shipment happens. I mailed you twice and opened a ticket and still no response. Please reply me when you can.

10X
Best


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: thorvald on January 12, 2013, 10:31:17 PM
BitSyncom,

It is very important for me to sort out the invoicing in advance before shipment happens. I mailed you twice and opened a ticket and still no response. Please reply me when you can.

10X
Best

Maybe the Billing Agreements can be used for this in the account   .
I`m checking every day for the news/response/tiket.

Regards
Thorvald



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Dhomochevsky on January 13, 2013, 02:22:41 PM
The address we should send questions (and shipping detail confirmations) to is "info[at]avalon-asic.com" , is that right?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: server on January 13, 2013, 03:26:53 PM
If it is not marked as an engineering sample or demo, you can have great problems on custom because of the missing CE mark!
Or i'm wrong?
there have been a few people in EU that have still bought FPGA's from this company. How have these done this? Perhaps they should share their experiences with this deals (shipping, custom, invoice etc.)...

I'm from Europe and I ordered several times boards from NGZ. I never experienced any problems.
The first time (https://bitcointalk.org/index.php?topic=51371.msg655146#msg655146) I received the package after 9 days.
The second and third time it was 20 days.

I trust NGZ and I think he knows what's best when it comes to shipping his products to the different parts of the world.

So for what it's worth.. only the best experiences on my part. :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: loshia on January 13, 2013, 03:35:11 PM

I'm from Europe and I ordered several times boards from NGZ. I never experienced any problems.
The first time (https://bitcointalk.org/index.php?topic=51371.msg655146#msg655146) I received the package after 9 days.
The second and third time it was 20 days.

I trust NGZ and I think he knows what's best when it comes to shipping his products to the different parts of the world.

So for what it's worth.. only the best experiences on my part. :)

+1
I am very happy with NGZ as well. But this time he will not be involved in shipping invoices and so on....
BitSyncom will take care of that and he is our contact person.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ngzhang on January 13, 2013, 03:41:54 PM

I'm from Europe and I ordered several times boards from NGZ. I never experienced any problems.
The first time (https://bitcointalk.org/index.php?topic=51371.msg655146#msg655146) I received the package after 9 days.
The second and third time it was 20 days.

I trust NGZ and I think he knows what's best when it comes to shipping his products to the different parts of the world.

So for what it's worth.. only the best experiences on my part. :)

+1
I am very happy with NGZ as well. But this time he will not be involved in shipping invoices and so on....
BitSyncom will take care of that and he is our contact person.


we discuss the whole process and working together. actually, i will use my previous experience for this project.

PS: everything is on schedule now, our target is to be the first.  ;D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: ewibit on January 13, 2013, 04:19:30 PM
I received the package after 9 days.
The second and third time it was 20 days.
why ist there so much different in shipping time (and why does it take so long time (20 days)?)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: server on January 13, 2013, 04:27:18 PM
I received the package after 9 days.
The second and third time it was 20 days.
why ist there so much different in shipping time (and why does it take so long time (20 days)?)

I really don't why. Most of the items I order from China take 20+ days, so the first time was a real surprise.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 13, 2013, 04:49:04 PM
I received the package after 9 days.
The second and third time it was 20 days.
why ist there so much different in shipping time (and why does it take so long time (20 days)?)

Regular First Class International Mail can vary a lot like that.  I think sometimes they wait for the pile of mail to get big enough before they send a batch over, so your mailpiece may arrive just as the pile gets full enough to be sent, or when it's still mostly empty and needs to wait.

The Avalons will all be dispatched by DHL Express (or EMS if the customer chooses), both of which should be consistently much faster than First Class Intl Mail.

If mine ships out by DHL on Monday the 21st, I expect I will have it in my hands here in the US on or before Friday the 25th.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 13, 2013, 09:07:36 PM
PS: everything is on schedule now, our target is to be the first.  ;D

No demo? ):


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Grix on January 13, 2013, 09:11:09 PM
When will the second batch be available? And will the price be the same?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Icoin on January 13, 2013, 11:02:14 PM
Quote
we discuss the whole process and working together. actually, i will use my previous experience for this project.

PS: everything is on schedule now, our target is to be the first.  Grin

I have full trust in NGZ the cooperation with him and the devices was allways 1+ so the GMP project looks forward for the tradein.

It would be great to have the dimensions and type of the coolingmount since 400W will produce a lot of heat ;)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MeSarah on January 13, 2013, 11:32:32 PM
PS: everything is on schedule now, our target is to be the first.  ;D

I am not the first to raise this question but I still would like to ask it. I checked www.avalon-asics.com to see what the 'count down clock' said. At the time I checked it was a little over 6 days. So lets look a little closer. If we have 1 day for assembly, how long will it be in transit from the assemblers to the Avalon shipping facilities? If the assemblers are close then they could pick up the assembled product. Otherwise it will take 1 to 3 days, maybe longer, to ship to Avalon for final assembly and shipment to the customer. Now how long will the product burn in be, 24 hours?

So that leaves virtually no time for quality control testing not to mention SRRC certification but Chinese companies don't seam to comply with their own countries laws when shipping outside their boarders. It appears to me that the Avalon development team is relaying solely on computer simulations of their product to be 100% accurate. Computer simulations are never wrong, right? With only days to do full quality control testing of the hardware and software purchasers of Avalon's products can expect a high failure rate and a large warranty return rate. Not to mention long shipping delays from country to country and lack of replacement parts to fix warranty issues. At which time you will not be eligible for a refund and stuck with an inferior product. But what can I say, China is home to the inferior product.

http://www.youtube.com/watch?v=94HTIueOuDQ

On Avalon's website they claim to have 10+ years ASIC experience. It's now time for Avalon to tell their customers and the community which Avalon employees have ASIC experience and how much each Avalon employee is claimed to have. But I suspect that full disclosure of claims made on their website will be an issue that will be avoided. I surmise they will claim that a Master's Degree is equivalent to 6 years experience. Or maybe if it takes someone 10 years to complete a 6 year program that could be counter as 10 years experience. Can one really claim taking a university class as experience? Not in my book and not on a job application. Could it be that someone is drinking their own Jonestown Kool Aid?

With less than a week to the proclaimed shipment date there is no reason not to show pictures of a PCB or chassis as Avalon's only competitor has done. Unless they don't have a PCB or chassis to show, which is entirely plausible.

Too bad that China's target is to be first (inferiority complex?), rather than America's where quality is job 1.

Now queuing 300 test dummies.


Edit below made by anonymous admin: note other edits might have been made by cowardly anonymous admins;
Now queuing 300 test dummies, a sacrifice to appease the gods I've angered by continuing to troll this thread... maybe they won't edit the hell out of this post as they promised to do (https://bitcointalk.org/index.php?topic=134952.0).


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: fcmatt on January 14, 2013, 12:14:22 AM
All this talk of shipping. When are we going to see a simple pic of a board with asic chips actually mining?



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: libertybuck on January 14, 2013, 12:52:32 AM
If we have 1 day for assembly, how long will it be in transit from the assemblers to the Avalon shipping facilities? If the assemblers are close then they could pick up the assembled product. 

They are located in BeiJing China. Arrange shipment is not difficult.


With less than a week to the proclaimed shipment date there is no reason not to show pictures of a PCB or chassis as Avalon's only competitor has done. Unless they don't have a PCB or chassis to show, which is entirely plausible.

I think some of your questions are reasonable.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 14, 2013, 12:59:15 AM
With less than a week to the proclaimed shipment date there is no reason not to show pictures of a PCB or chassis as Avalon's only competitor has done. Unless they don't have a PCB or chassis to show, which is entirely plausible.

I think some of your questions are reasonable.
[/quote]

With less than a week left, we'll find out soon enough no matter what.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 14, 2013, 01:05:32 AM
All this talk of shipping. When are we going to see a simple pic of a board with asic chips actually mining?

An image (or vid) of a box (or pcb) along with a display showing some numbers is not something which would impress _me_ a whole lot.

What would it take to make the suggested exercise be impressive to you?  Or have you put much thought into it?



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 14, 2013, 01:12:21 AM
All this talk of shipping. When are we going to see a simple pic of a board with asic chips actually mining?

An image (or vid) of a box (or pcb) along with a display showing some numbers is not something which would impress _me_ a whole lot.

What would it take to make the suggested exercise be impressive to you?  Or have you put much thought into it?



There's really no reason for them to do this now.  They're not accepting any new orders for a while, and it's not like they have a credibility problem and need to post something to stop a wave of cancellations.

Personally, I want to be the first to post pics and vid of one, when I receive mine.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 14, 2013, 02:40:10 AM
All this talk of shipping. When are we going to see a simple pic of a board with asic chips actually mining?
An image (or vid) of a box (or pcb) along with a display showing some numbers is not something which would impress _me_ a whole lot.

What would it take to make the suggested exercise be impressive to you?  Or have you put much thought into it?
There's really no reason for them to do this now.  They're not accepting any new orders for a while, and it's not like they have a credibility problem and need to post something to stop a wave of cancellations.

Personally, I want to be the first to post pics and vid of one, when I receive mine.

There is not much reason for them not to do it either.

But anyway, my point is that it would take a barely competent script monkey about 5 minutes to hack out a mock which would display anything they choose.

A better solution would be to publish a set of nonces shortly after a new piece of data came into existence.  Even here, though, someone who was intent on conning people could hook up a collection of lesser gear to work on the problem and pretend that it was their new little ASIC which had produced the results.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 420 on January 14, 2013, 03:14:07 AM
As other's have probably said, if they're just working on theory i.e. never had a working prototype, they won't have a demo model until 24hrs before they're going to ship some

if, which is what they should have done, is run a prototype model of one

of course they should do this and then have much testing etc. before mass producing so maybe up to a week minimum before shipping a batch they should have a working product; why not show it off?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 14, 2013, 03:47:46 AM
As other's have probably said, if they're just working on theory i.e. never had a working prototype, they won't have a demo model until 24hrs before they're going to ship some

if, which is what they should have done, is run a prototype model of one

of course they should do this and then have much testing etc. before mass producing so maybe up to a week minimum before shipping a batch they should have a working product; why not show it off?

Perhaps because, as I mentioned above, it would show nothing.  It would, in fact, be mainly a waste of time and Avalon may not have a compelling interest in impressing the segment of the community who would be be impressed by such a feat.

Again though, it would not be big effort or waste much time, so why not?  An ominous reason could be that it would be admissible,  incontrovertible, and documented evidence that they were running a scam if that happens to be the case.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cedivad on January 14, 2013, 05:45:52 AM
As other's have probably said, if they're just working on theory i.e. never had a working prototype, they won't have a demo model until 24hrs before they're going to ship some

if, which is what they should have done, is run a prototype model of one

of course they should do this and then have much testing etc. before mass producing so maybe up to a week minimum before shipping a batch they should have a working product; why not show it off?

Perhaps because, as I mentioned above, it would show nothing.  It would, in fact, be mainly a waste of time and Avalon may not have a compelling interest in impressing the segment of the community who would be be impressed by such a feat.

Again though, it would not be big effort or waste much time, so why not?  An ominous reason could be that it would be admissible,  incontrovertible, and documented evidence that they were running a scam if that happens to be the case.



You are right, it takes 5 minutes to take a reflex plugin the sd card and upload the pictures.
2 minutes using an iPhone.

That's a lot of time to waste.

I will buy BFL. Do someone want to bet against me that Avalon will not ship on time? 100BTC ready here.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 14, 2013, 06:09:08 AM

You are right, it takes 5 minutes to take a reflex plugin the sd card and upload the pictures.
2 minutes using an iPhone.

That's a lot of time to waste.

I will buy BFL. Do someone want to bet against me that Avalon will not ship on time? 100BTC ready here.

Huh.  Another BFL groupie who is impressed by some picture of numbers on a display.  Who'd have imagined?

You may give Sonny and Josh some of your money but I am less confident that you will actually buy anything in the common sense of the term.  Maybe a sore a-hole.

As for betting about Avalon, why should I?  I've no idea whether they even have an ASIC much less whether they will ship it on time.  They do seem vastly more credible to me than did bASIC and do BFL.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: anti76 on January 14, 2013, 06:15:38 AM

I used to send scanned documents to pay warrants 200,000,846.
Status of the order has not changed, the letters from the scans or who did not reply, sent to the address: info@avalon-asic.com, yifu.guo @ avalon-asic.com

Order #    Date    Ship To    Order Total    Status    
200000846    11/24/12    ---------   $8,159.94    Pending Wire    View Order


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on January 14, 2013, 06:22:38 AM

I used to send scanned documents to pay warrants 200,000,846.
Status of the order has not changed, the letters from the scans or who did not reply, sent to the address: info@avalon-asic.com, yifu.guo @ avalon-asic.com

Order #    Date    Ship To    Order Total    Status    
200000846    11/24/12    ---------   $8,159.94    Pending Wire    View Order

The wire came in on the 11th of this month, a month plus late... I'm aware of this order, but due to it's nature being two wire transfers it did not complete automatically. This matter will be addressed.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: anti76 on January 14, 2013, 06:44:13 AM

I used to send scanned documents to pay warrants 200,000,846.
Status of the order has not changed, the letters from the scans or who did not reply, sent to the address: info@avalon-asic.com, yifu.guo @ avalon-asic.com

Order #    Date    Ship To    Order Total    Status    
200000846    11/24/12    ---------   $8,159.94    Pending Wire    View Order

The wire came in on the 11th of this month, a month plus late... I'm aware of this order, but due to it's nature being two wire transfers it did not complete automatically. This matter will be addressed.
that is, now it will be paid to the status?
and on what email send letters to meet me?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 14, 2013, 10:14:32 AM

I used to send scanned documents to pay warrants 200,000,846.
Status of the order has not changed, the letters from the scans or who did not reply, sent to the address: info@avalon-asic.com, yifu.guo @ avalon-asic.com

Order #    Date    Ship To    Order Total    Status    
200000846    11/24/12    ---------   $8,159.94    Pending Wire    View Order

The wire came in on the 11th of this month, a month plus late... I'm aware of this order, but due to it's nature being two wire transfers it did not complete automatically. This matter will be addressed.
@ Yifu

Could you add --> info@avalon-asic.com, yifu.guo @ avalon-asic.com <--- these contact addresses to your signature?

It would make it easier to know who and how to contact.

-----------------------

Second, I know you aren't going to look at a gift horse in the mouth. But why is this guys wire so damn late? This month it was recieved?

Are you sure he didn't make a "ghost order" and then paid for it after all the ASIC drama was said and done? I thought there was a definite time limit to wire transfers being accepted?

You should look into this issue as there are probably folks right now who are going to send in wire transfers this late and claim order numbers which they never actually intended to pay for before the deadline in early October 2012.

If you don't look into it you might find out you'll get more than 300 orders to fulfill.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 14, 2013, 10:20:43 AM
I also noticed in my order 200000504:

That my address was doubled in the registration. I corrected it in my account settings but do not know if you guys will process them from the website or some kind of paper work that was generated a while back. Please check on this and let me know if the address line isn't doubled in the paperwork for shipping.

Good luck on being the first to release!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Kumala on January 14, 2013, 03:31:20 PM
from where are you shipping? Beijing? Can I come and pick them up?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Spekulatius on January 14, 2013, 03:51:26 PM
Since they are both "official", which date is right?

Your OP in this thread:

While the competition promised early delivery dates but kept pushing them back. Avalon instead gave an very conservative estimate but now is scheduled to ship even earlier at Jan. 14th 2013.

Or your count down on http://www.avalon-asics.com/?  (Monday, 21st of January 2013)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on January 14, 2013, 03:52:58 PM
Huh... 14th, then the 19th, now it's the 21st? 

Interesting...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: DutchBrat on January 14, 2013, 03:54:40 PM
Huh... 14th, then the 19th, now it's the 21st? 

Interesting...

Sounds a lot like October, then November, then December, then January, now it's February.... yet it is so different in soooooo many ways  ;)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on January 14, 2013, 04:02:07 PM
You're right... they haven't provided any evidence they have a product other than some documentation.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Syke on January 14, 2013, 04:04:47 PM
Huh... 14th, then the 19th, now it's the 21st? 

Interesting...

Nice trolling.

Avalon facts are this:

http://forum.bitsyn.com/viewtopic.php?id=5

Quote
Shipping will start from February 2013 following the order sequence.

Their initial shipping date was February. The fact that they are slipping on their early delivery is nothing like BFL:

October missed
November missed
December missed
January missed
February still to be missed


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Spekulatius on January 14, 2013, 04:11:04 PM
This is crazy! How is one supposed to keep oversight with that many "official" dates?

Clean up Avalon, because It's a mess!™


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: DutchBrat on January 14, 2013, 04:12:35 PM
You're right... they haven't provided any evidence they have a product other than some documentation.


Also sounds very familiar....

In the end I hope most vendors make good on their promises ! Better for Bitcoin !


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: RoboCoder on January 14, 2013, 04:24:53 PM

Nice trolling.

Avalon facts are this:

http://forum.bitsyn.com/viewtopic.php?id=5


Quote
SCHEDULE:

Sample Batch ( about 10 units ) at the end of December, 2012
- video demonstration of final product in operation can be seen at this time.

Did they ever provide the video in december that is mentioned on the bitsyn forum? If that was missed i would think that would be significant..  especially to those with large investments into the preorders.. 


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on January 14, 2013, 04:35:30 PM
Since they are both "official", which date is right?

Your OP in this thread:

While the competition promised early delivery dates but kept pushing them back. Avalon instead gave an very conservative estimate but now is scheduled to ship even earlier at Jan. 14th 2013.

Or your count down on http://www.avalon-asics.com/?  (Monday, 21st of January 2013)

You didn't finish reading, the second post on the front page as more information...

It has now been fixed. a small oversight. Unlike somebody, the difference in shipping date is only a few days and not a few months.

It has been changed to 18-20th, the countdown timer ends on 12:00:00am 21th.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: rudrigorc2 on January 14, 2013, 04:39:04 PM
anything to say about the DEMO? are they mining right now? :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: server on January 14, 2013, 04:44:02 PM
Ah forgive Josh, he is just frustrated about the empty case at the 2013 CES... ;)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 14, 2013, 04:45:04 PM
anything to say about the DEMO? are they mining right now? :)

yes, the hash rate is growing constantly since yesterday.  ::)

http://blockchain.info/charts/hash-rate?timespan=30days&showDataPoints=false&daysAverageString=1&show_header=true&scale=0&address= (http://blockchain.info/charts/hash-rate?timespan=30days&showDataPoints=false&daysAverageString=1&show_header=true&scale=0&address=)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cedivad on January 14, 2013, 04:51:01 PM
anything to say about the DEMO? are they mining right now? :)

yes, the hash rate is growing constantly since yesterday.  ::)

http://blockchain.info/charts/hash-rate?timespan=30days&showDataPoints=false&daysAverageString=1&show_header=true&scale=0&address= (http://blockchain.info/charts/hash-rate?timespan=30days&showDataPoints=false&daysAverageString=1&show_header=true&scale=0&address=)
Good trolling.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bitmar on January 14, 2013, 05:02:06 PM
You're right... they haven't provided any evidence they have a product other than some documentation.


hypocrite ;)
... but he's right. A few days to ship and there is no demo? LOL  ;D
The Bitcoin world never ceases to amaze me ;)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: rudrigorc2 on January 14, 2013, 05:07:05 PM
You're right... they haven't provided any evidence they have a product other than some documentation.


hypocrite ;)
... but he's right. A few days to ship and there is no demo? LOL  ;D
The Bitcoin world never ceases to amaze me ;)


maybe its really a tight schedule. the clock is ticking and there`s no demo but besides this we have no other reason to doubt.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: beekeeper on January 14, 2013, 05:20:27 PM
anything to say about the DEMO? are they mining right now? :)

yes, the hash rate is growing constantly since yesterday.  ::)

http://blockchain.info/charts/hash-rate?timespan=30days&showDataPoints=false&daysAverageString=1&show_header=true&scale=0&address= (http://blockchain.info/charts/hash-rate?timespan=30days&showDataPoints=false&daysAverageString=1&show_header=true&scale=0&address=)

Dude, you can't use one day sample as measurement unless someone deploys 100 THs over night.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 14, 2013, 05:21:57 PM
anything to say about the DEMO? are they mining right now? :)

yes, the hash rate is growing constantly since yesterday.  ::)

http://blockchain.info/charts/hash-rate?timespan=30days&showDataPoints=false&daysAverageString=1&show_header=true&scale=0&address= (http://blockchain.info/charts/hash-rate?timespan=30days&showDataPoints=false&daysAverageString=1&show_header=true&scale=0&address=)

Dude, you can't use one day sample as measurement unless someone deploys 100 THs over night.

calm down it was ironic!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: beekeeper on January 14, 2013, 06:02:39 PM
I'm quite calm, but informative.  ;D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 14, 2013, 06:06:44 PM
anything to say about the DEMO? are they mining right now? :)

yes, the hash rate is growing constantly since yesterday.  ::)

http://blockchain.info/charts/hash-rate?timespan=30days&showDataPoints=false&daysAverageString=1&show_header=true&scale=0&address= (http://blockchain.info/charts/hash-rate?timespan=30days&showDataPoints=false&daysAverageString=1&show_header=true&scale=0&address=)
Good trolling.

I expect a hash rate of 40,000+ GH/s next month.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: yrral on January 14, 2013, 06:57:03 PM
@Bitsyncom/ngzhang
What kind of package are your chips using?
https://forums.butterflylabs.com/content/129-13-jan-13-asic-update.html


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Syke on January 14, 2013, 07:14:36 PM
@Bitsyncom/ngzhang
What kind of package are your chips using?
https://forums.butterflylabs.com/content/129-13-jan-13-asic-update.html

Did you read the first post?

https://bitcointalk.org/index.php?topic=120184.msg1294416#msg1294416


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: SgtSpike on January 14, 2013, 07:17:47 PM
@Bitsyncom/ngzhang
What kind of package are your chips using?
https://forums.butterflylabs.com/content/129-13-jan-13-asic-update.html
OP says QFN.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mobodick on January 14, 2013, 07:40:49 PM
Huh... 14th, then the 19th, now it's the 21st? 

Interesting...

You get very little irony in your diet, true...?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Inaba on January 14, 2013, 08:04:49 PM
Huh... 14th, then the 19th, now it's the 21st? 

Interesting...

You get very little irony in your diet, true...?


It's not irony when I'm pointing out that they are doing the exact same thing they have been vilifying us for.  So, yeah, I guess it's irony, but not on my part.

BitSyncom: We are shipping on the 14th! BFL you keep pushing your date back, it is dishonest to push your date back!
BitSyncom: We are shipping on the 19th! BFL you keep pushing your date back, you suck because you keep missing your date!
BitSyncom: We are shipping on the 21st! BFL you keep pushing your date back, we've only pushed it back two days!

I guess we'll see in another 7 days.  Irony indeed.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Syke on January 14, 2013, 08:07:46 PM
It's not irony when I'm pointing out that they are doing the exact same thing they have been vilifying us for.  So, yeah, I guess it's irony, but not on my part.

BitSyncom: We are shipping on the 14th! BFL you keep pushing your date back, it is dishonest to push your date back!
BitSyncom: We are shipping on the 19th! BFL you keep pushing your date back, you suck because you keep missing your date!
BitSyncom: We are shipping on the 21st! BFL you keep pushing your date back, we've only pushed it back two days!

I guess we'll see in another 7 days.  Irony indeed.


When Avalon is 4 months past their initial delivery date (Feb '13), then you can say that. Until then, shut up.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on January 14, 2013, 08:11:01 PM
Does the countdown not agree with their original delay?
Updating as promised,

Let's be frank. We ran into a potential delay of 4-7 days.

What does this mean?

We when taped out the chips to TSMC we had a "projected out date" of Jan 3, 2013 which is on schedule with our late dec. / early jan. demonstration dates. Now however after this week's website update our "projected out date" has changed to Jan 7th, 2013 and "committed date" has been revealed to be Jan 10th, 2013. TSMC did not give us a reason for this, but as a small customer you are really at the mercy of bigger customers running higher priority lots. e.g. "super hot lot"  The "committed date" is the promised date of delivery, it is very unusual for TSMC to break their "committed date", so we expect our chips to ship on or before Jan 10th, 2013.

Another potential problem is Customs clearing, the packaging company Fujitsu is located in Shanghai's Export Processing Zone (EPZ), while the packaging itself will not see delays, it may take an additional 2-3 days to clear Customs. To make up for this, if it occurs, we will be flying down to Shanghai to the demonstration in the EPZ instead of waiting for the shipping to the factory for assembly.

With all this happening, it has burned through the 1 week additional leeway time we originally left out. I must say it will be difficulty for us to ship on Jan 14th, we however expect to ship around Jan 18 ~ 20.


The clock looks to be hitting 00:00 at 7am on the 20th in my time zone (CST)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Starlightbreaker on January 14, 2013, 08:15:30 PM
Huh... 14th, then the 19th, now it's the 21st? 

Interesting...

You get very little irony in your diet, true...?


It's not irony when I'm pointing out that they are doing the exact same thing they have been vilifying us for.  So, yeah, I guess it's irony, but not on my part.

BitSyncom: We are shipping on the 14th! BFL you keep pushing your date back, it is dishonest to push your date back!
BitSyncom: We are shipping on the 19th! BFL you keep pushing your date back, you suck because you keep missing your date!
BitSyncom: We are shipping on the 21st! BFL you keep pushing your date back, we've only pushed it back two days!

I guess we'll see in another 7 days.  Irony indeed.

unless you're as stupid as the shit you spew out your mouth fingers..
i think there's a difference between missing a couple of days and a couple of months, time-wise.

hell, they even haven't passed the delivery date.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mobodick on January 14, 2013, 08:30:38 PM
Huh... 14th, then the 19th, now it's the 21st? 

Interesting...

You get very little irony in your diet, true...?


It's not irony when I'm pointing out that they are doing the exact same thing they have been vilifying us for.  So, yeah, I guess it's irony, but not on my part.

BitSyncom: We are shipping on the 14th! BFL you keep pushing your date back, it is dishonest to push your date back!
BitSyncom: We are shipping on the 19th! BFL you keep pushing your date back, you suck because you keep missing your date!
BitSyncom: We are shipping on the 21st! BFL you keep pushing your date back, we've only pushed it back two days!

I guess we'll see in another 7 days.  Irony indeed.


That is not the ironic fact i was refering to tho.
There is a difference between a few days and a few months as you may know.
The irony in this case is that you do way way worse then the people you are so eager to accuse.
And they at least have the decency to inform their customers/investors beforehand and not a few days after the fact.

(This is of course completely besides the point that there is also irony in avalon getting delayed.)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cedivad on January 14, 2013, 08:34:51 PM
Come on guys, let's stop trolling.

We will see in a matter of days, i have mine "20 of January speculation deadline" and than this. It's gonna be a funny time.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Carlton Banks on January 14, 2013, 10:08:17 PM
Huh... 14th, then the 19th, now it's the 21st? 

Interesting...

You get very little irony in your diet, true...?


It's not irony when I'm pointing out that they are doing the exact same thing they have been vilifying us for.  So, yeah, I guess it's irony, but not on my part.

BitSyncom: We are shipping on the 14th! BFL you keep pushing your date back, it is dishonest to push your date back!
BitSyncom: We are shipping on the 19th! BFL you keep pushing your date back, you suck because you keep missing your date!
BitSyncom: We are shipping on the 21st! BFL you keep pushing your date back, we've only pushed it back two days!

I guess we'll see in another 7 days.  Irony indeed.


That is not the ironic fact i was refering to tho.
There is a difference between a few days and a few months as you may know.
The irony in this case is that you do way way worse then the people you are so eager to accuse.
And they at least have the decency to inform their customers/investors beforehand and not a few days after the fact.

(This is of course completely besides the point that there is also irony in avalon getting delayed.)

The most ironic thing of all is that no-one understands his tactics. He already knew before he penned his troll-post that his company is more incompetent and deceitful when it comes to their delivery schedule, that was the bait. Which you took.  If he could patent this trolling manoeuvre (which is actually as old as the beginning of time), he'd have earned alot of royalties using it on this forum, as it's one of the few trolling techniques he has he uses posting from his own account.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: libertybuck on January 14, 2013, 10:28:31 PM
How to describe everyone's feeling ?

eagerly ......   ;D
anxious ......   :o
tired ......       :'(
doubt ......     ???


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Spekulatius on January 14, 2013, 10:42:13 PM
 :o


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: smoothie on January 14, 2013, 10:56:00 PM
It's not irony when I'm pointing out that they are doing the exact same thing they have been vilifying us for.  So, yeah, I guess it's irony, but not on my part.

BitSyncom: We are shipping on the 14th! BFL you keep pushing your date back, it is dishonest to push your date back!
BitSyncom: We are shipping on the 19th! BFL you keep pushing your date back, you suck because you keep missing your date!
BitSyncom: We are shipping on the 21st! BFL you keep pushing your date back, we've only pushed it back two days!

I guess we'll see in another 7 days.  Irony indeed.


When Avalon is 4 months past their initial delivery date (Feb '13), then you can say that. Until then, shut up.

Yeah josh STFU  :D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mobodick on January 14, 2013, 11:18:36 PM
Huh... 14th, then the 19th, now it's the 21st? 

Interesting...

You get very little irony in your diet, true...?


It's not irony when I'm pointing out that they are doing the exact same thing they have been vilifying us for.  So, yeah, I guess it's irony, but not on my part.

BitSyncom: We are shipping on the 14th! BFL you keep pushing your date back, it is dishonest to push your date back!
BitSyncom: We are shipping on the 19th! BFL you keep pushing your date back, you suck because you keep missing your date!
BitSyncom: We are shipping on the 21st! BFL you keep pushing your date back, we've only pushed it back two days!

I guess we'll see in another 7 days.  Irony indeed.


That is not the ironic fact i was refering to tho.
There is a difference between a few days and a few months as you may know.
The irony in this case is that you do way way worse then the people you are so eager to accuse.
And they at least have the decency to inform their customers/investors beforehand and not a few days after the fact.

(This is of course completely besides the point that there is also irony in avalon getting delayed.)

The most ironic thing of all is that no-one understands his tactics. He already knew before he penned his troll-post that his company is more incompetent and deceitful when it comes to their delivery schedule, that was the bait. Which you took.  If he could patent this trolling manoeuvre (which is actually as old as the beginning of time), he'd have earned alot of royalties using it on this forum, as it's one of the few trolling techniques he has he uses posting from his own account.
..DAMMIT!...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Carlton Banks on January 14, 2013, 11:32:15 PM
Huh... 14th, then the 19th, now it's the 21st? 

Interesting...

You get very little irony in your diet, true...?


It's not irony when I'm pointing out that they are doing the exact same thing they have been vilifying us for.  So, yeah, I guess it's irony, but not on my part.

BitSyncom: We are shipping on the 14th! BFL you keep pushing your date back, it is dishonest to push your date back!
BitSyncom: We are shipping on the 19th! BFL you keep pushing your date back, you suck because you keep missing your date!
BitSyncom: We are shipping on the 21st! BFL you keep pushing your date back, we've only pushed it back two days!

I guess we'll see in another 7 days.  Irony indeed.


That is not the ironic fact i was refering to tho.
There is a difference between a few days and a few months as you may know.
The irony in this case is that you do way way worse then the people you are so eager to accuse.
And they at least have the decency to inform their customers/investors beforehand and not a few days after the fact.

(This is of course completely besides the point that there is also irony in avalon getting delayed.)

The most ironic thing of all is that no-one understands his tactics. He already knew before he penned his troll-post that his company is more incompetent and deceitful when it comes to their delivery schedule, that was the bait. Which you took.  If he could patent this trolling manoeuvre (which is actually as old as the beginning of time), he'd have earned alot of royalties using it on this forum, as it's one of the few trolling techniques he has he uses posting from his own account.
..DAMMIT!...


...Josh? Is that you in there? You've not taken to trolling your own troll accounts to keep the "debate" moving, surely? Things will improve you know, you might even get ASICs before the end of next month (just be sure you're first in line on that 2nd batch of Avalons!)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 15, 2013, 09:32:33 AM
...Josh? Is that you in there? You've not taken to trolling your own troll accounts to keep the "debate" moving, surely? Things will improve you know, you might even get ASICs before the end of next month (just be sure you're first in line on that 2nd batch of Avalons!)

Oh no! You've discovered my secret!

I mean his.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: lucif on January 15, 2013, 09:38:24 AM
I am glad Avalon helping me to dance on Josh bones.

But I should warn all of you about Avalon itself.

No demo, no tests, no bitcoin hashrate increase so far. Only pics with unnamed chips. And 5 days to delivery.

Lets see, lets see...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 15, 2013, 09:42:53 AM
No demo

Yeah, they still haven't given a solid answer on this (unless I missed it?). It's a bit odd.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: lucif on January 15, 2013, 09:45:18 AM
Very interesting what is estimated summary pre-orders amount in Avalon...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 15, 2013, 10:06:53 AM
Very interesting what is estimated summary pre-orders amount in Avalon...

300 pre-orders in first batch.

300 x 60 GH/s = 18,000 GH/s

increase of hashrate by 18,000 GH/s until next month.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: lucif on January 15, 2013, 10:12:12 AM
So, $400k.

Not enough, not enough... Okay lets see.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 15, 2013, 10:45:52 AM
So, $400k.

Not enough, not enough... Okay lets see.

right, $400k.

300 x $1,299.99 = $389,997.00

not enough for ASIC production but maybe they have own or foreign capital involved.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: aTg on January 15, 2013, 10:51:43 AM
So, $400k.

Not enough, not enough... Okay lets see.

right, $400k.

300 x $1,299.99 = $389,997.00

not enough for ASIC production but maybe they have own or foreign capital involved.

 A structured ASIC costs 300k €


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 15, 2013, 10:58:15 AM
So, $400k.

Not enough, not enough... Okay lets see.

right, $400k.

300 x $1,299.99 = $389,997.00

not enough for ASIC production but maybe they have own or foreign capital involved.

 A structured ASIC costs 300k €

this is exact the pre-orders amount.

€300k x 1.30 = $390k


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: anti76 on January 15, 2013, 12:26:08 PM

I used to send scanned documents to pay warrants 200,000,846.
Status of the order has not changed, the letters from the scans or who did not reply, sent to the address: info@avalon-asic.com, yifu.guo @ avalon-asic.com

Order #    Date    Ship To    Order Total    Status    
200000846    11/24/12    ---------   $8,159.94    Pending Wire    View Order

The wire came in on the 11th of this month, a month plus late... I'm aware of this order, but due to it's nature being two wire transfers it did not complete automatically. This matter will be addressed.

until now the status has not changed.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on January 15, 2013, 07:45:01 PM
Very interesting what is estimated summary pre-orders amount in Avalon...

300 pre-orders in first batch.

300 x 60 GH/s = 18,000 GH/s

increase of hashrate by 18,000 GH/s until next month.
It's 66GH/s now, is it not?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 420 on January 15, 2013, 07:54:47 PM
Very interesting what is estimated summary pre-orders amount in Avalon...

300 pre-orders in first batch.

300 x 60 GH/s = 18,000 GH/s

increase of hashrate by 18,000 GH/s until next month.
It's 66GH/s now, is it not?

ASIC Bitcoin Miner
Done right
~60GH/s starting at $1,299. Avalon, a world first, coming to your doorsteps Q1 of 2013.

4
DAYS
17
HOUR


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on January 15, 2013, 08:00:12 PM
From the original post of this thread.
Intro. Avalon launched with a challenge to our competitors: a over 50% dollar per GHash gain. Our competitors since then has also increased their specifications in order to stay competitive. Deviated from their original plan the competition managed to even the playing field, yet we simply proceeded with our original design goals and have reached 64Gh/s, and now 66Gh/s! Once again taking the lead in $/Ghash. While the competition promised early delivery dates but kept pushing them back. Avalon instead gave an very conservative estimate but now is scheduled to ship even earlier at Jan. 20th 2013.
...
$1,299? Yep, to stay with the spirit of the competition. $1,299 for 66Gh/s.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 15, 2013, 08:08:04 PM

I have a suggestion for future 'pre-order' funds management.

This suggestion only works of the vendor does not need to use the funds prior to shipping for operating expenses (and if they do, I would argue that pre-orders and are inappropriate source of funding anyway.)

I suggest that an entity who wishes to queue up in the delivery line simply transfers a particular value to an address that _they_ retain control of.  The address list would be public domain.  When their turn comes up in the queue, they can optionally take delivery.  If at some point prior to delivery they wish to de-queue, they just transfer the funds back out.

Any terms involving exchage rate adjustments (and the like) could be drawn up.  As long as it's clear that the vendor had an option to capitalize on favorable exchange rate moves up front, I'd be totally fine with that.  To clarify:

 - if the BTC values go up, the original outlay is taken
 - if the BTC values go down, additional funds are needed to exercise delivery.

In vendor-favorable scheme like the above example, the customer may still choose to take delivery or not.  If not, the next guy in the queue gets the option.

Lots of permutations are possible.  It is the case that people with excess funds could queue up as a speculative move planning to potentially sell their spots (which is why I used a vendor-favorable example above.)  At the end of the day, though, who cares?  Accounting and management of funds should be trivial and mechanical.  Most importantly, it should leave the customer in control.  Bitcoin offers some pretty unique opportunities because of it's transparency and it would be cool to seem them leveraged by vendors in efforts to demonstrate good intentions.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 15, 2013, 08:53:50 PM
any sign from Avalon? if they will start to ship next monday they should start to assembly and test the units.

countdown: avalon-asics.com (http://avalon-asics.com/)

http://i50.tinypic.com/b87d45.png


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: SolarSilver on January 15, 2013, 10:52:40 PM
A structured ASIC costs 300k €

this is exact the pre-orders amount.

€300k x 1.30 = $390k
and producing 300 units with a PCB, CPU, ethernet, case and power supply is free?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: julz on January 15, 2013, 11:07:49 PM

I have a suggestion for future 'pre-order' funds management.

This suggestion only works of the vendor does not need to use the funds prior to shipping for operating expenses (and if they do, I would argue that pre-orders and are inappropriate source of funding anyway.)

I suggest that an entity who wishes to queue up in the delivery line simply transfers a particular value to an address that _they_ retain control of.  The address list would be public domain.  When their turn comes up in the queue, they can optionally take delivery.  If at some point prior to delivery they wish to de-queue, they just transfer the funds back out.

Any terms involving exchage rate adjustments (and the like) could be drawn up.  As long as it's clear that the vendor had an option to capitalize on favorable exchange rate moves up front, I'd be totally fine with that.  To clarify:

 - if the BTC values go up, the original outlay is taken
 - if the BTC values go down, additional funds are needed to exercise delivery.

In vendor-favorable scheme like the above example, the customer may still choose to take delivery or not.  If not, the next guy in the queue gets the option.

Lots of permutations are possible.  It is the case that people with excess funds could queue up as a speculative move planning to potentially sell their spots (which is why I used a vendor-favorable example above.)  At the end of the day, though, who cares?  Accounting and management of funds should be trivial and mechanical.  Most importantly, it should leave the customer in control.  Bitcoin offers some pretty unique opportunities because of it's transparency and it would be cool to seem them leveraged by vendors in efforts to demonstrate good intentions.


I really love this idea.
Presumably people would prove they own the address, and agree to the particular terms by signing those terms using a Bitcoin 'sign message' facility.

More generally - this seems like a form of 'layaway' (or lay-by as it's known here in Australia)

I'd like to see a little lay-by management tool for merchants & customers to view their agreement terms and balances.
..but how could we prevent someone using the same funds as part of deals with multiple merchants where the amounts happen to match?
(some people may just reserve way more resources than they are ever going to be able to pay - negatively affecting the utility of the system for merchants)
I like the simplicity of your proposal.. but some further script magic would seem to be required?





Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tbcoin on January 15, 2013, 11:27:30 PM
Finally... how it is the Avalon hardware ? It is a complete PC with integrated ASIC? used Raspberry Pi? tablet?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 16, 2013, 12:02:24 AM
Finally... how it is the Avalon hardware ? It is a complete PC with integrated ASIC? used Raspberry Pi? tablet?

The high level controller is to be a small Atheros MIPS board similar to a TL-WR703N running a linux based on OpenWRT.

Like a Raspberry Pi, but even smaller/cheaper/lower-powered, and with no video output.

http://wiki.openwrt.org/toh/tp-link/tl-wr703n


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 16, 2013, 12:14:23 AM

I have a suggestion for future 'pre-order' funds management. <snip>


I really love this idea.
Presumably people would prove they own the address, and agree to the particular terms by signing those terms using a Bitcoin 'sign message' facility.

More generally - this seems like a form of 'layaway' (or lay-by as it's known here in Australia)

I'd like to see a little lay-by management tool for merchants & customers to view their agreement terms and balances.
..but how could we prevent someone using the same funds as part of deals with multiple merchants where the amounts happen to match?
(some people may just reserve way more resources than they are ever going to be able to pay - negatively affecting the utility of the system for merchants)
I like the simplicity of your proposal.. but some further script magic would seem to be required?


I guess I would say 'so what' if people did multiple pre-orders from the same addy?  For one, the address is public so if the merchant decided to give a shit he might be able to detect doubled-up pre-orders, but why should he care, for one, and more importantly...

The idea would be that the merchant only honors the queue position from the documented address.  If that gets spent it automatically drops out of the queue and the next guy in line gets his chance.

If merchants start using such a mechanism (which I doubt since pre-orders generally are a bit corner-case) it is unlikely that two merchants would have exactly the same notional value for a pre-ordered item, and if they did, they could avoid a collision...unless one of them wanted a collision for some reason I suppose...

---

An interesting artifact would be that being #500 in a queue of 300 ASIC chips (for instance) still gives one a decent chance of getting the item anyway.

An interesting fallout from the above in monetary science terms would be that a fair amount of money could be tied up in queues and not used in circulation.  Most mainstream economists would think this is not such a great thing.  I'm not so sure.  In any event, again, pre-orders are likely to be an unusual thing generally.

But as you allude to in your post, the general idea could probably be used for similar sorts of problems with a bit of scripting and perhaps a tool provided by someone for managing such a thing.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: leiyplane on January 16, 2013, 05:20:55 AM
Bitsyncom, any sign of progress now?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cedivad on January 16, 2013, 06:19:28 AM
^

Said the man that invested into the Chinese company.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on January 16, 2013, 06:21:28 AM
http://translate.google.com/#auto/en/%E6%B6%88%E6%81%AF%E7%9A%84%E7%9C%9F%E7%A9%BA%0A%E6%81%B0%E5%A6%82%E9%BB%8E%E6%98%8E%E5%89%8D%E7%9A%84%E9%BB%91%E6%9A%97%0A%E5%8F%88%E4%BC%BC%E4%BB%A4%E4%BA%BA%E7%AA%92%E6%81%AF%E7%9A%84%E9%9D%99%E5%AF%82

... easy enough to understand what it means.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Nemesis on January 16, 2013, 06:41:53 AM
http://translate.google.com/#auto/en/%E6%B6%88%E6%81%AF%E7%9A%84%E7%9C%9F%E7%A9%BA%0A%E6%81%B0%E5%A6%82%E9%BB%8E%E6%98%8E%E5%89%8D%E7%9A%84%E9%BB%91%E6%9A%97%0A%E5%8F%88%E4%BC%BC%E4%BB%A4%E4%BA%BA%E7%AA%92%E6%81%AF%E7%9A%84%E9%9D%99%E5%AF%82

... easy enough to understand what it means.

I love google translate, i can totally hit on a chinese girl with that.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: sounds on January 16, 2013, 07:34:04 AM
They say you really know a language well if you can get a girl who speaks that language to kiss you.

Did it work? Yeah, didn't think so...  ::)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: lucif on January 16, 2013, 10:59:19 AM
I am glad Avalon helping me to dance on Josh bones.

But I should warn all of you about Avalon itself.

No demo, no tests, no bitcoin hashrate increase so far. Only pics with unnamed chips. And 5 days to delivery.

Lets see, lets see...

Hey guys. 4 days left! The question is "4 days left for what?" Say somethething, show something?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on January 16, 2013, 11:51:45 AM
http://translate.google.com/#auto/en/%E6%B6%88%E6%81%AF%E7%9A%84%E7%9C%9F%E7%A9%BA%0A%E6%81%B0%E5%A6%82%E9%BB%8E%E6%98%8E%E5%89%8D%E7%9A%84%E9%BB%91%E6%9A%97%0A%E5%8F%88%E4%BC%BC%E4%BB%A4%E4%BA%BA%E7%AA%92%E6%81%AF%E7%9A%84%E9%9D%99%E5%AF%82

... easy enough to understand what it means.

I love google translate, i can totally hit on a chinese girl with that.

I like google translate coz it allows me to easily understand most things written in most languages.
I only know a small amount of about half a dozen languages, so being able to translate anything at all with the click of a button is great IMO.

For someone as racist as you, that may not be ideal. You probably prefer your ignorance.

For me, it's easy to understand most languages, and for asian languages like Korean, Chinese and Japanese, where it's not as good as others, it gives enough information to usually understand a lot of it also.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: beekeeper on January 16, 2013, 12:06:21 PM
I am glad Avalon helping me to dance on Josh bones.

But I should warn all of you about Avalon itself.

No demo, no tests, no bitcoin hashrate increase so far. Only pics with unnamed chips. And 5 days to delivery.

Lets see, lets see...

Hey guys. 4 days left! The question is "4 days left for what?" Say somethething, show something?

From what I understand, you need to kiss them first.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 16, 2013, 01:06:25 PM
Bitsyncom, any sign of progress now?

Chips should be sliced by now and should have gone through functional testing...in fact, the assembled units should be nearing completion (I would expect at least 1 day on a testnet for each finished unit).

They may be keeping us in the dark for some reason.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cablepair on January 16, 2013, 04:08:13 PM
Excellent work team Avalon,

Congratulations because the way it looks you will be the first team to release an ASIC based mining product.

3 Days away and I want you to know we are all happy and excited for you!


Tom


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: lucif on January 16, 2013, 04:15:22 PM
Yup. Very good product!

Blocks avg. per hour: 4.92
Difficulty:   3,249,550
Next Difficulty: in 947 blocks 3,035,068
Network Hashrate: 21.73 Terahashs/s


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: RoboCoder on January 16, 2013, 04:39:22 PM
Yup. Very good product!

Blocks avg. per hour: 4.92
Difficulty:   3,249,550
Next Difficulty: in 947 blocks 3,035,068
Network Hashrate: 21.73 Terahashs/s

I was looking at this set of graphs: http://bitcoin.sipa.be/index.html (http://bitcoin.sipa.be/index.html)

and it seems like there was a bit of a spike just a little while ago which could have been testing.  Of course, it could be other things as well even testing by BFL (cough, cough) - and there is the DISTINCT possibility i am misinterpreting the graphs.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: SgtSpike on January 16, 2013, 04:43:52 PM
Yup. Very good product!

Blocks avg. per hour: 4.92
Difficulty:   3,249,550
Next Difficulty: in 947 blocks 3,035,068
Network Hashrate: 21.73 Terahashs/s

I was looking at this set of graphs: http://bitcoin.sipa.be/index.html (http://bitcoin.sipa.be/index.html)

and it seems like there was a bit of a spike just a little while ago which could have been testing.  Of course, it could be other things as well even testing by BFL (cough, cough) - and there is the DISTINCT possibility i am misinterpreting the graphs.
BFL won't be testing anything until February based on their timeline.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: RoboCoder on January 16, 2013, 05:45:21 PM
BFL won't be testing anything until February based on their timeline.

I am quite sure you are correct - i was just saying it might imply Avalon HAS done some testing of assembled units already..  Of course ALL of this conjecture about ASICs is a crap shoot until someone actually receives a finished product.

Someone should open a bitcoin betting site that allows betting on who releases first and how close to original specs they were..   just to REALLY beat a dead horse..


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: SgtSpike on January 16, 2013, 05:47:50 PM
 just to REALLY beat a dead horse..
I'm pretty sure all that is left is an indent in the ground.  Maybe a few pieces of bone.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 420 on January 16, 2013, 05:49:13 PM
from what I remember all teams have said they will NOT test on any pools, bitcoin network, and avalon not even on the testnets, etc.

you won't be able to track them until customers are hashing


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: lucif on January 16, 2013, 06:04:24 PM
from what I remember all teams have said they will NOT test on any pools, bitcoin network, and avalon not even on the testnets, etc.

you won't be able to track them until customers are hashing
Just explain me at least one reason not to do that [having chips in hands].


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Raize on January 16, 2013, 06:55:40 PM
Overhead is a good reason not to do it. They really don't care about mining, they just want to sell cards. They don't want to configure a pool, or make it look like they favor one pool over another. I mean, there's plenty of reasons to do so (proof, free coin, etc.), but the reasons not to are mostly ethical in nature. The reasons to do so run the risk of backlash.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 16, 2013, 06:56:36 PM
from what I remember all teams have said they will NOT test on any pools, bitcoin network, and avalon not even on the testnets, etc.

you won't be able to track them until customers are hashing
Just explain me at least one reason not to do that [having chips in hands].

As I understand things, the theory goes that they would jack up the difficulty and burn their customers (who are chomping at the bit to do the same thing.)  And/or damage Bitcoin generally by some non-nondescript means.  Neither has ever made much sense to me.

If I were buying early ASIC, I'd specifically request that my units were burnt in for at least a week ON the Bitcoin network.  If they wanted to be good guys they are welcome to split any profits with me, but I wouldn't request it.

The whole 'we will not mine' thing seems like one of those unimportant things which get moderately ignorant people all worked up and which vendors/scammers/re-sellers/whatever just throw up their hands over and state silly (but mostly harmless) policies because of just for PR reasons.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: lucif on January 16, 2013, 07:00:10 PM
Hehe... https://bitcointalk.org/index.php?topic=136880

They can get 2000+ coins daily in their blocks. In any point in World. This is $28000 daily income. Not being responsible for breaked customers. Did they sign contract with you?

So will they resist this temptation?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 420 on January 16, 2013, 07:02:29 PM
think would you really want to start a trend of ASIC producing companies using their product and reaping the rewards first; increasing the difficulty while holding funds deposited by awaiting customers on a product that was delayed?

That is not good publicity and would NOT be good for bitcoin


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 16, 2013, 07:36:11 PM
think would you really want to start a trend of ASIC producing companies using their product and reaping the rewards first; increasing the difficulty while holding funds deposited by awaiting customers on a product that was delayed?

That is not good publicity and would NOT be good for bitcoin

Like I said, if the vendor wanted to they could discount the unit on the basis of any money generated during the burn-in period.  There is a total amount of money theoretically possible to earn during a few days, and it is not a huge amount.  Just does not seem like a big deal to me. 

As for damage to the Bitcoin network generally, what could it possibly do that is not going to be done several days later when customers receive their units anyway...assuming the units work?

Anyway, there is every bit as much reason to burn in the first generation of ASIC chips and PCBs as there is to test a car coming off the assembly line.  Again, I would almost demand that the vendor do this as one of the tasks I am paying them for (or would be if I were a customer.)



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 420 on January 16, 2013, 08:28:00 PM
One entity with over 22 T/hash/s power at their disposal....I believe there's a phrase often used to describe such a situation


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 16, 2013, 09:04:36 PM
no single sign. this hurts me!  :'(


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: meowmeowbrowncow on January 16, 2013, 09:08:11 PM
think would you really want to start a trend of ASIC producing companies using their product and reaping the rewards first; increasing the difficulty while holding funds deposited by awaiting customers on a product that was delayed?

That is not good publicity and would NOT be good for bitcoin

Like I said, if the vendor wanted to they could discount the unit on the basis of any money generated during the burn-in period.  There is a total amount of money theoretically possible to earn during a few days, and it is not a huge amount.  Just does not seem like a big deal to me. 

As for damage to the Bitcoin network generally, what could it possibly do that is not going to be done several days later when customers receive their units anyway...assuming the units work?

Anyway, there is every bit as much reason to burn in the first generation of ASIC chips and PCBs as there is to test a car coming off the assembly line.  Again, I would almost demand that the vendor do this as one of the tasks I am paying them for (or would be if I were a customer.)




Hmmmmm.


TL;DR:  ASICs and MCU's do not implement the complete block solving protocol - so burn-in testing of all units with full protocol is not needed AT ALL.

The premise is faulty - so it's a non issue in terms of burn-in testing - but very much an issue in terms of vendor credibility.  

The Avalon people were correct when they blasted anyone who suggested that burn-in testing, a complete burn-in cycle, required a full reproduction of the block solving protocol.  It isn't required.  Main net testing is not required.  Testnet-in-a-box is not required.  As a proof of concept measure the first samples of chips would of course need to be confirmed by using a full reproduction of the protocol.  However, still main net testing is not a requirement.  And even then a testing protocol, independent of the full protocol, can be used (must be written) for large scale functionality and burn-in testing of specific purpose for which the ASIC and MCU was designed.

BFL was initially going to use main-net for testing.  Josh/Inaba said it himself.  That is, full burn-in cycle for all units produced.  I and many others blasted them for such a "silly" idea (I quote Avalon).  

BFL's argument was that:

1.  "The dev's" frowned upon using test-net for such large QA activities.  The consequence would be astronomically high difficulty that could interfere with the testing activities of others.
2.  It was not possible to perform testing in other non-impactful ways, so main-net was the choice.

Once this information was made public and was met with criticism BFL claimed that all profit resulting from burn-in testing with main-net would be donated to the miner app dev's.

When this claim of donation of profits did not assuage BFL's critics Josh/Inaba did some blasting of his own by making accusations against those critics that:

1.  Critics didn't care about the miner dev's.
2.  Critics didn't care about the network's security.  Bizarrely, Josh/Inaba twisted critics arguments (memory is hazy) in to one where critics held an irresponsible position and jeopardized network security by the fact that if BFL didn't burn-in test with main-net to establish an equilibrium the combined capacity of units where customers had taken delivery threatened a 51% situation.

Of course, point 2 doesn't hold much water since, at the time, BFL's 1/3 shipping plan called for mass assembly, testing, and shipping thereby largely eliminating the risk of 51% in the hands of either one or a relative few customers.


In my mind this is the point where BFL lost some major credibility.  Either they were lazy or they were greedy.  Take your pick.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 16, 2013, 09:23:25 PM

 <snip - probably much re-hashed debate about real mining as vendor testing just above.>

In my mind this is the point where BFL lost some major credibility.  Either they were lazy or they were greedy.  Take your pick.

Bitcoin itself is still 'experimental'.  I see twanging on the mining effort rates as a good thing.  Any data it adds to the body of knowledge about the behavior of the system is great with me.

I do remember Avalon's statements and thought they were stupid at the time.  It counted as a _negative_ toward their credibility in my mind.

BFL never had any credibility to damage as far as I am concerned.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Exception on January 16, 2013, 09:28:05 PM
Once this information was made public and was met with criticism BFL claimed that all profit resulting from burn-in testing with main-net would be donated to the miner app dev's.

Maybe I misunderstand but since BFL has released their android miner wouldn't they themselves now be the "miner app dev" mentioned?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: meowmeowbrowncow on January 16, 2013, 09:33:09 PM

 <snip - probably much re-hashed debate about real mining as vendor testing just above.>

In my mind this is the point where BFL lost some major credibility.  Either they were lazy or they were greedy.  Take your pick.

Bitcoin itself is still 'experimental'.  I see twanging on the mining effort rates as a good thing.  Any data it adds to the body of knowledge about the behavior of the system is great with me.

I do remember Avalon's statements and thought they were stupid at the time.  It counted as a _negative_ toward their credibility in my mind.

BFL never had any credibility to damage as far as I am concerned.




I understand your sentiment and we can agree on some things.

But to extend the 'experiment' argument let's put AMD in BFL's (prior) position. 

Would it have been necessary, for experimentation reasons, for AMD to burn-in test the 7970 on main-net?

It would not.  It would not have been necessary.  It would have given no value towards understanding bitcoin's behavior.  Nothing that hadn't already been discovered during the CPU to GPU transition.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 16, 2013, 09:52:01 PM
I understand your sentiment and we can agree on some things.

But to extend the 'experiment' argument let's put AMD in BFL's (prior) position. 

Would it have been necessary, for experimentation reasons, for AMD to burn-in test the 7970 on main-net?

It would not.  It would not have been necessary.  It would have given no value towards understanding bitcoin's behavior.  Nothing that hadn't already been discovered during the CPU to GPU transition.

I'm definitely not trying to argue that appropriate burn-in could not be done without using the primary net.  Just that it is (in my opinion) pointless.  And even counter-productive.

For an 'open source' project, Avalon is disappointingly light on details on the avalon-asic.com site, but as I understand things, the devices have at least the capability of being stand-alone units.  That means they have probably a full linux distro*.  All kinds of real-world testing would be appropriate, and specifically hooking up to various pools, solo mining of some for perhaps, etc, since that is what a customer would wish to do. (Though actually to be fair, most of this kind of stuff only needs to happen for a random sample.  If that.)  But generally speaking, it becomes increasingly difficult to emulate real world conditions when things start to become complex.

(*) This reported design is a giant selling point to me.  If I can shit-can the base image and build my own, I very well may pay Avalon some money for some hardware at some point.

---

While I am at it here on this thread, here's a feature request for subsequent generations of gear.

I would like to see some technology (like TPM or some such) which would allow me to make the barrier to entry for unauthorized use high.  The use-case is that I would want to run units remotely and have them be under the care of non-fully-trusted parties.  By making the units as useless as possible to folks other than myself I would hope to encourage the minders to leave them alone (rather than to steal them.)



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Luke-Jr on January 16, 2013, 09:54:31 PM
For an 'open source' project, Avalon is disappointingly light on details on the avalon-asic.com site,
Open source doesn't mean you just get the details/source. It means customers get it with the product.

but as I understand things, the devices have at least the capability of being stand-alone units.  That means they have probably a full linux distro*.
IIRC, someone said it runs Openwrt.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: YipYip on January 16, 2013, 09:55:38 PM

 <snip - probably much re-hashed debate about real mining as vendor testing just above.>

In my mind this is the point where BFL lost some major credibility.  Either they were lazy or they were greedy.  Take your pick.

Bitcoin itself is still 'experimental'.  I see twanging on the mining effort rates as a good thing.  Any data it adds to the body of knowledge about the behavior of the system is great with me.

I do remember Avalon's statements and thought they were stupid at the time.  It counted as a _negative_ toward their credibility in my mind.

BFL never had any credibility to damage as far as I am concerned.




I understand your sentiment and we can agree on some things.

But to extend the 'experiment' argument let's put AMD in BFL's (prior) position.  

Would it have been necessary, for experimentation reasons, for AMD to burn-in test the 7970 on main-net?

It would not.  It would not have been necessary.  It would have given no value towards understanding bitcoin's behavior.  Nothing that hadn't already been discovered during the CPU to GPU transition.

A full Main-net test is not needed... It would not be hard to create a simulated network Test rig with a couple of servers

About 5-8 days dev work for somebody who knows the code base

To do a live main-net test points to no knowledge of the needed process or what they are doing



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Luke-Jr on January 16, 2013, 10:01:09 PM
It would not be hard to create a simulated network Test rig with a couple of servers
It would take all of 5 minutes on 1 server to setup a private testnet for any number of devices using GBT.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 16, 2013, 10:07:03 PM
For an 'open source' project, Avalon is disappointingly light on details on the avalon-asic.com site,
Open source doesn't mean you just get the details/source. It means customers get it with the product.

If I cannot evaluate things to my satisfaction before I pull out my private key, the private key will remain in it's protected sheath.  Just sayin'.  If I hear back from credible sources that I have a hope of obtaining the control over the device that I want, that may be good enough though.
but as I understand things, the devices have at least the capability of being stand-alone units.  That means they have probably a full linux distro*.
IIRC, someone said it runs Openwrt.

That's a 'full Linux distro' to me.  (To be fair, I've not played with OpenWRT yet at this point.)

edit: quotes


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: YipYip on January 16, 2013, 11:12:14 PM
Huh... 14th, then the 19th, now it's the 21st? 

Interesting...

You get very little irony in your diet, true...?


It's not irony when I'm pointing out that they are doing the exact same thing they have been vilifying us for.  So, yeah, I guess it's irony, but not on my part.

BitSyncom: We are shipping on the 14th! BFL you keep pushing your date back, it is dishonest to push your date back!
BitSyncom: We are shipping on the 19th! BFL you keep pushing your date back, you suck because you keep missing your date!
BitSyncom: We are shipping on the 21st! BFL you keep pushing your date back, we've only pushed it back two days!

I guess we'll see in another 7 days.  Irony indeed.


Be quite the adults are speaking


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: John (John K.) on January 17, 2013, 05:10:12 AM
Libertybuck and nemesis, stop your off topic trolling here. Languages other than English go to the Local subsection. In person attacks and posts filled with off-topic cursing go to the trashcan. Consider this a warning.
(PS: Yes, I understand Chinese perfectly without Google Translate)

Continue the civil discussion please.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: libertybuck on January 17, 2013, 06:45:23 AM
Libertybuck and nemesis, stop your off topic trolling here. Languages other than English go to the Local subsection. In person attacks and posts filled with off-topic cursing go to the trashcan. Consider this a warning.
(PS: Yes, I understand Chinese perfectly without Google Translate)

Continue the civil discussion please.

Sir,

Thanks for your justice.

I have a silly question here: what's the TOPIC we are discussing here ?

If I remember it correctly, it should be:  [Announcement] Avalon ASIC Development Status [Batch #1].  Isn't it ?

I am a customer of Avalon ASIC, why could not I post rely here ?


>  "Languages other than English go to the Local subsection."

So, Avalon customers from Asia, Russian and so on have no right to discuss with device provider about project status here ?

Topic ower and I say same kind of language. Why couldn't I ask him question with mother language ?


> In person attacks and posts filled with off-topic cursing go to the trashcan. Consider this a warning.

nemesis attacked I and my national language first. Do you know ?  If you are fair, you should drag him to trashcan.
 


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MeSarah on January 17, 2013, 08:01:58 AM
So after waiting days for the Avalon team to clarify the claims they made of having 10+ years experience producing ASICs they have failed to address the issue I have raised. I said they would avoid the issue of experience and they have done just that. The Avalon team's silence is thunderous. After all if they tell the community the truth after lying the community would rip them a new orifice and kill their chance of a successful second round of pre-orders. But after Tom's debacle it is unlikely that many would be willing to go the pre-oreder route again when purchasing an ASIC product.

So let's approach the question of Avalon's experience from a different direction. It has been reported that Avalon bought something like 1000 ASIC chips from Tom, sight unseen and untested. The use of Tom's ASIC would require a new PCB, chassis and power supply, bASICally a completely new product. This being true even though Avalon was going to be first to market. A thinking person can see my next question before it is even asked.

If the Avalon team is so skilled in manufacturing an ASIC product why don't they have the confidence in their own product? Why does the Avalon development team believe an untested, still in development ASIC is a better product then the one they have produced?

http://www.youtube.com/watch?v=8_EnrVf9u8s

It is becoming increasingly unlikely that Avalon's production run will exceed 300 units. I personally believe that there is a greater than 80% chance that Avalon will become the next failed Bitcion ASIC producer.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: creativex on January 17, 2013, 08:12:56 AM
I personally believe that there is a greater than 80% chance that Avalon will become the next failed Bitcion ASIC producer.

Time will tell. They certainly have a very long way to go to match BFL's incredible level of FAIL.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: WhitePhantom on January 17, 2013, 08:36:34 AM
I personally believe that there is a greater than 80% chance that Avalon will become the next failed Bitcion ASIC producer.
I assume you're a heavily invested BFL customer?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Uuno on January 17, 2013, 09:40:36 AM
So after waiting days for the Avalon team to clarify the claims they made of having 10+ years experience producing ASICs they have failed to address the issue I have raised. I said they would avoid the issue of experience and they have done just that. The Avalon team's silence is thunderous. After all if they tell the community the truth after lying the community would rip them a new orifice and kill their chance of a successful second round of pre-orders. But after Tom's debacle it is unlikely that many would be willing to go the pre-oreder route again when purchasing an ASIC product.

So let's approach the question of Avalon's experience from a different direction. It has been reported that Avalon bought something like 1000 ASIC chips from Tom, sight unseen and untested. The use of Tom's ASIC would require a new PCB, chassis and power supply, bASICally a completely new product. This being true even though Avalon was going to be first to market. A thinking person can see my next question before it is even asked.

If the Avalon team is so skilled in manufacturing an ASIC product why don't they have the confidence in their own product? Why does the Avalon development team believe an untested, still in development ASIC is a better product then the one they have produced?

http://www.youtube.com/watch?v=8_EnrVf9u8s

It is becoming increasingly unlikely that Avalon's production run will exceed 300 units. I personally believe that there is a greater than 80% chance that Avalon will become the next failed Bitcion ASIC producer.

I really, really hope that Avalon succeed but you have a good point/question here.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: John (John K.) on January 17, 2013, 11:36:31 AM
Libertybuck and nemesis, stop your off topic trolling here. Languages other than English go to the Local subsection. In person attacks and posts filled with off-topic cursing go to the trashcan. Consider this a warning.
(PS: Yes, I understand Chinese perfectly without Google Translate)

Continue the civil discussion please.


Sir,

Thanks for your justice.

I have a silly question here: what's the TOPIC we are discussing here ?

If I remember it correctly, it should be:  [Announcement] Avalon ASIC Development Status [Batch #1].  Isn't it ?

I am a customer of Avalon ASIC, why could not I post rely here ?


>  "Languages other than English go to the Local subsection."

So, Avalon customers from Asia, Russian and so on have no right to discuss with device provider about project status here ?

Topic ower and I say same kind of language. Why couldn't I ask him question with mother language ?


> In person attacks and posts filled with off-topic cursing go to the trashcan. Consider this a warning.

nemesis attacked I and my national language first. Do you know ?  If you are fair, you should drag him to trashcan.
 

Didn't you realize that BOTH of your posts are already deleted? You can PM him in your mother tongue if it suits you and him, just don't do it here. Your last few posts are filled with ad-hominem attacks against him, and is off-topic.

Back to the topic;we have  3 days to go for the shipping to occur. I would wager that most people are currently on the fence to see where they'll put their money now. Expect a massive wave of requests for refunds at BFL if Avalon pulls through....


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 17, 2013, 11:38:27 AM
So after waiting days for the Avalon team to clarify the claims they made of having 10+ years experience producing ASICs they have failed to address the issue I have raised. I said they would avoid the issue of experience and they have done just that. The Avalon team's silence is thunderous. After all if they tell the community the truth after lying the community would rip them a new orifice and kill their chance of a successful second round of pre-orders. But after Tom's debacle it is unlikely that many would be willing to go the pre-oreder route again when purchasing an ASIC product.

So let's approach the question of Avalon's experience from a different direction. It has been reported that Avalon bought something like 1000 ASIC chips from Tom, sight unseen and untested. The use of Tom's ASIC would require a new PCB, chassis and power supply, bASICally a completely new product. This being true even though Avalon was going to be first to market. A thinking person can see my next question before it is even asked.

If the Avalon team is so skilled in manufacturing an ASIC product why don't they have the confidence in their own product? Why does the Avalon development team believe an untested, still in development ASIC is a better product then the one they have produced?

http://www.youtube.com/watch?v=8_EnrVf9u8s

It is becoming increasingly unlikely that Avalon's production run will exceed 300 units. I personally believe that there is a greater than 80% chance that Avalon will become the next failed Bitcion ASIC producer.
Alright, I will bite.

What links do you have to solidly support the idea that Avalon purchases 1000+ ASIC devices (or otherwise) from Tom?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: pent on January 17, 2013, 11:42:53 AM
Why Avalon beats about the bush? Show us something... You probably have a full room of well-tested packages.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 17, 2013, 12:53:32 PM
Back to the topic;we have  3 days to go for the shipping to occur. I would wager that most people are currently on the fence to see where they'll put their money now. Expect a massive wave of requests for refunds at BFL if Avalon pulls through....

Personally, I wouldn't want a refund unless Avalon's second batch is somehow going to beat BFL's first...and if they can somehow get the power usage down.

I'm somewhat confused by why they aren't showing off shiny ASICs right now.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cedivad on January 17, 2013, 01:06:28 PM
They are either trolling us by letting us here cooking or running away.

I must say that I find it really strange not to have any kind of update. Why should they not update us here if they are on schedule? I fear that something went wrong. (I suggested guys here to resell their order... It would have been a safe and big gain).


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: greyhawk on January 17, 2013, 01:07:21 PM
Did the countdown clock just lose a day or was that me?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hope2907 on January 17, 2013, 01:25:58 PM
3 days left, not even a picture


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Vicus on January 17, 2013, 01:30:28 PM
So, I put that here :)

http://puu.sh/1OQYs


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: greyhawk on January 17, 2013, 01:32:42 PM
I'm not gonna click whatever that is. Post a real URL.  >:(


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: pent on January 17, 2013, 01:34:58 PM
Looks like just a picture

Code:
[pentarh@pentbook ~]$ HEAD http://puu.sh/1OQYs
200 OK
Cache-Control: public, max-age=43200
Connection: close
Date: Thu, 17 Jan 2013 xxxx GMT
Accept-Ranges: bytes
Server: cloudflare-nginx
Content-Length: 84438
Content-Type: image/jpeg
Expires: Fri, 18 Jan 2013 xxx GMT
Last-Modified: Thu, 17 Jan 2013 xxx GMT
CF-Cache-Status: HIT
CF-RAY: xxx
Client-Date: Thu, 17 Jan 2013 xxx GMT
Client-Peer: 108.162.197.128:80
Client-Response-Num: 1
Content-Disposition: inline; filename="ss (2013-01-18 at 12.29.15).jpg"


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tbcoin on January 17, 2013, 01:35:54 PM
I'm not gonna click whatever that is. Post a real URL.  >:(

Is a real URL. (paranoid mode on)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Vicus on January 17, 2013, 01:38:37 PM
I'm not gonna click whatever that is. Post a real URL.  >:(
puu.sh one of many instant screenshot post service...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: greyhawk on January 17, 2013, 01:44:29 PM
Huh, apparently it is.

These site names get progressively worse.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 17, 2013, 01:45:59 PM
So, I put that here :)

http://puu.sh/1OQYs

<ironic>sounds trustworthy to me!</ironic>

http://i47.tinypic.com/2r45uhc.jpg



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 17, 2013, 01:48:42 PM

Didn't you realize that BOTH of your posts are already deleted? You can PM him in your mother tongue if it suits you and him, just don't do it here. Your last few posts are filled with ad-hominem attacks against him, and is off-topic.

Back to the topic;we have  3 days to go for the shipping to occur. I would wager that most people are currently on the fence to see where they'll put their money now. Expect a massive wave of requests for refunds at BFL if Avalon pulls through....
I think I would expect a massive wave of refunds at BFL if Avalon falters just the same.

2 of 3 failures*  is a pretty bad sign in any sane mind. It would probably be enough to scare people into pulling their cash out immediately.

(Not including ASICMINER which is probably a success)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 17, 2013, 01:49:25 PM
So, I put that here :)

http://puu.sh/1OQYs

<ironic>sounds trustworthy to me!</ironic>

http://i47.tinypic.com/2r45uhc.jpg


That irony is a shared affair, apparently. I thought exactly the same.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tbcoin on January 17, 2013, 01:53:26 PM
thy are switching all from QFN to BGA  :D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 17, 2013, 02:10:33 PM
thy are switching all from QFN to BGA  :D

don't try at home kids!!  ::)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: squeept on January 17, 2013, 07:33:08 PM
Time will tell. They certainly have a very long way to go to match bASIC's incredible level of FAIL.

FTFY.

Also, holy unbelievable shit. You're still talking shit on BFL despite having violently defended a company that ACTUALLY went under?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on January 17, 2013, 07:45:23 PM
Time will tell. They certainly have a very long way to go to match bASIC's incredible level of FAIL.
FTFY.

Also, holy unbelievable shit. You're still talking shit on BFL despite having violently defended a company that ACTUALLY went under?
Exactly. Tom stopped talking in December. Avalon team hasn't said hardly anything, even tho they're "days" away from shipping. And Josh has posted pages of information dealing with their chip redesign, and a schedule for the next 3 weeks until they ship. So who's the delusional one in this picture?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 17, 2013, 07:54:50 PM
This point has been made before, but if Avalon is not trying to get people to send them money, there is not a real good reason to expend a lot of effort on proving that they actually have something.

Under the hypothesis that they have gear and a pretty anticipated production rate going forward, a good psychological strategy would actually be to let doubt and accusations build to a crescendo, then just go ahead and make their early deliveries without a lot of fan-fair.  The effect that would have would be to quash a lot of future doubt in whatever projects are to come.

I, of course, have no idea if Avalon is legit, total scam, or something in between.  I hope they are legit because I am starting to feel that it might make sense to get into mining (although not particularly for an immediate profit) and the basic design these guys elude to is compelling to me.

I do wish Avalon were more forthcoming with information, and that they are not counts as a negative to me, but as I mentioned it could be the case that there is not a compelling business case to be.  And they are likely fairly busy.  If they do not take the time to work on transparency at some point I can be pretty confident that they'll not count me as a customer.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Sitarow on January 17, 2013, 08:07:28 PM
This point has been made before, but if Avalon is not trying to get people to send them money, there is not a real good reason to expend a lot of effort on proving that they actually have something.

Under the hypothesis that they have gear and a pretty anticipated production rate going forward, a good psychological strategy would actually be to let doubt and accusations build to a crescendo, then just go ahead and make their early deliveries without a lot of fan-fair.  The effect that would have would be to quash a lot of future doubt in whatever projects are to come.

I, of course, have no idea if Avalon is legit, total scam, or something in between.  I hope they are legit because I am starting to feel that it might make sense to get into mining (although not particularly for an immediate profit) and the basic design these guys elude to is compelling to me.

I do wish Avalon were more forthcoming with information, and that they are not counts as a negative to me, but as I mentioned it could be the case that there is not a compelling business case to be.  And they are likely fairly busy.  If they do not take the time to work on transparency at some point I can be pretty confident that they'll not count me as a customer.



Customers that request a refund at this stage should not be surprised to discover the queue of willing customers desperate to pre-order devices as they become available.

This project has a good track record of not taking pre-orders for a future batch.

I recall Tom from bASIC also did not want to take orders on the 2nd batch, however people insisted that he continue taking pre-orders.

That should help put into perspective what bASIC's initial batch would cost to complete.

In retrospect the steps taken by this project team have worked in keeping them focused on the task at hand.

Short of any unforeseen events that may delay the project. The Avalon project and its team, have to contend with similar pitfalls that have delayed other ASIC projects.

Attempting to anticipate all possible outcomes is a waste of effort with such projects.

Hindsight is 20/20.

Keep up the good work.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: jamesg on January 17, 2013, 08:09:02 PM
So who's the delusional one in this picture?

+1


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Aseras on January 17, 2013, 08:13:20 PM
Avalons guys don't give a crap about marketing or fanfare. This thing has been in the works for a long time. ngzhang has never been one to talk much. He's no BS straight shooting and he delivers. Look up his profile and read his posts. He doesn't spend most of his time making thing pretty or flaunting his works like BFL or the other. The closest they came to flaunting anything is announcing some slight speed boosts and the countdown clock on the website. He knows his shit. BFL can even decide on packaging even after 3+ months of delays. Heat is a BS excuse, they would have shipped a first gen and then improved it later if they had a real product.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 17, 2013, 08:26:20 PM
Avalons guys don't give a crap about marketing or fanfare. This thing has been in the works for a long time. ngzhang has never been one to talk much. He's no BS straight shooting and he delivers. Look up his profile and read his posts. He doesn't spend most of his time making thing pretty or flaunting his works like BFL or the other. The closest they came to flaunting anything is announcing some slight speed boosts and the countdown clock on the website. He knows his shit. BFL can even decide on packaging even after 3+ months of delays. Heat is a BS excuse, they would have shipped a first gen and then improved it later if they had a real product.

Agree.  From the time ~ngzhang showed up on this forum he seemed like and interested and thoughtful person.  Nothing more or less.  And all of the technical stuff I've seen from him seem quite credible to me (although I'm not terribly qualified to make a call here.)

I've sorta vaguely worked with Yifu in a minor way once.  Although I was not totally impressed with him as a conceptual visionary, I never had reason to doubt his integrity.  I did feel that bitsyncom was a little to eager to monopolize the project I had some interested in, and that they never really followed through very well.  I lost interest and/or had a philosophical shift as well so I cannot hold that against them to much.

Anyhow, all of these things together give me some degree of hope for the Avalon project (relative to BFL or bASIC...which is not saying much...)



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 17, 2013, 09:24:19 PM
...
I've sorta vaguely worked with Yifu in a minor way once.  Although I was not totally impressed with him as a conceptual visionary, I never had reason to doubt his integrity.  I did feel that bitsyncom was a little to eager to monopolize the project I had some interested in, and that they never really followed through very well.  I lost interest and/or had a philosophical shift as well so I cannot hold that against them to much.
...

Actually, in the interest of analyzing all inputs, I should point out one thing which had slipped my mind.  Yifu did seem to have a non-trivial involvement with Bruce and his show.

I personally don't consider this to be a sure sign of scammery as I am pretty confident that some people who had a personal involvement with him were unaware of what a dirt-bag he was.  Much to my embarrassment Bruce fooled the shit out of me on-line.  He probably would have in person as well if had ever met him.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Syke on January 17, 2013, 09:59:30 PM
So who's the delusional one in this picture?

Anyone who thinks BFL is going to meet the currently published timeline.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Unacceptable on January 17, 2013, 09:59:35 PM
thy are switching all from QFN to BGA  :D

No no no,they're adding clock buffers!!!!!!!!!!!!!!  :D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 17, 2013, 10:03:00 PM
thy are switching all from QFN to BGA  :D

No no no,they're adding clock buffers!!!!!!!!!!!!!!  :D

don't try at home neither, kids!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 18, 2013, 02:00:11 AM
This point has been made before, but if Avalon is not trying to get people to send them money, there is not a real good reason to expend a lot of effort on proving that they actually have something.

Actually, I would say that it's an excellent reason. It would demonstrate that they actually care about keeping their existing customers well informed - every bit of positive news from BFL/bASIC is aimed at least partially at getting more pre orders.

Unfortunately, they have given up this opportunity.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tvbcof on January 18, 2013, 02:39:10 AM
This point has been made before, but if Avalon is not trying to get people to send them money, there is not a real good reason to expend a lot of effort on proving that they actually have something.

Actually, I would say that it's an excellent reason. It would demonstrate that they actually care about keeping their existing customers well informed - every bit of positive news from BFL/bASIC is aimed at least partially at getting more pre orders.

Unfortunately, they have given up this opportunity.

They've got a mailing list or forum or something, and presumably when one put in a pre-order they have e-mail addresses for news.  I've not tried to sign up for it (so I probably should not be bitching about lack of design details I guess.)  Anyway, the purported shipping date is right around the corner so it's almost pointless at this point to worry to much about lack of info.  We'll know soon enough if they've got anything.

As for your opportunity, I surmise that any potential you had to be an early-bird has flown long ago.  If they (have something which works and) stick with their pretty modest supply estimates, one does not suspect that they'll be needing a huge amount of effort to keep the pre-order pipelines full.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 18, 2013, 04:02:07 AM
This point has been made before, but if Avalon is not trying to get people to send them money, there is not a real good reason to expend a lot of effort on proving that they actually have something.

Actually, I would say that it's an excellent reason. It would demonstrate that they actually care about keeping their existing customers well informed - every bit of positive news from BFL/bASIC is aimed at least partially at getting more pre orders.

Unfortunately, they have given up this opportunity.

I would rather they spend their energy on fulfilling orders than making photo galleries or writing forum posts.

They say everything's on track and they're shipping in less than 3 days.  I don't feel the need to ask for more information.  I think all of the important questions have been answered.

All I need now is just a little more patience.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on January 18, 2013, 04:47:08 AM
This point has been made before, but if Avalon is not trying to get people to send them money, there is not a real good reason to expend a lot of effort on proving that they actually have something.

Actually, I would say that it's an excellent reason. It would demonstrate that they actually care about keeping their existing customers well informed - every bit of positive news from BFL/bASIC is aimed at least partially at getting more pre orders.

Unfortunately, they have given up this opportunity.

I would rather they spend their energy on fulfilling orders than making photo galleries or writing forum posts.

They say everything's on track and they're shipping in less than 3 days.  I don't feel the need to ask for more information.  I think all of the important questions have been answered.

All I need now is just a little more patience.
... except they've skipped a big item that they said they would do ...
Demo.

If they reach their current modified deadline, good, but if they don't ...

Anyway, I do not see a reason for not spending 5 minutes writing an update.
Will that make them deliver 5 minutes later? :P
Effort to do a demo? A couple of hours? (if the people doing it are pretty lacking in skills required - a lot less if they know what they are doing)
Will that make them deliver a couple of hours later?

At this point in time, it's quite simple to state the obvious:
To do a Demo requires fully functional hardware, firmware and software.
To not do a demo suggests ... ? Who knows?
Feel free to fill in the blanks where none is supplied ...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: regular on January 18, 2013, 05:27:43 AM
perhaps they feel if they ship first, they can catch BFL with their pants down.

If they release a demo now, BFL might rush to ship theirs and negate the Avalon advantage.  Just a thought coming from an ex-bASIC preorderer.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MrTeal on January 18, 2013, 06:15:19 AM
perhaps they feel if they ship first, they can catch BFL with their pants down.

If they release a demo now, BFL might rush to ship theirs and negate the Avalon advantage.  Just a thought coming from an ex-bASIC preorderer.

BFL is rushing to ship theirs as best they can. They have nothing to ship, and Avalon shipping or not won't speed up the fact that their chips aren't ready to ship.

Avalon could demo now and start taking preorders for the next batch in late Feb. Given the delays BFL has had, it wouldn't be too far fetched that customers with high preorder numbers might jump ship and join new money in buying Avalon. The could sell a ridiculous number of units in a short time with proof that they have a working, mining ASIC.

That they don't, 3 days before their countdown expires... We'll see. Maybe they'll just delay a couple days, but I'd be shocked if they had units in the mail 55 hours from now.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bitmar on January 18, 2013, 07:45:22 AM
Where can I find photos of AVALON's rig?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Vicus on January 18, 2013, 08:03:00 AM
Where can I find photos of AVALON's rig?
Nowere


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 18, 2013, 10:11:40 AM
.. except they've skipped a big item that they said they would do ...
Demo.

Yep. I'm only holding them to their own terms.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bitmar on January 18, 2013, 10:45:55 AM
Where can I find photos of AVALON's rig?
Nowere

No photos, no demo... this a joke? LOL
I never understood the Asian sense of humor.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazy_rabbit on January 18, 2013, 10:53:19 AM
Why is it normal in the BTC community to demand photos of products before they are released? It's not like Apple would show us the iphone 6 just so we could cream our panties in anticipation.

That said, Apple is apple and BTC is something else.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bitmar on January 18, 2013, 11:13:56 AM
Why is it normal in the BTC community to demand photos of products before they are released? It's not like Apple would show us the iphone 6 just so we could cream our panties in anticipation.

That said, Apple is apple and BTC is something else.

This is normal in any kind of community. Usually you can see what you're buying, besides buying a lottery ticket.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazy_rabbit on January 18, 2013, 11:34:28 AM
Why is it normal in the BTC community to demand photos of products before they are released? It's not like Apple would show us the iphone 6 just so we could cream our panties in anticipation.

That said, Apple is apple and BTC is something else.

This is normal in any kind of community. Usually you can see what you're buying, besides buying a lottery ticket.

Well, a pot of gold is kinda like a lottery ticket. :-)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: server on January 18, 2013, 02:08:57 PM
It will cause delay once we start shipping, it was pretty much a heads up before the 20th. I'll get to you guys early next week. I simply haven't gotten around to double check yet due to being swarmed.

Can you give us an update about this 'order status = Processing' problem and what delay we can expect ?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cypherdoc on January 18, 2013, 04:28:37 PM
when is THE day?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: jamesg on January 18, 2013, 04:34:09 PM
when is THE day?

1d ~21h to go.....


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 18, 2013, 04:43:52 PM

Countdown at: http://www.avalon-asics.com/

Looks like it's set for Sunday 20-Jan 12:00 PM UTC, which is Sunday 20-Jan 8:00 PM CST (China Standard Time).


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on January 18, 2013, 05:21:16 PM
Why is it normal in the BTC community to demand photos of products before they are released? It's not like Apple would show us the iphone 6 just so we could cream our panties in anticipation.

That said, Apple is apple and BTC is something else.
Normally I'm with you, but they did say that they'd release a demo...  ::)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Turbor on January 18, 2013, 05:23:33 PM
I wish them the best ! Go team China ;)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: rudrigorc2 on January 18, 2013, 06:23:33 PM
you guys noticed the title for the www.avalon-asic.com website?

Quote
world's first consumer bitcoin mining ASIC.

sounds pretty confident.

I just saw this. what about you?



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mjc on January 18, 2013, 07:04:45 PM
Are there any confirmed miners like cgminer that will work or has worked with them?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on January 18, 2013, 07:08:36 PM
Are there any confirmed miners like cgminer that will work or has worked with them?
They had stated that they would be using a version of CGMiner, but Kano pointed out that they cannot use an altered version of CGMiner without first releasing their code changes, which they have not done.

Edit: Meh I was confused. Turns out they can ship an image with a modified CGMiner without having to publicly release the source code.

What they did promise was a system image for their WRT that would include a version of CGMiner. This is what they havn't made public yet, to my knowledge. Again, I got a little confused, so apologies.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 18, 2013, 07:12:26 PM
Are there any confirmed miners like cgminer that will work or has worked with them?

It's to come with it's own on-board miner host.  All you need to do is plug Avalon into a DHCP-enabled LAN, configure using a browser (presumably), and you're mining.

I believe internally it's to run cgminer or bfgminer (I forget which), and is to be all open source and friendly so you can connect your own miner host if you wish instead of using the onboard one.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: regular on January 18, 2013, 07:37:06 PM
perhaps they feel if they ship first, they can catch BFL with their pants down.

If they release a demo now, BFL might rush to ship theirs and negate the Avalon advantage.  Just a thought coming from an ex-bASIC preorderer.

BFL is rushing to ship theirs as best they can. They have nothing to ship, and Avalon shipping or not won't speed up the fact that their chips aren't ready to ship.

Avalon could demo now and start taking preorders for the next batch in late Feb. Given the delays BFL has had, it wouldn't be too far fetched that customers with high preorder numbers might jump ship and join new money in buying Avalon. The could sell a ridiculous number of units in a short time with proof that they have a working, mining ASIC.

That they don't, 3 days before their countdown expires... We'll see. Maybe they'll just delay a couple days, but I'd be shocked if they had units in the mail 55 hours from now.

True but BFL may have more expensive options they don't wish to do at this time.  For example Tom with the bASIC had mentioned assembly in the USA vs China which would be faster but cost more.  Avalon showing off their device might make it worthwhile for BFL to pay more for domestic assembly to maintain their reputation.  However if Avalon just ships with no notice, BFL will not have the time to switch production lines.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: jjiimm_64 on January 18, 2013, 07:54:06 PM
make it worthwhile for BFL to pay more for domestic assembly to maintain their reputation.  However if Avalon just ships with no notice, BFL will not have the time to switch production lines.

Please know your subject before posting:

BFL is already doing it domistically in the US


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Luke-Jr on January 18, 2013, 08:04:43 PM
Are there any confirmed miners like cgminer that will work or has worked with them?
They had stated that they would be using a version of CGMiner, but Kano pointed out that they cannot use an altered version of CGMiner without first releasing their code changes, which they have not done.
Kano is wrong, if he actually said this. The license cgminer and BFGMiner are distributed under allows them to keep their code semi-private, so long as they ship the devices with the code (including instructions for putting it on the device). Of course, any customer who receives this may do what they want with it (including send it to Con), but there is no reason to assume they need to send it to him themselves beforehand.

Also, I'm not aware of any statement that they are switching to the cgminer fork instead of sticking with BFGMiner.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on January 18, 2013, 08:10:35 PM
Are there any confirmed miners like cgminer that will work or has worked with them?
They had stated that they would be using a version of CGMiner, but Kano pointed out that they cannot use an altered version of CGMiner without first releasing their code changes, which they have not done.
Kano is wrong, if he actually said this. The license cgminer and BFGMiner are distributed under allows them to keep their code semi-private, so long as they ship the devices with the code (including instructions for putting it on the device). Of course, any customer who receives this may do what they want with it (including send it to Con), but there is no reason to assume they need to send it to him themselves beforehand.

Also, I'm not aware of any statement that they are switching to the cgminer fork instead of sticking with BFGMiner.
I may have misread him, so if I did, I"m sorry. It's been a weird couple of days. Maybe I'm thinking of them saying that they would release an image with the included CGMiner, and they never did?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Fuzzy on January 18, 2013, 08:13:42 PM
I for one can't wait to get in on the next batch.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: midnightmagic on January 18, 2013, 08:24:07 PM
Are there any confirmed miners like cgminer that will work or has worked with them?
They had stated that they would be using a version of CGMiner, but Kano pointed out that they cannot use an altered version of CGMiner without first releasing their code changes, which they have not done.

That is incorrect. They can release their software, and then wait for requests for source code, and fulfill them as per GPL. They do NOT have to pre-release their modifications.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Luke-Jr on January 18, 2013, 08:25:38 PM
Are there any confirmed miners like cgminer that will work or has worked with them?
They had stated that they would be using a version of CGMiner, but Kano pointed out that they cannot use an altered version of CGMiner without first releasing their code changes, which they have not done.

That is incorrect. They can release their software, and then wait for requests for source code, and fulfill them as per GPL. They do NOT have to pre-release their modifications.
The GPL allows the product to ship with an offer to anyone to send the code. If they elected this option, they could not keep it even semi-private, since anyone (not only their customers) would have a right to request the code from them.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on January 18, 2013, 08:26:02 PM
Are there any confirmed miners like cgminer that will work or has worked with them?
They had stated that they would be using a version of CGMiner, but Kano pointed out that they cannot use an altered version of CGMiner without first releasing their code changes, which they have not done.
That is incorrect. They can release their software, and then wait for requests for source code, and fulfill them as per GPL. They do NOT have to pre-release their modifications.
Ya LJR already stated that above. Thanks tho.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: sharky112065 on January 18, 2013, 08:38:03 PM
Also, I'm not aware of any statement that they are switching to the cgminer fork instead of sticking with BFGMiner.

I see your reality distortion field is in full operation. BFGMiner was forked from CGMiner. It will always be so, no matter how many times you try to convince others of the inverse.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bce on January 18, 2013, 09:03:51 PM
Also, I'm not aware of any statement that they are switching to the cgminer fork instead of sticking with BFGMiner.

I see your reality distortion field is in full operation. BFGMiner was forked from CGMiner. It will always be so, no matter how many times you try to convince others of the inverse.

It's a pretty weak distortion field at that :P.  I just hope that BFGMiner (which the BFL android app will be using) is or has been fixed with proper stratum support as is the case in CG Miner.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: RoboCoder on January 18, 2013, 09:13:44 PM
I just hope that BFGMiner (which the BFL android app will be using) is or has been fixed with proper stratum support as is the case in CG Miner.

It has had excellent stratum support for quite a number of rev's now and i prefer it to CGMiner - especially 2.10.2 with the Zero Stats feature.. love that..


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Luke-Jr on January 18, 2013, 09:25:01 PM
Also, I'm not aware of any statement that they are switching to the cgminer fork instead of sticking with BFGMiner.
I see your reality distortion field is in full operation. BFGMiner was forked from CGMiner. It will always be so, no matter how many times you try to convince others of the inverse.
BFGMiner was forked from CGMiner-the-GPU-miner. CGMiner-with-modular-device-support came from BFGMiner.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Raize on January 18, 2013, 09:33:06 PM
I may have misread him, so if I did, I"m sorry. It's been a weird couple of days. Maybe I'm thinking of them saying that they would release an image with the included CGMiner, and they never did?

I may have contributed to the confusion when I mentioned I used a xiangfu-designed OpenWRT binary with cgminer support with my Icarus. I apologize if anyone thought I was implying malfeasance on the Avalon development team's part. I have no idea if they are going to use bfgminer or cgminer or something completely different. I would suspect they will be supporting a lot of different options, not just in choice of miner.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: sharky112065 on January 18, 2013, 10:35:04 PM
Also, I'm not aware of any statement that they are switching to the cgminer fork instead of sticking with BFGMiner.
I see your reality distortion field is in full operation. BFGMiner was forked from CGMiner. It will always be so, no matter how many times you try to convince others of the inverse.
BFGMiner was forked from CGMiner-the-GPU-miner. CGMiner-with-modular-device-support came from BFGMiner.

No, You added Modular device support to CGMiner via acceptance from the CGMiner project maintainer, and threw a hissy fit when some of your changes were either rejected or took too long to be merged and then you forked BFGminer from CGMiner. Just because you contributed code to CGMiner and later forked the project does not make your delusions that CGMiner was forked from BFGMiner true. Yes you contributed code to CGMiner and then forked the project. CGMiner is not a fork of BFGminer and you know it. You use your delusion to try to make yourself look superior in some way.  You have even removed CGMiner from the wiki as well. You sir seem to have some self esteem issues (as in you use this reality distortion field of yours to hopefully make people think you are superior - it's not working).

For those that cant seem to get past his Reality Distortion Field, here is the proof.
https://github.com/luke-jr/bfgminer/commit/b9df56511c7bd1a2e1f075e9c184c1a4b0f1ba20

Edit: and more of his wiki editing trying to edit CGMiner out of existance.
https://en.bitcoin.it/w/index.php?title=P2Pool&action=historysubmit&diff=31023&oldid=30982


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: tbcoin on January 19, 2013, 12:52:48 AM

Countdown at: http://www.avalon-asics.com/

Looks like it's set for Sunday 20-Jan 12:00 PM UTC, which is Sunday 20-Jan 8:00 PM CST (China Standard Time).

... Start shipping a Sunday at 8pm... really?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 19, 2013, 03:08:22 AM

Way to add some value to the discussion.  I've quoted the parts I liked.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 19, 2013, 03:10:34 AM

Countdown at: http://www.avalon-asics.com/

Looks like it's set for Sunday 20-Jan 12:00 PM UTC, which is Sunday 20-Jan 8:00 PM CST (China Standard Time).

... Start shipping a Sunday at 8pm... really?

Maybe it's business as usual in China on Sundays?  I guess I don't know, myself.

I do know that DHL Express will provide Sunday delivery in the US, by request.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: dust on January 19, 2013, 03:23:51 AM
@dust

if you recall there some server problem when the site first launched, please send me a email/PM with your bitcoin order ID and payment address so I may manually check aganist the system.

The system was automatically set orders to cancel if they have not been paid, and since due to server errors some order which got paid never got the call back to mark them as completed thus were in turn canceled.

No worries though, we keep all the records so we can double check aganist this.
Any update on this?  I sent a PM within 15 minutes of your reply and have received no response or update to my ticket  I'm sure the team is busy :)
I still have received no communication from Avalon about this and my paid order is still listed as cancelled.  I'm getting concerned as the shipping date is very near, and I believe there are other customers with the same problem as well.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Phinnaeus Gage on January 19, 2013, 03:25:22 AM

Countdown at: http://www.avalon-asics.com/

Looks like it's set for Sunday 20-Jan 12:00 PM UTC, which is Sunday 20-Jan 8:00 PM CST (China Standard Time).

... Start shipping a Sunday at 8pm... really?

Maybe it's business as usual in China on Sundays?  I guess I don't know, myself.

I do know that DHL Express will provide Sunday delivery in the US, by request.

The Chinese Post Office is open 7 days a week.

Not sure if this truck that's being unloaded is of packages arriving into or out of China, but... http://www.youtube.com/watch?v=0ztBF9NuaSY


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: repentance on January 19, 2013, 03:44:58 AM
Transport and logistics is a 24/7 industry.  Their consignment may be collected or they may be dropping it off themselves.  I wouldn't worry about the Sunday thing - the real question is how long it's going to take from the time the packages are scanned into the transport company's system until they start being delivered to their final destinations and that will likely vary as customs clearance times always seem to be something of a lottery.  Tracking information also seems to be extremely hit and miss, so I guess there are going to be many nervous moments until the first customer confirms that they've received their ASIC.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 19, 2013, 03:55:26 AM
Transport and logistics is a 24/7 industry.  Their consignment may be collected or they may be dropping it off themselves.  I wouldn't worry about the Sunday thing - the real question is how long it's going to take from the time the packages are scanned into the transport company's system until they start being delivered to their final destinations and that will likely vary as customs clearance times always seem to be something of a lottery.  Tracking information also seems to be extremely hit and miss, so I guess there are going to be many nervous moments until the first customer confirms that they've received their ASIC.

DHL Express is special in that for many countries they have Customs agents for the destination country actually on the planes, clearing the cargo as it's en route.

That's one way they're able to be so awesomely fast.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: repentance on January 19, 2013, 04:56:38 AM

DHL Express is special in that for many countries they have Customs agents for the destination country actually on the planes, clearing the cargo as it's en route.

That's one way they're able to be so awesomely fast.

Yeah, I've found in the past when shipping shit that some companies really have their shit together when it comes to customs stuff and others don't.  I've also found that sometimes it's better to take your stuff to the airport yourself so that you're there when your consignment gets scanned in than to have it picked up (because if it's picked up you have no control over when it gets processed and can't double check the paperwork and fix errors before it actually gets put on a plane).


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: nathanrees19 on January 19, 2013, 05:02:20 AM
For those that cant seem to get past his Reality Distortion Field, here is the proof.
https://github.com/luke-jr/bfgminer/commit/b9df56511c7bd1a2e1f075e9c184c1a4b0f1ba20

Edit: and more of his wiki editing trying to edit CGMiner out of existance.
https://en.bitcoin.it/w/index.php?title=P2Pool&action=historysubmit&diff=31023&oldid=30982

Quote from: Luke-jr
cgminer is pretty much deprecated at this point

:/


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: kano on January 19, 2013, 07:54:45 AM
For those that cant seem to get past his Reality Distortion Field, here is the proof.
https://github.com/luke-jr/bfgminer/commit/b9df56511c7bd1a2e1f075e9c184c1a4b0f1ba20

Edit: and more of his wiki editing trying to edit CGMiner out of existance.
https://en.bitcoin.it/w/index.php?title=P2Pool&action=historysubmit&diff=31023&oldid=30982

Quote from: Luke-jr
cgminer is pretty much deprecated at this point

:/
Just ignore Jesus, he puts his personal whacked out opinions all over the Bitcoin wiki - the wiki is a joke and not worth taking much notice of any page that has his name on any changes.
To be blunt, the Bitcoin wiki is a joke and bad publicity for Bitcoin - and the fools who run it don't seem to care either.

Anyway, I've recently written a new full USB cgminer interface that uses libusb and implemented MMQ FPGA and BFL FPGA on that.
Not the old outdated serial-USB code that the old backward Jesus clone uses.
Direct USB has a bunch of advantages already (and it's ready for the new ASIC devices)

Though, it is a pity that a crap decision by Jesus to use the crappy serial-USB ~a year ago has lead to the ASIC devices still restricting their performance to suit that silly choice ...

Once the version one ASIC devices are released, I might then contact the manufacturers, that actually succeed in releasing an ASIC, about upgrading their MCU hardware out of the 1900s serial I/O to the more advanced USB I/O and get some very likely performance boosts due to that ...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: king_pin on January 19, 2013, 09:08:44 AM
Hey, are we going to start betting on what their excuse for not shipping will be?
I say that the hand of god intervened and they, are as frustrated as we are of the delay but we need to wait just 3 more weeks. :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: hope2907 on January 19, 2013, 10:09:19 AM
one day left, as least they should give us even one picture of warehouse with full of asic product


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 19, 2013, 03:17:20 PM
one day left, as least they should give us even one picture of warehouse with full of asic product

expect a surprise tomorrow in every case: delay or delivery...  ;D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Vicus on January 19, 2013, 03:38:36 PM
One thing is bothering me. If Avalon will ship to me via DHL, this is will be total fail because of reasons, I explained before.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: king_pin on January 19, 2013, 04:07:04 PM
expect a surprise tomorrow in every case: delay or delivery...  ;D
If it is Delay, It won't be much of a surprise, but I will be extremely surprised if it is delivery. :)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bogart on January 19, 2013, 05:50:05 PM
One thing is bothering me. If Avalon will ship to me via DHL, this is will be total fail because of reasons, I explained before.

I believe you can request shipping via EMS instead.  Send Yifu an email.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 19, 2013, 06:15:04 PM
will the website avalon-asic.com (http://avalon-asic.com) explode if the countdown is finished??  ;D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Vicus on January 19, 2013, 06:16:14 PM
One thing is bothering me. If Avalon will ship to me via DHL, this is will be total fail because of reasons, I explained before.

I believe you can request shipping via EMS instead.  Send Yifu an email.
Just did that by PM at this forum and support ticket at support.avalon-asic.com. Hope this will be enough.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: BitSyncom on January 19, 2013, 06:17:26 PM
One thing is bothering me. If Avalon will ship to me via DHL, this is will be total fail because of reasons, I explained before.

I believe you can request shipping via EMS instead.  Send Yifu an email.
Just did that by PM at this forum and support ticket at support.avalon-asic.com. Hope this will be enough.

correct, I am making form for people to choose right now, should be ready in a few hours.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 19, 2013, 06:20:02 PM
aha! http://support.avalon-asic.com/solution/categories/40996/folders/66201/articles/31066-when-are-the-avalon-asics-shipping- (http://support.avalon-asic.com/solution/categories/40996/folders/66201/articles/31066-when-are-the-avalon-asics-shipping-)

Quote
The projected shipping date is Jan 14th, our conservative estimate on our shipping capacity is 300 units in two weeks, this number is set to increase once the process gets more streamlined.

In addition, we have a promise to ship out all of the first 300 units before the end of February 2013.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: melmo on January 19, 2013, 07:18:18 PM
I still have received no communication from Avalon about this and my paid order is still listed as cancelled.  I'm getting concerned as the shipping date is very near, and I believe there are other customers with the same problem as well.

I'm in the same boat.  I've PM'ed, emailed and opened a support ticket, but haven't received any response.  I'm very disappointed and surprised by Avalon's lack of response.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: myrond on January 19, 2013, 07:39:12 PM
One thing is bothering me. If Avalon will ship to me via DHL, this is will be total fail because of reasons, I explained before.

I'm not sure what that is.  I also am outside of DHL (no service at all).  What I receive items via DHL it goes to a city about 600 miles away.   Then DHL re-ships the original piece of the local mail system to the destination.  I have seen two different carriers used to re-ship packages.

The tracking information comes up and says, "delivery arrangements have been made" as that last item in tracking website.

I looked through your post history and I could not find a reason why DHL can't mail to you.

Have you ever had a failure of DHL to deliver to your location?

As far as customs, you should have less problems with DHL.  I suppose different countries could be different depending upon who is bribed.  But maybe next time DHL has greased the proper palms.  (you should hope)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazyates on January 19, 2013, 08:38:24 PM
Ignorant Ramblings
Normally I don't mind your useless posts as much as everyone else, but it wasn't funny the first time you posted that in the other thread, and it's not funny here this time either.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bcpokey on January 19, 2013, 09:21:25 PM
Ignorant Ramblings
Normally I don't mind your useless posts as much as everyone else, but it wasn't funny the first time you posted that in the other thread, and it's not funny here this time either.

Indeed.

I've never used the ignore button on this forum, for anyone, as I have an ignore button in my head, and occasionally even the worst people say something interesting, but this person is really making me reconsider. Weren't they banned at one point? What happened to that?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 20, 2013, 01:36:31 AM
@ Mods

Could you Ban MeSarah? I think the sentiment is clear that they provide nothing worth the electrons on the screen.

Or better yet, just Ban them for another 30 days. Make them wait for the next post!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: poon-TANG on January 20, 2013, 02:39:01 AM
@ Mods

Could you Ban MeSarah? I think the sentiment is clear that they provide nothing worth the electrons on the screen.

Or better yet, just Ban them for another 30 days. Make them wait for the next post!


LOL ....  this coming from the biggest troll on any BFL thread. Toooo funny


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Vicus on January 20, 2013, 03:21:51 AM
One thing is bothering me. If Avalon will ship to me via DHL, this is will be total fail because of reasons, I explained before.

I'm not sure what that is.  I also am outside of DHL (no service at all).  What I receive items via DHL it goes to a city about 600 miles away.   Then DHL re-ships the original piece of the local mail system to the destination.  I have seen two different carriers used to re-ship packages.

The tracking information comes up and says, "delivery arrangements have been made" as that last item in tracking website.

I looked through your post history and I could not find a reason why DHL can't mail to you.

Have you ever had a failure of DHL to deliver to your location?

As far as customs, you should have less problems with DHL.  I suppose different countries could be different depending upon who is bribed.  But maybe next time DHL has greased the proper palms.  (you should hope)

update.

Shipping. We at Avalon understands the some what unreliableness of EMS in certain countries, to address this issue, all existing and future orders will be shipped out via DHL at no additional charge. This will ensure timely delivery of our products.
For Russia DHL is absolutely unacceptable.
1. DHL doesn't deliver the goods to Russia for individuals. The exception is made for some online shops which have the direct contract relations with DHL.
2. For DHL of 30% duty is raised, if cost (including delivery cost) of the goods exceeds 200 euro/month. For EMS this threshold is 1000 euro/month (tax = 0.3 * (cost - threshold)).
3. Procedure of customs cleaning is more difficult for DHL and offen demands services of the customs broker. In case of EMS customs cleaning is strongly simplified.

I understand that EMS can deliver the goods not so quickly, but DHL this bigger evil for Russia.

Please take in account that info, when you will be shipping in Russia.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: repentance on January 20, 2013, 03:30:05 AM
One thing is bothering me. If Avalon will ship to me via DHL, this is will be total fail because of reasons, I explained before.

I'm not sure what that is.  I also am outside of DHL (no service at all).  What I receive items via DHL it goes to a city about 600 miles away.   Then DHL re-ships the original piece of the local mail system to the destination.  I have seen two different carriers used to re-ship packages.

The tracking information comes up and says, "delivery arrangements have been made" as that last item in tracking website.

I looked through your post history and I could not find a reason why DHL can't mail to you.

Have you ever had a failure of DHL to deliver to your location?

As far as customs, you should have less problems with DHL.  I suppose different countries could be different depending upon who is bribed.  But maybe next time DHL has greased the proper palms.  (you should hope)

update.

Shipping. We at Avalon understands the some what unreliableness of EMS in certain countries, to address this issue, all existing and future orders will be shipped out via DHL at no additional charge. This will ensure timely delivery of our products.
For Russia DHL is absolutely unacceptable.
1. DHL doesn't deliver the goods to Russia for individuals. The exception is made for some online shops which have the direct contract relations with DHL.
2. For DHL of 30% duty is raised, if cost (including delivery cost) of the goods exceeds 200 euro/month. For EMS this threshold is 1000 euro/month (tax = 0.3 * (cost - threshold)).
3. Procedure of customs cleaning is more difficult for DHL and offen demands services of the customs broker. In case of EMS customs cleaning is strongly simplified.

I understand that EMS can deliver the goods not so quickly, but DHL this bigger evil for Russia.

Please take in account that info, when you will be shipping in Russia.

They already posted earlier today that they'll be putting up a form for people to select alternative shipping options.

Bear in mind that it a lot of countries final delivery is handed off to a local service once the goods have cleared customs and not done by DHL itself.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: 420 on January 20, 2013, 10:42:49 AM
When was the last statement from Aavalon; what did they say?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: beekeeper on January 20, 2013, 10:44:11 AM
When was the last statement from Aavalon; what did they say?
I think someone posted a screenshot from a discussion with one of their guys in a messenger window.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bicknellski on January 20, 2013, 12:14:40 PM
45:45 to go before they ship.... cool.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 20, 2013, 12:22:27 PM
35mins to go.... ;D :o 8)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 20, 2013, 12:26:17 PM
they will ship, definitely! soon or later...  ;D


So, I put that here :)

http://puu.sh/1OQYs

<ironic>sounds trustworthy to me!</ironic>

http://i47.tinypic.com/2r45uhc.jpg




Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bicknellski on January 20, 2013, 12:36:44 PM
23 minutes and counting.... (nasa sounds in the background)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: rchapoteau on January 20, 2013, 12:41:46 PM
18 minutes. 

Any speculation as to whats going to happen on the site when it goes to 0?  Will it just sit there, or do you think it will automatically change the page to something interesting.  Maybe pics of the product or something.



Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: demkd on January 20, 2013, 12:46:33 PM
Adjust time on your computer and see by yourself  ;)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 20, 2013, 12:50:31 PM
T Minus Ten Minutes.

All looks good for go.

----------------------------

http://i46.tinypic.com/149tjea.gif


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 20, 2013, 12:52:14 PM
18 minutes. 

Any speculation as to whats going to happen on the site when it goes to 0?  Will it just sit there, or do you think it will automatically change the page to something interesting.  Maybe pics of the product or something.



this!

http://www.youtube.com/watch?v=Ejq-Xu0jM_E (http://www.youtube.com/watch?v=Ejq-Xu0jM_E)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: PuertoLibre on January 20, 2013, 12:54:44 PM
Nah, it will just go to zero and then negative. It's always done that in the past.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bicknellski on January 20, 2013, 12:56:43 PM
3 minutes... and counting!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: cedivad on January 20, 2013, 12:57:32 PM
http://www.reactiongifs.com/wp-content/uploads/2011/05/tumblr_ljh0puClWT1qfkt17.gif


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Frequency on January 20, 2013, 12:59:02 PM
1 minute 2 go....


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 20, 2013, 12:59:33 PM
10 seconds...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bicknellski on January 20, 2013, 12:59:43 PM
10....


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mezzomix on January 20, 2013, 12:59:56 PM
They ship, they ship ... not.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: itsgoldbaby on January 20, 2013, 01:00:06 PM
Nah, it will just go to zero and then negative. It's always done that in the past.
....and you're right...


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 20, 2013, 01:00:10 PM
BAH WAHHHHHHH  ;D ;D ;D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: chriswilmer on January 20, 2013, 01:00:28 PM
Well played Avalon. Well played.
http://i.imgur.com/wSpnQ2U.jpg


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: rchapoteau on January 20, 2013, 01:00:45 PM
Holy crap I didn't see that coming!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bicknellski on January 20, 2013, 01:00:51 PM
Yawn.... now what am I going to do for the rest of the evening.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mezzomix on January 20, 2013, 01:01:52 PM
Yawn.... now what am I going to do for the rest of the evening.

Wait for your parcel to arrive ... ;D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: rchapoteau on January 20, 2013, 01:02:19 PM
The programming of the countdown clock on their website makes me wonder about some of their technical skills . . .


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazy_rabbit on January 20, 2013, 01:05:14 PM
And the groans of a thousand bitcoins rang out into the universe.

WHY AVALON WHY!?!?!? YOU HAD TWO TASKS- 1) MAKE ASICS 2)MAKE A COUNTDOWN TIMER.

ARUGH!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: bumbox on January 20, 2013, 01:05:51 PM
The programming of the countdown clock on their website makes me wonder about some of their technical skills . . .

Well, indeed they used a ready made template, LOL
http://themeforest.net/item/donner-under-construction-page/2735992


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Bicknellski on January 20, 2013, 01:06:38 PM
The programming of the countdown clock on their website makes me wonder about some of their technical skills . . .

LOL I never ordered anything from anyone... I was just entertained by the countdown clock. Like many others I will wait to see if people actually get one and then check if it makes sense to even order from Avalon or BFL or even bASIC. I am definitely not the early adopter type.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: turboNOMAD on January 20, 2013, 01:07:03 PM

Quote
   -1 DAYS   
    --   
    -1 HOURS   
    --   
    -6 MINUTES   
    --   
    -19 SECONDS   

WTF?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazy_rabbit on January 20, 2013, 01:07:47 PM
Its burns! it burns! Seriously!!!!! WTF?!?!?!


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mezzomix on January 20, 2013, 01:08:00 PM
At least, the whole thing was entertaining. I think the entertainment was worth the pre-order money used to create an ASIC (A System Information Counter).


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: DobZombie on January 20, 2013, 01:08:12 PM
http://i.imgur.com/7LzBTov.jpg (http://imgur.com/7LzBTov)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Frequency on January 20, 2013, 01:09:42 PM
At least, the whole thing was entertaining. I think the entertainment was worth the pre-order money used to create an ASIC (A System Information Counter).


lol  :D


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: mezzomix on January 20, 2013, 01:10:10 PM
LOL I never ordered anything from anyone... I was just entertained by the countdown clock. Like many others I will wait to see if people actually get one and then check if it makes sense to even order from Avalon or BFL or even bASIC. I am definitely not the early adopter type.

But it is much more thrilling if you lose a significant amount of money when playing the game.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: crazy_rabbit on January 20, 2013, 01:10:35 PM
ASIC

A Splendid International Con


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Maniac on January 20, 2013, 01:11:06 PM
Are they took the bag with the money and hid on an island in the Pacific Ocean?


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: MPOE-PR on January 20, 2013, 01:11:58 PM

Quoted for lolz value.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: DobZombie on January 20, 2013, 01:12:35 PM
ASIC

A Splendid International Con

ASIC

Another Screwed It Concurrently


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: Gyrsur on January 20, 2013, 01:13:17 PM
https://bitcointalk.org/index.php?topic=137534.0;topicseen (https://bitcointalk.org/index.php?topic=137534.0;topicseen)


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: organofcorti on January 20, 2013, 01:14:37 PM
Are your complaints that the countdown timer went negative (which was expected) or is a day out (indicating shipping started a day ago? I can't tell from the posts; informative content from posters is as low as emotional content is high.


Title: Re: [Announcement] Avalon ASIC Development Status [Batch #1]
Post by: John (John K.) on January 20, 2013, 01:15:30 PM
Locking the thread by request from OP.