Bitcoin Forum

I'm new to BTC and FPGA. I see lots of discussion and lots of good-intended vaporware. I see the real thing too in ztex,icarus,x6500,bfl. (I miss any?)

But has anyone actually talked with a company that is in the business of creating FPGA designs and products?
I know there are some companies that take FPGA designs and automate the FPGA design to an ASIC product.

I may look into it just for the experience and see what happens. I'm sure some of you here already know where this will take me so chime in.

I envision getting some quotes, settling on one and then crowd funding for that.
Part of the request for the quote will require that the entire design be free (as-in freedom). Will that change the price?

Has it been tried already?

[UPDATES]
Wed Mar 21, 2012 I have sent out three requests in the past week or so. No replies yet.

A full custom ASIC at current gate lengths (28 nm, 35 nm, 40 nm, 45 nm) is now several million.

I actually asked a buddy of mine who works as an ASIC designer here in Silicon Valley whether we could just slap Stefan's Verilog code into his Synopsis or Cadence workstation at work, and I'll pay the 25 grand for a multi-project wafer somewhere, and his answer was, yes, he could certainly compile the Verilog code into RTL, and maybe even simulate the RTL, but there's much more to an ASIC than that, for instance the physical layout and physical verification, which he cannot do by himself. Now, if I had two friends at that particular Silicon Valley company, one a Verilog/RTL guy and the other one a physical design guy, maybe it would be possible to "moonlight" this over the course of several months...

But I don't and it isn't.

Hrmf, too bad.

Ok so an ASIC seems to be out of the question as of now. But what about just an FPGA design?

The best hope now seems to be EldenTyrell, who has managed to fit three instances of SHA-256 (single SHA, not double SHA) into a Spartan6-150, however he wants to be compensated at market rates for his (admittedly brilliant) work, and thus it is unclear whether his bitstream will ever become publicly available.

Then there is wondermine, who certainly does not lack youthful exuberance and enthusiasm and maybe he can duplicate EldenTyrell's work and put it in the public domain.

If none of them comes through, it looks like we are stuck at 210 MH/s (Stefan == ZTEX).

As the topic of this thread is about contracting out the design, I was asking what that would cost for an FPGA from a real company.
i.e. don't take it all the way to an ASIC

I am collecting a list of vendors and will see.

Why? They will just try to sell you a low performance, tightly-rolled design. No need to reinvent the wheel.

If you could add another zero to that sum, you might want to look at doing an altera hardcopy. Its the logical next step after FPGA; significant power consumption and (given enough volume) cost advantages, without the excessive NRE of a full custom asic. Should also be much easier to develop, if you have a working FPGA implementation, and a bundle of cash, you have all you need.

How much would going from Spartan 6 to Altera Hardcopy (and then to a board that actually plugs in to a USB port) be? And whats the estimated time to have these bad boys delivered to your door step?

Infinite. :)

Spartan = xilinx FPGA
Altera Hardcopy = Altera sASIC.

You would need a competitive FPGA using an Altera chip and not just any chip a chip that they have a HardCopy equivelent for.

Altera "Spartan equivelent" is the Cyclone and there is no path to HardCopy from a Cyclone.  You would need a Stratix family chip (and they start @ $4K ea).

That's what I meant. We have "code" for Spartan 6, of course you "port" that on an Altera device first before you go the Altera route. And with "put" I don't necessarily mean upload and change a few lines ;)

$4k/each doesn't sound so bad, I suppose you only need one or two to create the prototypes and mine for a while to get them stable.

I would still be interested in the estimated price and lead time.

The first step would be getting an efficient design on a Stratix IV series chip.  There isn't much porting.  Bitstreams are very device specific.  You can get started in this stage for $10K plus an experienced FPGA engineer.

If/when you have an efficient design on a Stratix IV series chip lead time for a HardCopy is about 3-4 months and capital requirements will be in the $200K+ range.

It reamains to be seen if a HardCopy IV chip will be competitive on a MH/$ basis though.  A lot depends on how many MH/S you can get out of a Stratix.  Since Stratix is a dead end (nobody is going to be buying $5K miners which get <1 GH/s) unless you use it as a stepping stone to HardCopy a lot remains unknown (and thus risky).

Thanks a lot, you are really very knowledgeable in this field. Just out of curiosity, did you learn this through Bitcoin and mining, or is this some knowledge you acquired unrelated to Bitcoins?

Unrelated to Bitcoin.  At one time I worked for Juniper networks.  Some of the high end products use FPGAs and sASICs because volume is too low to make using ASICs cost effective.  I didn't do any FPGA programming BTW. 

@DandT.  Did you read that Cisco will be temporarily sourcing off the shelf silicon due to the pickle they have found themselves in with fractured product lines.  Lulz.  They don't know which front to fight on and with  what. ;)

(sorry for hi-jack)

I hadn't heard but after how they destroyed the awesome Linksys brand I can't say it makes me sad.  Hopefully CISCO can de-frak themselves and their product lines.  I mean it isn't rocket science and gross margins are 50%+.  How exactly you end up with products which don't talk to each other when you make both of them I am not really sure.

As with most big companies bureaucracy creeps in and the company loses cohesion. The more high tech the company the worse the results.

IMO.

Actually, Juniper really has smart designs.  I mean, why else would the Federal Govt buy Juniper to span ports at major NAPs and funnel to the NSA...

:D

Most i hate about Cisco switches is that every single model has somewhat different management commands/configuration ffs! :/

Updated

do you have an educated guess as to what kind of hashrate one of those 4k chips could push?

Not enough.  

On 820K LUTs if your placement was no more efficient then Spartan-6 boards maybe 1 GH/s.  Spartan-6 is kinda hard to place though so maybe you get 50% better (50K LUTS per SHA-256 loop).  Routing is greatly improved so a 4ns critical path is plausible.  That means running the chip at 250Mhz.  Ballpark we are talking ~ 1.8GH/s.  If you could achieve 3ns critical path you might get that up to 2.4GH/s.  That is on the largest Stratix IV which runs ~$8K.  You would have a higher cost per MH/s on the smaller chips.  

That was all back of napkin guestimate.  Don't go buying $9K chips based on that. :)

The power of Stratix line comes from the ability to perfect a design on a $9K chip which can be reprogrammed at will.  Once you perfect that hypothetical 2GH/s you build a half dozen and torture test them.  $100K investment sounds like a lot but honestly it isn't compared to the huge fixed costs and large run sizes of sASICS. It allows your team to perfect the design, tweak out any PCB issues, bugs, glitches, power and cooling concerns, etc.  Catching a problem here is relatively cheap.   You can get new prototype boards with 3 day turn around for <$100.  Remember the goal isn't to be economical.  It is all about perfecting a design as quickly and cheaply as possible. 

Once you are completely satisfied with final design and your investors sign off, Alterra would "clone" that bitstream to produce a mask for etching sASICS.  The mask is going to cost you $100K+ (my number is probably dated, it might be triple that).  The good news is the sASIC of the same chips is likely less than $2K each in bulk and probably uses 33% to 50% less power. :)  Still you are looking at a minimum order of 1,000 units and 5,000 units would be more cost effective.  There is no "do over" on a sASIC. If your chips have some critical flaw which produces invalid hashes under certain conditions well you got $10M in defective chips (it happens sometimes even to Intel).  With those kind of numbers I think you can see how getting it right on a "cheap" $9K chip makes sense.

Chips like Stratix are designed to allow low cost, low risk PROTOTYPING not retail use.  Only if the market segment is so small that you could never sell more than a hundred units or so (like some high end enterprise networking devices) would you use the chip in a retail product.

gotcha, thanks.