Oh, I thought that the last two lines (212 MHz and 208 MHz) mean that everything is fine and dandy again.
I didn't see the "FPGA is shut down to prevent damage" line.
If it's shut down, why does it then have normal frequencies like 212 MHz, 216 MHz and 208 MHz again?

Anyway, this sounds like a classical RMA situation to me.

Turbor, what you see in your first log is called the "downclock of death" and people, including me, have seen this for a long time. What you see in your second log is just normal behavior.

I would like to know the WEIGHT of the mini rig.
My mining office is on the 2nd floor of a 2-story office building - there is no elevator.   

The answer to life, the universe, and everything?   

Agreed.
It could be much more than that.

With BFL's June 15th announcement looming, however, I believe that all these speculations are mostly academic and of little practical importance. FPGA miners, including the Spartan6-based miners, will soon be obsoleted by ASIC miners, just like CPU miners were obsoleted by GPU miners.
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Doh! Havnt seen a date for the announcement, in what thread/source did you find that ? Not so sure of a ASIC revolution yet, but of course it will have an impact on this quite interesting approach.
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http://www.butterflylabs.com/production-update/

"Please note:  Until we’re through initial Mini Rig shipments, you may find communications with anyone outside of customer service to be difficult.  Please be patient and reach out to Jody for the time being.  Announcements regarding abbreviated shipping schedules and future product (BitForce SC) release will be made on June 15th.  Until then we will be focusing purely on Mini Rig shipments."

Kano, each of the 3 half-miners has a decryption algorithm embedded in the first 8 rounds and an encryption algorithm embedded in the last 8 rounds. It's actually quite clear. Upon exiting the first SHA and entering the second SHA (a miner consists of 2 complete SHA256s), the encryption and the decryption cancel each other out.

I think it could be reverse-engineered quite easily -  however, the advent of ASIC-based miners would make that a (largely) futile endeavor.

Ah, I see.

Well, in that case, it would not even be necessary to remove your decryption algorithm from the first 8 stages.
It would only be necessary to reverse-engineer it.

Upon reverse engineering this 8-stage decryption algorithm, one could then pre-encrypt the pool vectors in software, so that they, upon decryption, form a valid input vector.

Previously, you had alleged that changing [LUTs and] routes/lines would be needed to "break" this protection.
Nonsense.
Judging from your recent post, that seems completely unnecessary.

The encryption of the golden nonce could be broken in a similar way, without changing LUTs, without rerouting connections:
One could merely undo it in software.

One cannot modify the 512 input bits of the SHA-256 algorithm, because otherwise nonce-detection would be impossible. A golden nonce would still be computed, but it would be a meaningless golden nonce.

I realize, however, that one can add some pseudorandom bits, which may or may not be a crypto hash of some or all of the 512 legitimate input bits, to the input bits, and thus "extend" SHA-256 with respect to its WIDTH.

In an unmodified SHA-256, what percolates down the 64 stages are 512 bits of w and 256 bits of ABCDEFGH.
By adding a few bits (how many bits has not been disclosed, but this will be trivial to find out) to these 768 bits, one can "extend" SHA-256 without messing it up. In other words, a kind of mini-SHA can be run along the full-fledged SHA, keeping the full-fledged SHA intact.
Similarly, for the second SHA iteration.

Then, at the end of the 2nd iteration, the pseudorandom result of the mini-SHA can be used to encrypt the golden nonce, making it unsuitable for direct submission to a pool, requiring submission to the ET-owned server farm instead.
At the ET-owned server farm, the quite-trivially-but-still-sufficiently-encrypted nonce is quickly decrypted, and 95% of these nonces are then returned to the miner, while 5% are retained by ET.

So, in other words, while I don't believe ET is adding any STAGES to the double-SHA, not even one, as that would directly impact the hash rate, I now think he's running a "mini-SHA" alongside both stages of the double-SHA. Maybe 16 bits wide. Maybe 32 bits wide. Maybe only 8 bits wide, partly relying on security-through-obscurity.

While undoubtedly ingenious, such an approach would needlessly increase the power consumption of the FPGA, which is already hitting various limits, mostly thermal ones, but in the ZTEX case also an Amp limit.

With BFL's June 15th announcement looming, however, I believe that all these speculations are mostly academic and of little practical importance. FPGA miners, including the Spartan6-based miners, will soon be obsoleted by ASIC miners, just like CPU miners were obsoleted by GPU miners.

Crickets chirping.
A ball of tumbleweed slowly rolls down Main Street.

Look guys - BFL are really busy this week and next week trying to ship the first batch of mini rigs.

Can you please show some consideration and muster some constraint, and postpone this time-consuming show-and-tell thing until after the the first batch of the mini rigs has been shipped?

Thank you.

Word on the street is, they are waiting for the enclosures.

By the way, I don't believe that EldenTyrell modifies the INPUT of the double-SHA.
Changing even one input bit will change all output bits in a non-trivial, seemingly stochastic, way.
After all, this is the very idea of SHA-256.

What I, however, do believe, is: Once a "golden nonce" has been found, he encrypts it. Probably quite trivially,
as his professional pride would not permit him to add extra encryption stages and thus slow the miner down. Extra stages would also impact space and power consumption.

It may be some kind of fixed XOR mask, but that would be too trivial. Maybe an XOR mask that is based on the
32-bit counter or something. Maybe an adder plus an XOR mask. Something like that.

Preferably, PLATINUM certified.

A radical new idea called quality assurance.
Just a wild guess...

Sometimes it feels good to meet a person who believes in the good nature of man, even if it's just on the internet.

However, let's drop all romantic notions and let's be realistic:

They announced the trade-in program because without it, their own sales and thus their own cash flow would screech to a halt immediately after their ASIC  announcement ALONG WITH the sales and the cash flow of competitors.
Going bankrupt because you prematurely announce a better product is called the Osborne effect, because the computer company Osborne inadvertently killed itself that way.

Yes, it has. In post #84.

You'd be surprised what senior electronics engineers and senior software engineers make nowadays, and that doesn't even include QA, custumer support, marketing, sales...

Taking your numbers, they're losing money, not making money.

I don't think that since BFL's ASIC announcement any of the FPGA guys is laughing anymore.
Case in point: Bitfury sounded outright, well, furious in his attacks against BFL...

Exactly my thinking.

The message It is finally here! is displayed on the screen, but, except for a link to this thread, nothing else.
No image. No clickable link. No order page. No info page. Nothing.