1. Host board will be a two board solution ( SOM & Daughter board).
SOM - system on a module(little tiny computer), daughter card is a secondary PCB attached to the SOM through a connector or cable likely containing the ASIC and accompanying devices.
2. Wifi capability has been added to the host board.
Wifi! no cables!
3. Power measurement capability added to the host board.
Web interface and/or front display will likely report out active power usage.
4. Temperature measurement capability added to the mining board.
Web interface and/or front display will likely report out active temperature levels.
5. ASIC – Physical design is going on:
1. Memory cells are chosen as array of 1024*128 bits.
Physical dimension/structure of the memory blocks
2. Various options for memory floor planning is being tried upon like multiple memories being stacked on top of each other along with grouping them together for better die size.
Puzzle piecing the memory partitions to try and optimize die size... smaller the die, more per wafer, cheaper the chip.
6. RTL synthesis has been tried out with HVT , RVT and LVT cells. LVT offers good frequency, however power leakage is higher, RVT offers balance on timing and power.
ASIC standard cell types, High vT, Low vT, Regular/Standard vT... used depending on situation, its a Speed vs Power dissipation thing. vT = Threshold voltage, this is threshold at which a transistor turns on/off. A Low vT turns on and off faster but comes with increased leakage, the opposite for High vT. Think of an HVT device like a sprinter starting in a standing position(when idle its easy to stay standing, but slow to start) and an LVT device like a sprinter starting low in the starting blocks (when idle, the starting stance requires allot of effort to maintain, but a fast start).
7. Block level pin assignments in progress.
Pin assignments are the ports, connection points to the various design partitions (collections of logic that perform a specific task)... its a hardware equivalent of a "function" in programming and the ports represent the input/output of those functions. When talking full chip those ports correspond to the physical pins/solder balls on the package.
8. DFT Scan insertion in progress.
This is a built in test methodology for post silicon validation(testing the die for defects). DFT = Design For Test. I would assume along these lines that basic I/O test logic and mbist test logic is being implemented as well... especially mbist, as i'm sure the die area consumed by the memory is a big percentage as compared to the random logic (that scan covers).
9. Place and route in progress.Assuming the place and route for the asic and not the PCB... but means the same thing... the die is being automatically synthesized based on the design, a process of placing standard cells (and/Or/Nand/Nor/Latch/Inverter...etc) and generating the electrical connection paths between them.
Credits to Phidian from Litecointalk.org Forum for the technical breakdown.
Show Posts
