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Today I was able to get the Enterpoint cairnsmore to work with the tricone mining software without needing an isolated stand-alone cable, just the FTDI link. The code is still early in function, and still suffers from some JTAG errors likely due to noise / reflections on the lines which will need better error handling. I only performed several tests, but was easily able to get stable function with three rings at 100Mhz. (150 Mh/s). I will keep you guys updated, I should have more time to work on it on Tuesday. Here's some brief logs from submitted shares, it's fairly garbled from the ascii formatting for the colors. [cairnsmore:1:0.1 ] [32m pool accepted share[0m ...
nice one! But only with one fpga? What OS you use? If windows then please can you provide the patched urjtag prog.? The code of tml would be also nice. All 4 FPGAs work, just a testing run post. I'm doing it under linux, but it should work fine under Win32/Mac/Linux. The code actually doesn't use urjtag, but just the modified tml code and FTDI driver. It should be much more useful once the JTAG issues are hammered out. Chris
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Today I was able to get the Enterpoint cairnsmore to work with the tricone mining software without needing an isolated stand-alone cable, just the FTDI link. The code is still early in function, and still suffers from some JTAG errors likely due to noise / reflections on the lines which will need better error handling. I only performed several tests, but was easily able to get stable function with three rings at 100Mhz. (150 Mh/s). I will keep you guys updated, I should have more time to work on it on Tuesday. Here's some brief logs from submitted shares, it's fairly garbled from the ascii formatting for the colors. [cairnsmore:1:0.1 ] [32m pool accepted share[0m
H:[1m[32m0[0m[0m/[32m0[0m[32m,[0m[32m0[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m38s | H:[1m[32m0[0m[0m/[32m0[0m[32m,[0m[32m0[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m0[0m R:[33m0[0m T:3m38s H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m40s | H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m1[0m R:[33m0[0m T:3m41s requesting name
[cairnsmore:1:0.1 ] decrypting nonce at address 0x000000b8
H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m40s | H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m1[0m R:[33m0[0m T:3m41s requesting name
[cairnsmore:1:0.1 ] encrypted nonce = 0x0d210e79
H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m40s | H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m1[0m R:[33m0[0m T:3m41s H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m42s | H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m1[0m R:[33m0[0m T:3m43s requesting name
[cairnsmore:1:0.1 ] found a share: 0xe16ddf30
H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m42s | H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m1[0m R:[33m0[0m T:3m43s requesting name
[cairnsmore:1:0.1 ] [32m pool accepted share[0m
H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m42s | H:[1m[32m19[0m[0m/[32m0[0m[32m,[0m[32m19[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m1[0m R:[33m0[0m T:3m43s H:[1m[32m38[0m[0m/[32m0[0m[32m,[0m[32m38[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m44s | H:[1m[32m38[0m[0m/[32m0[0m[32m,[0m[32m38[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:3m45s H:[1m[32m37[0m[0m/[32m0[0m[32m,[0m[32m37[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m46s | H:[1m[32m37[0m[0m/[32m0[0m[32m,[0m[32m37[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:3m47s H:[1m[32m37[0m[0m/[32m0[0m[32m,[0m[32m37[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m49s | H:[1m[32m37[0m[0m/[32m0[0m[32m,[0m[32m37[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:3m49s H:[1m[32m37[0m[0m/[32m0[0m[32m,[0m[32m37[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m51s | H:[1m[32m37[0m[0m/[32m0[0m[32m,[0m[32m37[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:3m51s H:[1m[32m36[0m[0m/[32m0[0m[32m,[0m[32m36[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m53s | H:[1m[32m36[0m[0m/[32m0[0m[32m,[0m[32m36[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:3m53s H:[1m[32m36[0m[0m/[32m0[0m[32m,[0m[32m36[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m55s | H:[1m[32m36[0m[0m/[32m0[0m[32m,[0m[32m36[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:3m55s H:[1m[32m36[0m[0m/[32m0[0m[32m,[0m[32m36[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m57s | H:[1m[32m36[0m[0m/[32m0[0m[32m,[0m[32m36[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:3m58s H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m59s | H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:4m requesting name requesting name
[34m[cairnsmore:1:0.1 ] prediction: optimalFreq=229mhz, errorrate=40%, hashrate=67MH/s, alpha=0.329 beta=5.887 gamma=-5601.734[0m
H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m59s | H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:4m requesting name
[cairnsmore:1:0.1 ] setting clock to 65 Mhz, mult=13 div=10
H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m59s | H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:4m requesting name
[cairnsmore:1:0.1 ] ramping clock: mult=13 div=10
H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m59s | H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:4m requesting name requesting name
[cairnsmore:1:0.2 ] setting clock to 60 Mhz, mult=6 div=5
H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m59s | H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:4m requesting name
[cairnsmore:1:0.2 ] ramping clock: mult=6 div=5
H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m X:87 C:60,60,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:3m59s | H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:4m H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m X:90 C:60,65,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:4m2s | H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:4m2s requesting name
[cairnsmore:1:0.1 ] decrypting nonce at address 0x0000005c
H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m X:90 C:60,65,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:4m2s | H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:4m2s requesting name
[cairnsmore:1:0.1 ] encrypted nonce = 0x9a6c87ca
H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m X:90 C:60,65,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:4m2s | H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:4m2s H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m X:90 C:60,65,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:4m4s | H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:4m4s requesting name
[cairnsmore:1:0.1 ] found a share: 0x615b9649
H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m X:90 C:60,65,55 E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m T:4m4s | H:[1m[32m35[0m[0m/[32m0[0m[32m,[0m[32m35[0m[32m,[0m[32m0[0m E:[1m[31m0[0m[0m/[31m0[0m[31m,[0m[31m0[0m[31m,[0m[31m0[0m A:[32m2[0m R:[33m0[0m T:4m4s requesting name
[cairnsmore:1:0.1 ] [32m pool accepted share[0m
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As far as I understand it you can use a programming cable to run ET bitstream already and there is even a chance our front end might just work anyway. Urjtag has support for a FT2232 a very close relative of the FT4232 we use on Cairnsmore1. Which cable do I need? Your prog3 cable? Is it supported by urjtag? We have not proven either hardware with urjtag. Our Prog3 is a Xilinx cable clone and in theory would work urjtag as Xilinx cable is on the support list. That said there are a range of Xilinx cables and it is possible our clone is one not supported. We know Prog3 works fully with Xilinx tools and that has always been our benchmark. The in-built FT4232 on Cairnsmore1 is a big brother version of the FT2232 that is on the urjtag support list. It has the same JTAG processing features so that is why it might work. I've had significant problems attempting to run it with the built-in 4232. Could possibly be related to the (undocumented) DIP switch functions / settings. If enterpoint would only publish a schematic, or even a .ucf for their board, we could happily have native support in no time. Yohan: Please release a pinout or ucf file for your board, I will happily write the java interface. Chris
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hi eldentyrell,
i have tried the last TML version on cairnsmore1 with the following result with the buildin usb to jtag FTDI chip FT4232:
Do you know what's wrong here? jtag connect to the cable and "idcode" shows 4x XC6SLX150 FPGAs. It also look's like successfully patched with the "tdo" command.
Can you help here?
Thank you!
eb
I've had similar problems attempting to run it with the built-in 4232. Could possibly be related to the undocumented DIP switch functions. If enterpoint would only publish a schematic, or even a .ucf for their board, we could happily have native support in no time. Yohan: Please release a pinout or ucf file for your board, I will happily write the java interface. Chris
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Attempted the new bitstream and java jar on enterpoint. Able to program the bitstream, however, clock detection fails. It will the majority of the time detect erratic results on the CSG package pin L22 and often not continue to the J1 detection. K20 doesn't seem to be an issue and reliably detects 0. Then when detecting the J1 pin should it get that far, the results are quite unreliable.
Chris, you'll need to be more specific than that. Please post a log file for each of these behaviors. Both runs completed back to back. Input clock should be 50 mhz on cairnsmore pin.
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TML-0.999 is posted.Please upgrade if you care about performance; all previous versions have a serious performance bug that causes valid shares to silently be "lost". The number of shares-per-second lost scales non-linearly with clock rate which is why I didn't notice it before. Please do not report performance numbers using anything earlier than 0.999; those numbers will be skewed low. The bug manifests itself as the hashrate (H: number) being much lower than the expected hashrate (X: number) even when the error percentage is zero -- that should never happen! Attempted the new bitstream and java jar on enterpoint. Able to program the bitstream, however, clock detection fails. It will the majority of the time detect erratic results on the CSG package pin L22 and often not continue to the J1 detection. K20 doesn't seem to be an issue and reliably detects 0. Then when detecting the J1 pin should it get that far, the results are quite unreliable. Chris
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Can you at least get 380 solid when it's running? I'm interested but I don't want to get a dud.
If the board is faulty I am certain Enterpoint will replace it at no cost to you. If not I will refund your payment in full. Received 2 days following payment, excellent transaction, board is hashing now! Thanks Pipesnake Chris
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Hello,
Please tell me which FPGA pin is used for the primary clock input and what frequency that clock input runs at.
Please email me the answer; I don't read this thread.
@eldentyrell: thanks for taking a look in here @yohan: please give eldentyrell that information! Details sent. Is it possible to have the schematics or pinout publicly documented? I'd love to use the board for some other bitstream uses and it would be greatly appreciated. Thanks, Chris
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On one page they describe a project that costs $175. But I think they all use a spartan chip.
I too was wondering if the problem can be solved by 200 $0.50 chips or something like that.
Part of the difficulty with using multiple smaller parts is the large state-size. Each iteration requires 8 32-bit integers as well as other variables. To pass >256 bytes at the goal clock rate would in general more expensive than using a larger FPGA.
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Agreed! Netbooting has a certain wow factor though
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Read times for USB flash drives are typically 10-30Mbyte/second. Mostly secondary to higher protocol overhead.
With giga-ethernet you can get 90-110Mb/sec. Under similar conditions.
Doesn't account for USB 3.0 though, haven't used it personally.
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Greeting all,
I'm Chris, got interested in bitcoin back in the 30$ haydays. Started hashing with a 4870, now upgraded to ~1.2 ghash total.
Currently working on a modular spartan-6 design (pcb and fpga design in the past) with pluggable cards. Hoping to have a standalone solution that will fit in a mini-itx form factors.
Looking forward to chatting and developing more!
Chris
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