I have found that elevating the unit about 1" so the bottom fan can work more efficiently gives me about 5 degrees cooler temps. Maybe give that a try.
Actually, I place all my singles on their pretty face, cables sticking out on top. This should allow for maximum airflow. |
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I have found that elevating the unit about 1" so the bottom fan can work more efficiently gives me about 5 degrees cooler temps. Maybe give that a try.
Be men and add some REAL fans, pussies! http://vimeo.com/41028028 Yeah, in fact one of the fans I just ordered is a 103 cfm, 61 dBA Delta fan. It's 50mm thick, so maybe you're using that as well. SVC.com has them on sale for a mere $10 - regular price is $65. |
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I think that all of your Singles are fine and the small temperature variations that you see are just that, random variations.
I also think that a brief blink every 3 minutes is not an indication of throttling, but rather an indication that the device has found a match or that it is being provided with a new work unit.
Yeah, I guess I'm ahead of time. Assumed people already started tweaking it to push it to the max (like done with GPUs), but I guess most are just happy with it as a plug-and-mine device. As for the LED blinking, I'm pretty sure I read somewhere that a blinking front LED indicates throttling. Plus in my setup it is only the device with the lower hash rate that blinks, which I take as strong indication for throttling. What you maybe mean is the internal LED at the right side that goes off every ~5s for a short moment. I'd guess this is when the work is done and it stops for a moment to deliver shares and get fed with new work. Also, with now running for 72h continuously I'd exclude variance as a cause for 4 devices being exactly at 810 and the fifth at 65 less. I'm pretty noob when it comes to HW, but I'm tempted to disassemble (and pretty sure brick) it to see what's wrong. In think you are right, after all. Upon closer examination, one of my Singles (the first Rev. 3 Single with an external fan attached) also seems to blink. See, when BFL wrote "will blink" I was expecting it to blink continuously, but that's not what it does. It blinks for a few seconds as it throttles down to some 530 MH/s, and then, as it gradually increases its frequency again (probably in a ZTEX-like fashion) until it reaches 820 MH/s again, it does not blink, until the throttling game begins again. Placing a 133 cfm fan on top of the unit to aid the internal fan in sucking hot air out did not help at all. Neither did positioning the 133 cfm fan at one of the side vents of the throttling-afflicted Single. However, placing the 133 cfm fan at the BOTTOM of the Single, aiding the Single's external bottom fan, seems to have done the trick for me and thus I can recommend swapping the bottom fan of the Single for a higher-cfm model. Edit:  No, it still throttles. Took it quite some time; I was seeing 825 MH/s for a long time, but it's at 591 right now, already on the upslope again. 754 now. Upslope. Nevertheless, I have ordered a few fans from Silicon Valley Compucycle, all of them 65 cfm and above, and will probably open up this Single and swap out the fans. Admittedly, my mining environment is quite extreme as the central AC does not manage to replace enough hot air with cool air. |
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Good info, thanks. And I might as well ask, although no one else seems to have any info on Artix 7, do you as a large manufacturing joint have any other info? I think that is one of the most anticipated devices, although it sounds like it will be rather late.
At the X-Fest on Thursday Xilinx reps said that Artix will be available at the end of the year - however, who knows whether this is a fact or just BFL-style wishful thinking. |
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I think that all of your Singles are fine and the small temperature variations that you see are just that, random variations.
I also think that a brief blink every 3 minutes is not an indication of throttling, but rather an indication that the device has found a match or that it is being provided with a new work unit.
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I just snuck out of the X-Fest (Avnet/Xilinx seminar) to do some work in my nearby office, which doubles as my mining office. The highlights of X-Fest, as far as they are relevant for FPGA mining, are: - Artix will arrive by the end of this year - let's hope this is not a BFL-like time estimation  - like all Xilinx-7 devices, Artix requires power supply sequencing and needs at least one more voltage compared to Spartan-6 - not even ballpark pricing for Artix was available - this year, there are no discounts on eval boards or the ISE software license  - but there is a low-cost Kintex-7 eval board: The so-called Mini-Module Plus with a Kintex XC7K325T-1FFG676 for $895 - it includes a full version of ISE, which is, however, locked to Kintex XC7K325T devices - but it doesn't come with a power supply, which is $300 extra (several different vendors to choose from: TI, Maxim, GE, ST, AD) - all of these power supplies only provide 6A for VCCINT, which may or may not be enough for mining - and it doesn't include the base board, which is $500 (but not strictly required, if you wire the Mini-Module to the P/S yourself) Will I buy the Kintex Mini-Module? I'm not sure. An Artix version of the mini module will arrive "at the end of the year" and that one will be much more interesting for mining / Bitstream development. |
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Tomorrow, I will attend X-Fest, which is a complimentary all-day Xilinx seminar sponsored by Avnet, and if they have the KC705 Kintex-7 eval kit on sale at a significant discount, I'll buy it.
But this board won't make a cost-efficient miner and I neither have the time nor the gumption to try to duplicate EldenTyrell's work.
So, yeah, I'll compile a miner for that board all right, but it'll be far from optimal and will not earn the board's purchase price back.
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The best price I found is on Alibaba.com but I'm afraid about counterfeited product.
Anyone could get me in touch with a trustworthy company?
The GPU will be shipped to Thailand so if the company is in Asia it is perfect!
I can sell you 16 used ones. They all work. Send me a PM. I'm located in California & would have to get a shipping quote to Thailand. |
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$15 000 required up front. They will put you in production line when they have received your payment. No refunds.
Actually, it's $15,510 within the U.S., including shipping. Oh, thanks for the info. You forgot to mention the VAT that private customers have to pay, at least in EU. That $510 changes the whole thing. I need to make some new calculations. (dumbassfanboy) Always willing to educate where education is needed. P.S.: Why do you call yourself dumbassfanboy? Don't judge me. I would buy a whole pile of singles or two MiniRigs if they could deliver them faster. Correcting me about some $510 is just dumb especially when I was answering to someone else. When BFL gets their shipping schedule in order I while buy some(~20) singles. Well, I happen to know the exact number because I wired the $15,510 just yesterday - no need for you to get so defensive about it when someone posts the correct number. Yes, it costs more than the Largecoin mining rig, which I have also ordered. So, in case you tried to call me a BFL fanboy, that's not only juvenile, but also inaccurate: I have a ZTEX board, a double digit number of Radeon cards, [currently] four Singles mining and some more Singles on order, along with a Mini Rig Box and a Largecoin box. |
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$15 000 required up front. They will put you in production line when they have received your payment. No refunds.
Actually, it's $15,510 within the U.S., including shipping. Oh, thanks for the info. You forgot to mention the VAT that private customers have to pay, at least in EU. That $510 changes the whole thing. I need to make some new calculations. (dumbassfanboy) Always willing to educate where education is needed. P.S.: Why do you call yourself dumbassfanboy? |
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$15 000 required up front. They will put you in production line when they have received your payment. No refunds.
Actually, it's $15,510 within the U.S., including shipping. |
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I'll explain it once again:
A buddy of mine is an ASIC designer here in Silicon Valley.
When asked to implement an FPGA on a standard ASIC design flow, he could obviously do that, have some other people in his company implement and verify the physical back-end and then ship the design files off to TSMC or some other foundry.
A few months later, you receive your first sample ASIC, which implements an FPGA.
There's no secret, magic FPGA design flow at TSMC, just like there is no secret, magic source for Stratix III chips at 1/10th of the list price.
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A FPGA is a sub-category of an ASIC.
It's APPLICATION happens to be being a programmable chip.
What's so hard to understand about this?
A FPGA is not a full-custom chip because even large companies like Xilinx or Altera lack the financial resources to design full-custom chips. Not being a full-custom chip, it is an ASIC. Subcategory FPGA.
I hope this clarifies it.
No those are made up nonsense terms & definitions used by nobody except yourself. In the future if you wish to make up nonsense definitions it would be less confusing if applies them to new made up terms. Like this: A Flangerton is a sub-category of an Aderonk
It's Aderonk-ness happens to be being a pos-rogged clinkos.
What's so hard to understand about this?
A Flangerton is not a full-custom clinko because even large companies like Xilinx or Altera lack the financial resources to design full-custom clinkos. Not being a full-custom clinkos, it is an Aderonk. Subcategory Flangerton .
I hope this clarifies it.
If you tried to learn a little bit about how ASIC foundries like TSMC operate, where Xilinx and Altera and Nvidia, among others, have their chips manufactured, then you would know that each and every foundry customer has to follow a foundry-approved process to have their ASICs manufactured. These foundries are not interested all the back-and-forth that's involved in running full-custom chips through their foundries. If you own your own fab, like Intel does, different story. Don't try to cloud the issues, but educate yourself instead. |
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Calling an FPGA an ASIC defeats the entire purpose of the definition. Definitions exist for a reason.
In related new I have a miner working with quantum computing*. It's true.
* Quantum computing in this case doesn't refer to any commonly accepted definition of the word it refers HD 5970s. Definitions who needs definitions.
Calling a FPGA and ASIC is asinine. Utterly asinine. It is like deciding you are going to call floating point integer or English spanish, or the period of time when the sun is down "daytime".
FPGA = Field Programmable Gate Array
ASIC = Application SPECIFIC Integrated Circuit.
The definitions are mutually exclusive.
Even if they weren't lets boil this down. Your (accepted by nobody else on the planet) definition of an ASIC is a silicon chip? Ok genius you honestly think it is a breakthrough that we "now" know that BFL uses Silicon chips. Thanks for that clarification. Prior to that I honestly thought they built their boards out of potatoes.
A FPGA is a sub-category of an ASIC. It's APPLICATION happens to be being a programmable chip. What's so hard to understand about this? A FPGA is not a full-custom chip because even large companies like Xilinx or Altera lack the financial resources to design full-custom chips. Not being a full-custom chip, it is an ASIC. Subcategory FPGA. I hope this clarifies it. |
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Well calling a custom FGPA an ASIC kinda defeat the entire purpose of using standardized terms.
ASIC = "application-specific integrated circuit"
A customizable programmable application specific integrated circuit is kinda an oxymoron wouldn't you say?
occam's razor says it is a Stratix III FPGA (my total guess would be a EP3SL150F780) purchased at huge discount to retail price because the Stratix III is EOL.
The voltage, power draw, dimensions, pin layout, package type, voltage, and board characteristics (1MB flash loader, JTAG header, etc) all match that hypothesis.
I disagree. Everybody makes ASICs now. Almost nobody (except Intel and IBM) can afford to make a full-custom chip anymore. The full-custom chip has gone the way of the dodo. Thus, a Xilinx FPGA is an ASIC. An Altera FPGA is an ASIC. A custom BFL FPGA is an ASIC. I'd still call an Intel CPU a full-custom chip. Also an IBM Power7 CPU. AMD? Not so sure, and it shows. Oracle/SUN CPUs? More like an ASIC (manufactured by TI) than full custom. Full-custom: Optimized at the transistor level. ASIC: Run through Synopsys DC and some back-end tools, but not optimized at the transistor level. >purchased at a huge discount  In books and movies, they call that "deus ex machina", i.e. some kind of wonder or act of god to resolve a problem in the plot, like a scientist being able to stop an impending alien attack with a computer virus which he uploads to the alien mother ship. My theory does not require a deus ex machina. |
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The chip many of us guess it to be can't be purchased retail at the price point BFL is offering so the theory is that they secured are leveraging a significant discount to retail price.
As far as sASIC, Cell ASIC, Custom ASIC, etc. It doesn't fit.
MH/W is horrible (relatively speaking).
The board has a JTAG and a flash loader neither of which are used with xASIC.
It's not an ASIC built for mining, but a CONFIGURABLE ASIC, like an array processor or a custom FPGA. That's why MH/W is "horrible" - it's not a chip built specifically for mining. And yes, many, if not most ASIC designers do put a JTAG interface on the ASIC, to facilitate in-circuit testing. For instance, via JTAG one can set any output pin to any value, thus allowing early production tests, whether the chip was soldered correctly etc. |
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I didn't see any pricing on there for the chips (just for the design kit). Did you submit a quote request? What technology generation (90nm, 45nm, etc) and reticle size? In other words, any Tom, Dick and Harry may participate in a multi-project wafer run, but only publicly funded research organizations pay a mere 1100 Euros per year for the Synopsys Design Compiler instead of about 100 times as much (or so the rumor goes).
You're quite right. On the other hand, there are still a few people around who know how to do full-custom VLSI. For something as regular and repetitive as SHA-256 it is possible (though certainly not easy!) Upon someone's suggestion, I have been looking into eASIC. I have a buddy who is a professional ASIC designer, and he says that eASIC has an excellent reputation. On April 28th, less than a week from today, they will officially release their 28 nm design flow (on the 28th, geddit?). That said, right now I don't have the money for such a venture. A year from now - different story. So what kind of cash is involved in that type of idea? Including a one-year subscription to the Synopsys DC, probably between mid 100s and low 200s... Just guessing. I don't want to swing by eASIC right now and say "I'll have the money in a year", because the typical answer to that is "come back in a year". |
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the latest iteration has a design clock rate of 180mhz and meets timing for all of the "ordinary" stages
Drool. -- i.e. all of them except the funny ones at the very beginning, the very end, and the corner turn (stages 30-31).
Could one, two, or all three of these corner cases be solved by adding a "dummy" stage? |
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He is probably right with JTAG Probing, modern FPGAs include pretty good bitstream encryption.
These are totally unrelated. The JTAG interface lets you ask the chip "what chip are you" -- IDCODE. All Xilinx chips have this capability, and it cannot be disabled. I don't know about altera, but I suspect it's the same deal. This has nothing to do with the bitstream/firmware. Interesting so all we would have to do is find the jtag pins and do that. I would be surprised if the JTAG pins were not already broken out to a header (populated or unpopulated) on the board somewhere. This is very standard for any programmable device layout. The Single has a JTAG connector, but BFL have said on this forum that using JTAG won't help in any way in finding out which chip it is. Which leads me to suspect that it is a programmable custom ASIC, originally intended for supercomputing / cryptography. Something like a custom FPGA or a large array of microcontrollers. |
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I didn't see any pricing on there for the chips (just for the design kit). Did you submit a quote request? What technology generation (90nm, 45nm, etc) and reticle size? In other words, any Tom, Dick and Harry may participate in a multi-project wafer run, but only publicly funded research organizations pay a mere 1100 Euros per year for the Synopsys Design Compiler instead of about 100 times as much (or so the rumor goes).
You're quite right. On the other hand, there are still a few people around who know how to do full-custom VLSI. For something as regular and repetitive as SHA-256 it is possible (though certainly not easy!) Upon someone's suggestion, I have been looking into eASIC. I have a buddy who is a professional ASIC designer, and he says that eASIC has an excellent reputation. On April 28th, less than a week from today, they will officially release their 28 nm design flow (on the 28th, geddit?). That said, right now I don't have the money for such a venture. A year from now - different story. |
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