 So just contact him though his website, Gekoscience.com.... Too obvious a solution eh?
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@ZachJ00 DUDE! Please use the CODE tag before posting another wall of text.... It looks like #Your wall then becomes a much more readable Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.10.31-ltsi-00003-gcf03eb9 (lzq@armdev01) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #81 SMP Mon Apr 25 11:20:36 CST 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 258048
free_area_init_node: node 0, pgdat 806e5cc0, node_mem_map 8072a000
Normal zone: 2016 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 258048 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @80f17000 s11200 r8192 d13376 u32768
pcpu-alloc: s11200 r8192 d13376 u32768 alloc=8*4096
pcpu-alloc:
0
1
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 256032
Kernel command line: mem=1008M console=ttyS0,115200 root=/dev/mtdblock3 rw rootfstype=jffs2
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1008MB = 1008MB total
Memory: 1015844k/1015844k available, 16348k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xbf800000 - 0xff000000 (1016 MB)
lowmem : 0x80000000 - 0xbf000000 (1008 MB)
modules : 0x7f000000 - 0x80000000 ( 16 MB)
.text : 0x80008000 - 0x8065a930 (6475 kB)
.init : 0x8065b000 - 0x806adbc0 ( 331 kB)
.data : 0x806ae000 - 0x806e9990 ( 239 kB)
.bss : 0x806e9990 - 0x80729384 ( 255 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17687 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804ab220 - 0x804ab278
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1196.85 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 524288 B
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab <bio-0> at 0
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
Switching to clocksource timer0
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled for 1 cores
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 1984
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
denali-nand-dt ff900000.nand: Dump timing register values:acc_clks: 4, re_2_we: 20, re_2_re: 20
we_2_re: 12, addr_2_data: 14, rdwr_en_lo_cnt: 2
rdwr_en_hi_cnt: 2, cs_setup_cnt: 2
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
5 ofpart partitions found on MTD device denali-nand
Creating 5 MTD partitions on "denali-nand":
0x000000000000-0x000001000000 : "NAND Flash Boot Area 16MB"
0x000001000000-0x000002000000 : "NAND Flash Boot Area backup1 16MB"
0x000002000000-0x000003000000 : "NAND Flash Boot Area backup2 16MB"
0x000003000000-0x00000b000000 : "NAND Flash jffs2 Root Filesystem 128MB"
0x00000b000000-0x000010000000 : "NAND Flash jffs2 Root Filesystem 80MB"
dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=bf8dc000, irq=163)
stmmac_hw_init: 1000M
stmmac - user ID: 0x10, Synopsys ID: 0x37
Ring mode enabled
DMA HW capability register supported
Enhanced/Alternate descriptors
Enabled extended descriptors
RX Checksum Offload Engine supported (type 2)
TX Checksum insertion supported
Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 0007c0f1 at 0 IRQ POLL (stmmac-0:00) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
jffs2: Empty flash at 0x01379264 ends at 0x01379800
jffs2: jffs2_scan_inode_node(): CRC failed on node at 0x026f5ff4: Read 0xffffffff, calculated 0x1490a44b
jffs2: Empty flash at 0x026f604c ends at 0x026f6800
jffs2: jffs2_scan_inode_node(): CRC failed on node at 0x053257d0: Read 0xffffffff, calculated 0x89a57f3a
jffs2: Empty flash at 0x05325828 ends at 0x05326000
jffs2: Empty flash at 0x06d4a440 ends at 0x06d4a800
jffs2: Empty flash at 0x071cc00c ends at 0x071cc800
jffs2: jffs2_scan_inode_node(): CRC failed on node at 0x072d0fc8: Read 0xffffffff, calculated 0x05c6c1f6
VFS: Mounted root (jffs2 filesystem) on device 31:3.
devtmpfs: mounted
Freeing unused kernel memory: 328K (8065b000 - 806ad000)
eth0: device MAC address 6e:1f:aa:4f:59:2e
init phy ok
PHY DMA init OK
eth0: device MAC address 00:87:9f:01:9a:3e
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
libphy: stmmac-0:00 - Link is Down
In axi fpga driver!
Original value in RESET_MANAGER_BASE_ADDR + BRGMODRST_ADDR is 0x0
request_mem_region OK!
AXI fpga dev virtual address is 0xbf942000
*base_vir_addr = 0xc50f
In fpga mem driver!
request_mem_region OK!
fpga mem virtual address is 0xc0000000
libphy: stmmac-0:00 - Link is Up - 100/Full
eth0: device MAC address 00:87:9f:01:9a:3e
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
eth0: device MAC address 00:87:9f:01:9a:3e
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
libphy: stmmac-0:00 - Link is Down
libphy: stmmac-0:00 - Link is Up - 100/Full
This is C5 board.
DETECT HW version=0000c50f
Miner Type = R4
AsicType = 1387
real AsicNum = 63
get PLUG ON=0x00000005
Find hashboard on Chain[0]
Find hashboard on Chain[2]
set_reset_allhashboard = 0x0000ffff
Check chain[0] PIC fw version=0x03
Check chain[2] PIC fw version=0x03
chain[0] has no freq in PIC! Will use default freq=550 and jump over...
Check chain[0] PIC fw version=0x03
chain[2] has no freq in PIC! Will use default freq=550 and jump over...
Check chain[2] PIC fw version=0x03
get PIC voltage=91 on chain[0], value=890
get PIC voltage=91 on chain[2], value=890
set_reset_allhashboard = 0x00000000
chain[0] temp offset record: 3,-71,4,-88,0,0,0,0
chain[2] temp offset record: 3,-81,4,-108,0,0,0,0
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
CRC error counter=0
set command mode to VIL
--- check asic number
set_baud=0
The min freq=700
set real timeout 52, need sleep=379392
After TEST CRC error counter=0
search freq for 1 times, completed chain = 2, total chain num = 2
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
restart Miner chance num=2
waiting for receive_func to exit!
waiting for pic heart to exit!
Start bmminer ...
This is C5 board.
Miner Type = R4
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x0000ffff
Check chain[0] PIC fw version=0x03
Check chain[2] PIC fw version=0x03
Chain[J1] orignal chain_voltage_pic=91 value=890
Chain[J3] orignal chain_voltage_pic=91 value=890
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
Chain[J1] has 63 asic
Chain[J3] has 63 asic
Chain[J1] has no freq in PIC, set default freq=550M
Chain[J1] has no core num in PIC
Chain[J3] has no freq in PIC, set default freq=550M
Chain[J3] has no core num in PIC
read PIC voltage=940 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain:0 temp offset=0
Chain:0 base freq=550
Asic[ 0]:550
Asic[ 1]:550 Asic[ 2]:550 Asic[ 3]:550 Asic[ 4]:550 Asic[ 5]:550 Asic[ 6]:550 Asic[ 7]:550 Asic[ 8]:550
Asic[ 9]:550 Asic[10]:550 Asic[11]:550 Asic[12]:550 Asic[13]:550 Asic[14]:550 Asic[15]:550 Asic[16]:550
Asic[17]:550 Asic[18]:550 Asic[19]:550 Asic[20]:550 Asic[21]:550 Asic[22]:550 Asic[23]:550 Asic[24]:550
Asic[25]:550 Asic[26]:550 Asic[27]:550 Asic[28]:550 Asic[29]:550 Asic[30]:550 Asic[31]:550 Asic[32]:550
Asic[33]:550 Asic[34]:550 Asic[35]:550 Asic[36]:550 Asic[37]:550 Asic[38]:550 Asic[39]:550 Asic[40]:550
Asic[41]:550 Asic[42]:550 Asic[43]:550 Asic[44]:550 Asic[45]:550 Asic[46]:550 Asic[47]:550 Asic[48]:550
Asic[49]:550 Asic[50]:550 Asic[51]:550 Asic[52]:550 Asic[53]:550 Asic[54]:550 Asic[55]:550 Asic[56]:550
Asic[57]:550 Asic[58]:550 Asic[59]:550 Asic[60]:550 Asic[61]:550 Asic[62]:550
Chain:0 max freq=550
Chain:0 min freq=550 which is far less annoying... |
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Bitmain describes the APW8 power supply (which is the psu for S11, T11, S15, T15) as a 16 - 18 V DC power supply. I think that this means the controller board is able to control the psu output voltage fed to the hash boards. That is my thought as well. Doing all regulation in the PSU vs using the normal 2-stages (AC line > PSU 12v > hash boards 7 or whatever volts) certainly kicks up the efficiency. Has anyone looked to see if there is a coms cable going to the s15 PSU? I would think that the Pangolin and Inno miners should do the same thing. |
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Well, y'all convinced me and I have my 1st M10 on order from Pangolin. It will be nice having something other than my very healthy herd of Avalons and the few remaining s9's I have left which are slowly dying board-by-board.  |
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That^^ plus the fact that IF the miner finds a block during the dev mining period you or the pool obviously do not get credit for the block -- the developer does. Just something to keep in mind...
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How long you have on that UPS on power loss? Love the fan speed on the 741 too...
In all cases power & speed checks were done after at least 6 hours of running to make sure the miners were up to full speed and Kanopool would reflect that. The 921 voltage-level -1 and -2 tests ran for 2 days each. For now at least I'm keeping the 921 at voltage-level -1. The 741 and 841's data is after them running for months. |
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Well... just so happens I've been running tests on the miners I have at home... For completeness this also has settings/results for my A741 TV room heater as well as the A841's I have running downstairs next to one of the 3x 921's I just got... Only thing left to do is plug in the J/THs values File date: 1/10/2019
Conditions:
A741 is an upstairs space heater using 120VAC
A841's and 921 are in basement ambient temp 74-76F
A841/921 power source is Tripp*Lite SU6000RT4UHV—6kVA dual-conversion (always on) UPS, all power data comes from it
Voltage output is set to 60Hz and 230VAC +/-0.5%
A841 PSU's are 1.8kw Sorcerers
A921 PSU is Blokforge 2.0kw PSU
%%%%%%%%%% Fun time %%%%%%%%%%%%%
Home A741
Single miner, firmware is MM 9211809-b150820
More Options
--avalon7-voltage-level 8 --avalon7-freq 524 --avalon7-fan 10-40
GUI speed 5360.83GHs Kano speed 5.25THs power ~750w from 120V source
Quiet enough for office or TV room
Temp[39]
TMax[86]
Fan[2220]
FanR[29%]
Vi[1211 1211 1215 1215]
Vo[4166 4138 4124 4148]
GHSmm[5902.34]
WU[75713.21]
Freq[524.00
-----------------------------------------------------------
Home Avalon 841's
Power & speed are average of 2 miners running side-by-side on same came controller
sharing 1 AUC3 with a third 841 fed from different UPS.
All 3 miners using same firmware version MM 8411803-14b0f10
More Options
--api-listen --avalon8-voltage-level -1 --avalon8-fan 10-85
GUI speed 13675.39GHs Kano speed 13.17THs power 1.3kw
Temp[34]
TMax[81]
Fan[5190]
FanR[85%]
Vi[1209 1209 1209 1209]
Vo[3738 3718 3746 3748]
GHSmm[13700.45]
WU[188084.25]
Freq[765.90]
-----------------------------------------------------------
Home A921 Test summary:
Single miner, firmware is MM 9211809-b150820
Using full defaults GUI speed 22+THs Kano speed 22+THs power 2.16kw
Using More Options:
--api-listen --avalon9-voltage-level -1
GUI speed 21116.41GHs Kano speed 19.84THs, power, 2.0kw
--api-listen --avalon9-voltage-level -2
GUI speed 19.047THs Kano speed 18.1THs, power 2.0kw
--api-listen --avalon9-voltage-level -3
GUI speed 17.78THs Kano speed 17.97THs, power 1.9kw
With only GUI Voltage Offset -1
GUI speed 21.5785THs Kano speed 21.34THs, power 2.15kw
with only GUI Voltage Offset -2
GUI speed 21.373 THs Kano speed 21.2THs, power 2.14kw
===========================================================
A921 tweaks and results
Full default
Temp[32]
TMax[95]
Fan[5970]
FanR[76%]
Vi[1232 1232 1236 1236]
Vo[4205 4210 4176 4182]
GHSmm[22235.70]
WU[306008.64]
Freq[835.18]
-----------------------
GUI Voltage Offset -1
Temp[34]
TMax[95]
Fan[6180]
FanR[79%]
Vi[1232 1232 1236 1236]
Vo[4190 4193 4161 4170]
GHSmm[22167.20]
WU[296022.20]
Freq[832.60]
------------------------
GUI Voltage Offset -2
Temp[34]
TMax[95]
Fan[5970]
FanR[76%]
Vi[1232 1232 1237 1237]
Vo[4176 4184 4151 4156]
GHSmm[22127.45]
WU[298652.16]
Freq[831.11]
------------------------
More Options --avalon9-voltage-Level -1
Temp[34]
TMax[94]
Fan[5430]
FanR[68%]
Vi[1233 1233 1238 1238]
Vo[4118 4124 4092 4099]
GHSmm[21639.85]
WU[236014.72]
Freq[812.79]
---------------------------
More Options --avalon9-voltage-level -2
Temp[35]
TMax[95]
Fan[5430]
FanR[68%]
Vi[1233 1233 1238 1238]
Vo[4106 4112 4080 4087]
GHSmm[21612.55]
WU[266368.11]
Freq[811.77]
---------------------------
More Options --avalon9-voltage-level -3
HW[6]
DH[15.893%]
Temp[33]
TMax[95]
Fan[4740]
FanR[57%]
Vi[1232 1232 1235 1235]
Vo[4090 4097 4063 4070]
GHSmm[21419.85]
WU[248682.56]
Freq[804.53]
--------------------------
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Another 'gotcha' can be the USB-A to micro cable feeding the AUC3 - be sure it is a DATA cable and not just a charger cable. Charger cables usually do not support data xfr as all 4 wires in them are used for power.
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You do know that just like the A721/741 and 821/841 use their own software versions the 921 needs to be ran on a Pi using 921 software (OpenWrt) and you cannot mix models on 1 controller? Avalon 921 software here |
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Damn Sam, that is one Lucky Ant!  |
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^^ Good to hear. Now the question will become how many weeks/months the miners run before we start seeing issues  |
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think F1 car against a pinto Actually, more like a F1 car against a 3-legged plow horse... Current ASIC-based miners are hundred's of thousands times faster than mining BTC using GPU's. |
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Ouch! Pool is down to 9PH... Aside from the Halong/btcDrak cabal leaving, where did the other folks move to?
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When you get it, please take a look at how power is fed to the hash boards.
I'm thinking that BM will not be having Vcore regulators on each board and instead will be controlling output of the PSU itself with the chip strings fed directly from the rails. Reason: Losing the additional board level regulators gains several % efficiency
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Meanwhile - lulz at that other pool that wont update their hash rate - it's been well over a week since it dropped below 10PH ... Shhhh! They are being vewy vewy quiet while they are hunting wabbits...   Then again, but for the grace of God and Lady Luck, there go we... |
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Heh heh, gee, color me not surprised.....
At best these folks were highly over-optimistic hucksters from day-1 shilling 7nm tech long long before it was anywhere close to being usable other than as engineering test samples. As a result all performance specs they came up with were pure speculation with zero basis in reality. At worst they were scammers who from the very beginning knew exactly how this would turn out.
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this firmware is a mess
can not do a lot of stuff with it
Perhaps, but unlike BM at least Canaan lets us play with it to see what happens |
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