Order date (1): 1/6/12 Ship date: 4/10/12  Received: 4/12/12  |
|
|
|
Isn't the whole unrolling discussion really quite naive?
The optimal solution will be, depending on the layout of the chip, partly unrolled partly not, depending on which place inside the chip the operation takes place. It isn't really proficient to even talk about unrolling since depending on the amount of elements which can be used for memory, logic and routing a particular approach will be best.
Of course computing a solution which fits this paradigm would probably be too much, however if the tools permit programming the FPGA on a low level it should be at least possible to use close to 100% of all resources for something useful.
As far as I understand, loops that are not 100% unrolled incur inefficiencies, as partial results have to be fed back in and there has to be logic (multiplexers) to do that, whereas data in a fully unrolled design just percolates from start to finish. |
|
|
|
|
OK, after 15 1/2 hours Quartus failed to fit two instances of the double-SHA, albeit at the "optimize for speed" setting.
I have now restarted it with the "optimize for space" setting. The tension is almost unbearable...
|
|
|
|
BFL making their own custom chips seems hard to believe. Their performance per dollar is much better than existing FPGA solutions, but their performance per watt is worse than current FPGA implementations. That's the opposite of what you'd expect from a custom ASIC, at least in the small quantities that BFL would be producing.
Maybe it's some sort of custom FPGA that happens to have fast adders, originally intended for supercomputing applications, and now re-purposed for mining. Remember that BFL and their Single already existed before they stumbled onto mining (and had to redesign the power supply just like Stefan of ZTEX). Being a custom FPGA, it did not wind up as energy-efficient as the products of Xilinx and Altera. |
|
|
|
Is it still only failing on the JTAG clock or is it also failing on the hashing clock?
It never "failed" on the JTAG clock, because I never put a time constraint on the JTAG clock. At 7.3 ns clock cycle, the design passes. Fmax is quoted as 139 MHz and 141 MHz for Slow 0C and Slow 85C, respectively. (Yes, for some reason the Cyclone V is expected to run slightly faster at a higher temperature.) I have not tried to fit two instances of the miner yet. If you have the time, please elucidate the difference between LOOP_LOG2=0 and LOOP_LOG2=1. I can't wrap my head around that - both of them are supposed to be fully unrolled ?!? Which one is the "preferred", "believed to be faster" setting? (I do understand that a setting of 2 means that there is only one SHA-256 instance and its output has to be fed back in front. No need to set LOOP_LOG2 to 2 or higher on the Cyclone V.) You could try the DE2_115_makomk_serial project put together by teknohog, which uses a UART core. I'm designing a newer UART core with more functionality, etc, but that's not done yet and the one by teknohog is perfectly sufficient. You just need to make sure the makomk code in there is up-to-date (I haven't checked yet). Duly noted, but convenient I/O is not my main focus now - rather, I now want to focus on getting two instances fully placed and routed and timed. |
|
|
|
Its only 17 by 41 inches. One of the key features of this tray is its flexibility. The placement of all the floor "beams" are adjustable (horizontally), along with the vertical placement of the PCI and extra GPU support beams. Plus all manor of hardware can be attached to all of those t-slots. Why not simply bolt all ground connections to this aluminum frame? It probably sports lower resistance than traditional power cables. Only relatively short stub ground cables would go to the graphics cards, and, of course, the conventional +12V cables. Thoughts? |
|
|
|
There's a cool ground of people over in europe that make it pretty affordable to do prototype and short-run ASIC chips, in a bunch of different technologies too! http://www.europractice-ic.com/prototyping.phphttp://www.europractice-ic.com/access.phpFor about 1100 EUR/year we can get access to the appropriate design tools and simulators. We already have core logic available to us in Verilog format. This would in theory allow us to (slowly) go from Verilog to a chip design.... Anybody wanna pool up for it?  As far as I understand, the front-end design software is not included, only PUBLICLY FUNDED research organizations are eligible to obtain it for a low annual fee. In other words, any Tom, Dick and Harry may participate in a multi-project wafer run, but only publicly funded research organizations pay a mere 1100 Euros per year for the Synopsys Design Compiler instead of about 100 times as much (or so the rumor goes). |
|
|
|
In fact, I set the clock period of the system clock "osc_clk" to 8 ns in a constraint file, and the design compiled without error.
When I set it to 4 ns (more as a sanity check than as a serious attempt to achieve 250 MH/s), TimeQuest flagged errors.
6 ns ... stay tuned.
Strange, Quartus ignores the jtag clock for me. You might try setting a false path for the jtag clock in your constraints file in order to tell the system to ignore the jtag clock. It should report Fmax for the main clock under the slow timing model section of the timing analyzer output. So you were able to hit 125MHz so far -- that's pretty good and suggests that the Cyclone V can hit at least 250MH/s. It will need to hit at least 300MH/s to make it competitive with the LX150 on a MH/$ basis, but it does seem at least possible that the Cyclone V may displace the LX150 as the new MH/$ leader. A mining board with 2 Cyclone Vs can presumably be produced for about the same cost as a BFL single, but at 600MH/s, it's still less than three quarters of the BFL's mining rate. I wonder if the reduced power consumption (should use less than one quarter of what the BFL uses) would entice many people to buy such a board in lieu of BFL's offering? I'm guessing not, but I'm sure that won't stop someone from making them. Maybe this is what ngzhang has up his sleeve for his Icarus replacement? 7 ns also failed in both slow models, but only by a small margin. 7.3 ns should work (running now, but I have to drive to work now). IMHO, these timing simulations are not 100% accurate - the real-life error rate you get with an actual clock, that's where the rubber meets the road. The fast model works up to 4 ns (250 MHz) - that's very promising and maybe that's what you get in the real world. Or maybe not. We'll never know until someone builds an actual board. |
|
|
|
No, the jtag clock isn't the limiting factor, i had only set the PLL to 120 MHz which seems not sufficient to get optimal synthesis results.
I was compiling for the smallest avaiable part offered by quartus, not the smallest caclone V (I mistakely mixed it with the xilinx artix7 where all sub100k parts were dropped). Btw. how did you select a (the) cycloneV E devise, i could only choose a GX part but the number of aluts seem to be the same.
5CGXBC7C6F23C7 6 ns ... passes "fast 1100mV 0C model", fails both slow models 4 ns ... passes "fast 1100mV 0C model", fails both slow models 3 ns ... fails all 3 models 7 ns ... running as we speak |
|
|
|
Just for curiousity i compiled a single DE2_115_makomk_mod with Quartus 11.1 (no SP) for the smallest CycloneV GX Speedgrade 8. The report said 40% device usage, but the reported Fmax was quite low under 100 MHz. Maybe there is a bug in the timing analyzer since the reportet Fmax was a little higher at 85°C. I think i will try it again with SP2 apllied even if the 'Not in stock' will last for a while (i guess)
I tried that also and got 97 or 98 MHz Fmax, but the signal this pertains to is altera_reserved_tck, which (as far as I understand) is the JTAG clock, not the system clock. In fact, I set the clock period of the system clock "osc_clk" to 8 ns in a constraint file, and the design compiled without error. When I set it to 4 ns (more as a sanity check than as a serious attempt to achieve 250 MH/s), TimeQuest flagged errors. 6 ns ... stay tuned. |
|
|
|
Why would they?
A Mini-rig is simply 16 "new singles". They obviously have limits on production (has anyone yet gotten an order in 4-6 weeks? anyone?). Given that they can sell everything who would choose to sell 1 unit when they could sell 16 units. Fewer, larger orders are easier to handle especially when production constrained.
IF you makes it easier don't think of it as a mini-rig. Think of it as new "single". One caveat you must buy at least 16 and all orders must be in increments of 16 units. My guess is that if there is enough demand someone could likely buy a mini-rig and then sell off the 16 boards.
18, not 16. |
|
|
|
So if the Mini-Rig consists of 24 boards like in this drawing, each one has about 1GH/s and about 20MH/W, just like at some point proposed for the Singles.
It doesn't. It consists of 18 modules, because the power supply takes up some space. Total hash rate is 25 GH/s. |
|
|
|
The Mini Rig is now on BFL's product page; the Rig Box is gone.
The air flow kind of scares me with this setup. Could definitely be optimized, especially if those are fans over each board. I see what looks like 24 singles. By my calculations that is just shy of 20GH/s. I wonder if they're planning on optimizing the Single firmware or designing new modules that gets a little over 1GH/s. Only 18 modules, because the power supply takes up some space. Total hash performance 25 GH/s. |
|
|
|
Ahh these look so sweet. I need a car more than a single though  Get a LOAN for the car, buy a few singles and let the singles pay the monthly car payments... |
|
|
|
Wow. I count upwards of 25Ghash sitting there. I count 25 singles (one of them with my name on it), and 25 x 832 MH/s is 20.8 GH/s. The ones in the rear of the pic are double stacked. OK, you may be right: 35 x 832 MH/s = 29.1 GH/s |
|
|
|
Wow. I count upwards of 25Ghash sitting there. I count 26 singles (one of them with my name on it), and 26 x 832 MH/s is 21.6 GH/s. |
|
|
|
You seriously think a once used BGA FPGA has any value ??
Name one institution/entity that will pay any signifcant sum for a used BGA FPGA that has already been soldered in place.
One of them would be fairly useless. Take 100, or better, 500, and they can be desoldered with a rework station, reballed and sold in bulk. |
|
|
|
|
Honestly, I wouldn't bother with an expensive PDU and an electrician and stuff.
That $900 basically pays for an entire low-end (4 x HD 5830) rig.
Why don't you wire some kind of adapter cable that routes one 110V circuit to a $5 power strip A and the other 110V circuit to a $5 power strip B. Then, you start by plugging in two rigs to power strip A and two rigs to power strip B. This will definitely work. So far, so good.
The elephant in the room is what your circuit breakers actually are.
20A each? This is what I had in Palo Alto, and I maxed them out.
35A each? 30A each? 40A each?
Check the circuit breaker panel. The circuit breakers should be labeled with the office suite #.
If you cannot clearly identify the circuit breakers, buy a $29.99, 1000 W electrical space heater at Walmart.
Plug it into power strip A, while all miners are mining, and turn it on.
Then repeat for power strip B.
If the circuit breaker doesn't fall, you're good to go for another 2 rigs (one goes into strip A and one goes into strip B).
Now you got 6 rigs.
Rinse and repeat this simple test to get to 8 rigs.
I'd stop at 8 rigs, 4 on each side, for a symmetrical load.
Edit: In case a $5 power strip is only rated for 10 A, you'd want more than one for each of the 110 V circuits. But the principle remains: No need to spend $900 on this.
|
|
|
|
The other legs of the 3 phase prob go to other offices. You have 2 legs of 208 3 phase in that outlet.
Does that mean I treat it like a singe phase outlet then? Like TWO 110V single phase outlets. Or like ONE 208V single phase outlet. |
|
|
|
There is no evidence that BFL has started shipping the January orders yet (ordered 12+ weeks ago). Hopefully shipments will resume next week and will be of the heatpipe design.
In fact, according to the delivery tracking thread, not even all 12/26/11 orders have been shipped yet. Which makes the backlog more like 13 weeks, not 12. Also, it is not impossible that there are issues, which have to be worked out, with the heat pipe version as well. Murphy's law pretty much guarantees that. |
|
|
|
|
Show Posts
