Someone requested scope traces before and I still haven't been able to get the scope USB save to work. It just errors out or write 0 byte files - useless. It says use FAT32, which I am, but still doesn't work with either 512MB or 16GB flash sticks. I'll probably have to get some support for that but in the mean time I used my camera to capture some screen shots.
Many thanks:) intron |
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Intron you were using the diodes to protect INSCK INMOSI inputs in the first board.
But bitfury said that there are diodes inside the chip. Are you still using them on new boards?
No. I was alarmed a bit by some of bitfury's comments about the chip being highly sensitive and could be 'fried' in a whimp. Later, when the boards were ready I read the ASIC had protection inside the chip. So on the new boards the zeners are omitted. intron |
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The c-scape firmware has its own TCP/IP stack, JSON parser and mining software,
so it's lightweight and compact, and can run on single chip $5 ARMs in less than
32 KB flash memory. The only code from external sources is the SHA-256 implementation
(about 150 lines), needed to prepare the midstate, and to verify the bitfury results,
and of course bitfury's example SPI code to initialize the chip and get the results.
Currently it only supports the getwork protocol, so it depends on an external
stratum proxy for best results.
c-scape
Which ARM chip? I was thinking about doing something similar with an LPC1768. Has USB OTG, Ethernet, 512kb flash memory with in app programming, and a bunch of other useful features. You can get them in prototyping quantities for ~$6-8 and in lots of 100 for $3-4 (depending on how many chinese distributors you want having your email and phone number). I've got a small stratum implementation tested against stratum proxy, eloipool, etc. I'll upload somewhere when I get home from traveling. We use the NXP LPC1758, quite similar. And looking forward to see your code:) intron |
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Thank you very much for your reply. Felipeo and I were using the term "standalone" in the old software engineering sense: not using the OS services like network stack, dynamic linking and memory management.
A lot of Bitcoin software is hopelessly entwined with humounguos OS-dependent components like Python interpreter or OpenSSL library.
I was just trying to confirm my guess that your miner software isn't dragging that baggage.
Thanks again.
The c-scape firmware has its own TCP/IP stack, JSON parser and mining software, so it's lightweight and compact, and can run on single chip $5 ARMs in less than 32 KB flash memory. The only code from external sources is the SHA-256 implementation (about 150 lines), needed to prepare the midstate, and to verify the bitfury results, and of course bitfury's example SPI code to initialize the chip and get the results. Currently it only supports the getwork protocol, so it depends on an external stratum proxy for best results. c-scape |
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It connects to stratum proxy running on a PC
using it's own TCP/IP stack. No OS, just on
the bare metal. It's c-scape's work.
intron
So its standalone  Not totally, it still needs a PC running a stratum proxy. When there is time and the poor little ARM can handle the workload it would be nice to have it truly stand-alone. intron |
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Code is running on the ARM Cortex M3, getting work from
the pool and sending results back using on-board Ethernet.
Just one quick question about your miner: is it running standalone (no underying OS, but using a lightweight TCP/IP stack) or hosted (by an OS like Linux, and if so, which OS)? Thanks. It connects to stratum proxy running on a PC using it's own TCP/IP stack. No OS, just on the bare metal. It's c-scape's work. intron |
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That is pretty fantastic.... though at 2.15 GH/s the 120GH miner is going to need about 56 of those chips.
Are you going to try to push more power through it to see if you can get the desired 5GH/s speed (for 24 chips), or is that something that metabank themselves will need to be exploring?
We will play around a bit, see what we can get out of this ASIC. But we have no set targets or something. It's merely a fun project:) intron |
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Cool! But how can it estimate hash rate without any accepted shares? Few minutes later: intron_2 2,149.59 MH/s 174 (100.00%) 0 / 1 / 0 |
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intron_1 : 4 USB Block Erupters intron_2 : 1 bitfury ASIC  intron |
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bitfury started hashing: 2013-06-29 16:17:46,068 INFO proxy getwork_listener._on_submit # [19ms] Share from 'intron_2' accepted, diff 1 Picture of the makeshift miner:  Code is running on the ARM Cortex M3, getting work from the pool and sending results back using on-board Ethernet. So bitfury is making btc now:) intron | c-scape |
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Yes. Would love to see a picture of a scope trace
capturing the real wave form.
intron
I tried to capture the wave to put up here but for some reason it didn't save on the USB flash stick in the scope. I got a zero-byte file instead and didn't feel like messing around figuring out why before leaving. I'll be trying again, probably more than a few times. Ok, thanks anyway. Maybe more luck next time... intron |
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Now getting correct Nonce result data.
Have receiver working and posting correct Nonce to host via USB.
So your clocking data into the shift resistor on the falling edge of the output of the NOR gate. Do you know what the setup time is on the data input. Also is the result data 400ns/bit time fixed or is it dependent on the clock frequency? Great progress. Thanks for the update. Yes. Would love to see a picture of a scope trace capturing the real wave form. intron |
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I think I recall you mentioning that your original testing PCBs were designed for Avalon chips. Are you planning on making Avalon compatible hash modules with Bitfury chips? I am sure they would be a very popular upgrade with the Avalon chassis purchasers!
Yes, I started with Avalon. But I'm in batch 4 and I couldn't get samples. So I jumped ship when the bitfury ASIC came along. The S-HASH boards could work with any ASIC, just the interface with the processor needs some re-work and possibly the power supply. So when this is done and I can lay my hands on some Avalon samples I will continue with the Avalon board. Later when BFL ships there ASICs I try to make one for their chip also. intron |
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Propably becuse you are only one that recived chips. Great work by the way...
No, there are more. No idea who they are or how many. intron |
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Layout for 'bitfury H-CARD', the low cost miner board, has been accepted and is now inproduction: http://imgur.com/IWBq5Ctintron Hi intron, can you clarify in which way you are involved with bitfury? Is this the official board bitfury/metabank yis going to use or is it just a prototype board? I didnt saw thr information, am i blind or simply stupid? I'm just one of the alfa-testers. bitfury asked me to post the progress I make, so that's what I'm doing here in this thread. Looks like I'm still the only one doing so:) intron |
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Layout for 'bitfury H-CARD', the low cost miner board, has been accepted and is now in production:  intron |
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Development mining board 'bitfury S-HASH' is underway:  From this the low-cost mining boards will be derived. We get it working hopefully soon and try to learn from it. intron |
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VDD => lets's forget the IOREF line.
Nice. It's in the schematic already:) |
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Normally, IOREF is set with a restistor divider to half IOVDD (normally 1V8). To make the board simpler, IOREF was connected to core voltage. http://imgur.com/QZYoGDQCore voltage was adjusted between 0V59 and 0V83 V and operation of the chips remained normal. Leszek/bitfury, can this be done on the miner board also? Reduces the wiring a bit. intron Yes. This is why IOREF pin is there (near VDD . If you don't use external clock and spi is slow enough (you don not worry about width distortion) - it will work just perfectly. But when you slice CMOS signals not exactly at 50% level - then - you would encounter slight width distortion caused by sampling differences. So what to do on the mining board: connect IOREF to Vcore or connect IOREF to IOVDD/2? intron |
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