That's why it makes zero sense to say they're locked into a process node size once they get their cell library. There's no reason why someone couldn't just get multiple cell libraries for different technologies and design and simulate against both of them. They would only have to chose at the very last minute, before they sent their order into the fab, so long as they ensure the computer generated physical designs simulate properly across all the libraries. OH please, stop talking nonsense. what you get from the fab is not just the cell library, its also all the design rules and parameters. You can ignore the cell library if you want, like bitfury apparently did, but you cant do any meaningful physical design without adhering to the process rules. How are you going to implement one if you dont even know what layers the process has, transistor width, channel length, and a gazillion other process specific parameters and constraints? You seem to think producing an FPGA bitsteam is the same as designing an asic. Just a 5 minute resynthesis, right? Well its not (unless you go with Hardcopy or similar structured asic). The difference between them is the physical design phase and that is NOT process agnostic nor "automatic". Its usually the most laborious step in designing a chip. Now it really sounds like you've never written software (or maybe aren't any good at it), because you can write software that runs on multiple architectures and operating systems really easily. You don't have to decide if you're writing a Windows program or Linux program before you start, even if you're using a language like C, C++. You just use different libraries and have the compiler generate binaries for different CPUs. Yeah einstein, analogies break down. But if you want to continue it, HDL would be your pseudo code and what you get from the fab is the programming language and compiler (along with some sample code you may or may not use). It may be less work to port your code from Java to C++ than starting from scratch, but it aint no last minute job either. It didn't even occur to me to ask, because it didn't even occur to me that you might have valid point.
Right. I get it. Because whats really important here is not whether or not Labcoin could ever deploy their 65nm asic before next spring, its who of us knows more about chip design right? Well, as it turns out, it seems I was on the money about labcoins inability and you were not. Probably just a coincidence.
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bitfury designed their own transistors. Just clarifying.
Correct, I since read that elsewhere. Even I cant always be right
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Who is doing the PCB and software ? How far along is that?
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If I had any doubts, this removes it: https://www.kncminer.com/userfiles/image/ASIC_PCB.jpgThats an altera cyclone FPGA on there. THats what you would use to prototype your design (and pcb). THe chance that a custom asic would fit, let alone work in the same board as an altera fpga is zero. Moreover they write underneath that picture: We will be using these boards to fully validate the entire setup. They will consume the same power, make the same noise level, produce the same heat and run the same RTL code. The only difference will be related to hashing.Definitely an altera hardcopy implementation.
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Why dont you ask TheSeven if there is a snowballs chance in hell this chip will be deployed this year. Im guessing you already did but didnt feel like posting that part.
something similar has been asked to him yesterday: [15:44] <[7]> does that 500th/s plan involve 65nm chips? [15:44] <[7]> this weird TSMC document suggests they're planning to do 65nm in Q1 2014 ... [15:48] <[7]> I'm confident that the interface circuitry for 65nm will be finalized this year, but I have no idea who's even going to implement the hashing core. [15:48] <[7]> if they want me to do that, it would take months, and I wouldn't be very confident that it's going to actually work well [15:48] <[7]> it's a complete redesign from scratch. at least if their plans haven't changed. Gee, who'd have thought? IO might be done this year and thats by far the easiest and least critical part for a bitcoin chip. Sounds like a tape out this year isnt even in the cards and that would make deployment by summer 2014 optimistic. Well good luck labcoin investors!
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Are you saying you think they lied when they specifically said it was a standard cell design and not an FPGA conversion?
Where did they say that and what did they say exactly? You have to admit, the chip being nearly 4x the size of hashfast, worse power consumption, very fast tape out and promised post tape out implementations, apparently no interest in any tests and done by a company that promotes its hardcopy services. I dont know if they lied or what they said, but if it talks like a duck...
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Just out of curiosity, do you have any idea what people actually do with these cell libraries? I don't mean "design the chip" but actually how they physically use them? Because it doesn't sound like you actually have any idea. Are you serious? How do you "physically" use libraries? They are not collections of books you know. Sure sounds like you are the one who has no idea what he is talking about. Go here for a primer: http://en.wikipedia.org/wiki/Physical_design_(electronics) See that? synthesis is automated.
Synthesizing is akin to compiling code. And what you are saying is akin to software development being automated because the computer does the compilation Thats great, now if only you can make it write the code Look, believe what you want. Why dont you ask TheSeven if there is a snowballs chance in hell this chip will be deployed this year. Im guessing you already did but didnt feel like posting that part.
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I think I know now why KnC cant compete with Bitfury on J/GH. And why they are moving so fast. And why they apparently dont feel a need for wafer or chip testing. They use Orsoc to make the chip. On Orsoc's site I see this: Retargeting of complex FPGA design from Xilinx Virtex5 into an Altera Hard Copy http://www.orsoc.se/?page_id=79KnC's chip is most likely not a custom cell based asic, but a hardcopy V implementation. Didnt KnC work on a FPGA earlier? They would just have used that design as starting point and things can go very fast then. Probably a good move too in this race, but not to win in power efficiency, nor die size efficiency nor cost per unit. But the surest way for time to market and probably more affordable NRE.
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And yes it is possible to go faster, by implementing something like altera hardcopy, easic's nextreme, etc which is really inbetween an FPGA and a custom cell based asic. Thats the route KnC most likely took and ActiveMining definitely took.
KnC's chip is done by orsoc. I just checked their website: "Retargeting of complex FPGA design from Xilinx Virtex5 into an Altera Hard Copy" Bingo. Im willing to bet that is why KnC is moving so fast (and performing so poorly on GH/W). Its not a cell based custom asic, its an altera hardcopy V. Also explains why they dont feel a need to do wafer probe testing or even final package tests.
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Will you open registration again? Everybody asked the same question, why don't you answer or did I miss the answer?
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You keep talking as if the feature size for all of these chips was set in stone as soon as they started design work. In fact if you read that post it doesn't even sound like they had picked whether they were going to do 130 or 65 nm: Tthey signed an NDA with the fab and received the cell libraries in July. Its set in stone then. Still took >2 months to tape out and until february to hash. Note that these libraries are not only specific to a node size, but to a specific process at a specific fab. What friedcat did before that would have been process agnostic, but most likely with a process node size in mind. And yes you could pick one smaller of bigger at that point, that isnt the point. The point is the 2 months it took to implement the design for their chosen process and the 7-8 months it took after tape out. But you think its ludicrous to claim that this would likely take 6-9 months. You tell Friedcat that. And Bitfury. And BFL. IOW, everyone who so far has brought a bitcoin asic to market and even most of the one's that havent done yet but already believe they cant do it much faster, like black arrow and cointerra. And yes it is possible to go faster, by implementing something like altera hardcopy, easic's nextreme, etc which is really inbetween an FPGA and a custom cell based asic. Thats the route KnC most likely took and ActiveMining definitely took. Doing that makes the development cycle substantially shorter, and has a lower NRE, but you pay for that in higher unit prices, worse performance and worse power efficiency. On 28nm thats a good tradeoff right now. But not something you can afford on a 65nm process that wont arrive until next year. The evidence you're presenting is totally irrelevant to the actual claim you made.
The evidence covers 100% of all other bitcoin asics. Whats your evidence it can be done substantially faster?
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Sorry if this is has been asked before, but its a long thread. Will these miners have a CE/FCC label on them?
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But there doesn't seem to be much basis for saying that the process node needs to be fixed 9 months before chips finish.
All the evidence points in that direction, that especially for a small team it does take that much time. Need one more ? Asicminer started their design in june 2012, selected the process and published preliminary specs in July, taped out end of september, started hashing in February. https://bitcointalk.org/index.php?topic=91173.msg1003326#msg1003326Friedcat is no idiot, wasnt underfunded, used an old "simple" process node, but it took 8 months between selecting their process node and hashing. What basis do you have to assume labcoin could go so much faster?
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Yes adjusted for inflation you may decide to hold to maintain your purchasing power. However, most investors/traders are not convinced the price will go up or down. They give it a probability. For example, suppose hypothetically that I think there is a 50% chance bitcoin will be over $1000 by 2025 so I allocate a portion of my investment fiat to bitcoin, yet I have the ability to purchase more.
Thats the point. The chance that bitcoin is worth exactly $123 in 2025 is close to zero. Heck, the chance its that tomorrow is pretty small. But the aggregate off all the expected probabilities of bitcoin investors currently averages to $123. Thats a much more meaningful number than a poll on this forum.
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I have never taped out a thing in my life either, and my experience with the industry is image sensors, not asics, and not even from design POV. Most of the steps will be similar, but lets not waste time going over that. I am not a rocket scientist either, and cant tell you all the steps involved in launching a rocket and docking it with the space station. I can tell you you almost certainly cant do it 6 weeks if you start from scratch. Simply deducting from common sense how long it took others. How long did it take between the time bitfury settled on a 55nm design for them to have working silicon? I dont know, but I do know bitfury raised the idea of developing his own asic back in may of 2012, I know they taped out in March this year, had prototypes hashing in July and have only recently been shipping in volume. I might also add, if Bitfury was involved in this project, Id probably have bought in. Anyway, your argument seems to be they may be further ahead in the design and closer to tapeout that Im willing to believe, and that may be so. But you should be asking Theswede for evidence of that rather than asking me to prove the negative. Everything I have seen so far points towards little more than vague ideas and not being anywhere near tape out. In fact, Ive not seen anything that leads me to believe there will ever be one "rev2". TheSeven has recently been contracted to do "some work". Fine, but my guess is that he has been asked to come up with some numbers, rough projections. If that had already been done, wouldnt we have heard them? So he is probably not doing more a preliminary feasibility study, One that should lead to canceling this whole project, if there ever was one. And if it doesnt, you can go by any of the other bitcoin asics to get an idea of when it could realistically be deployed. Not this year, that much Im very confident off. Next summer seems a lot more plausible and financially unfeasible.
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Whats with this
Bitfunder: ฿0.00119799
btct.cp: 0.001966
Thats nearly twice the price?
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From tape out to working silicon is typically 2 months or more. If you believe they are close to tape out, but havent even selected a process yet, I got a bridge to sell.
One more reference point. New entry: black arrow. They are not a huge company, and I dont know if they partnered with anyone else, but at least they do have some relevant bitcoin hardware experience and a good reputation. THey are now promising delivery of their new asics and miners a few days before March 2014: http://www.blackarrowsoftware.com/store/minion.htmlIm assuming they taped out, at the very least they picked a process and have finished the design and simulations. You think its likely labcoin will beat them to the punch? Im willing to bet with unreasonably uneven odds Labcoin wont have their own 65nm asic hashing 6 months from here.
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We are making the most efficient ASIC possible and there's nowhere to go to from 28nm until 2015 I agree, and power efficiency will once again become the key but we are still very far from that point. Right now, the price (hardware write off) is still a much bigger factor. Once we reach >10PH, and hardware prices have come down correspondingly, your low power consumption will become an asset. But not yet IMO. As for the rest, probably the wrong thread, but since you bring it up: If our ASIC will not be profitable, no ASIC will be
Thats exactly what I expect. But judging by the avalanche of preorders, not many agree, so you should be good and bitcoin mining will stop. You know better than saying that. Sales will dry up, thus prices will drop, sales will resume, miners still wont make a profit, sales will dry up, prices will drop,.. rince repeat. But whatever happens, mining wont stop. Even sales wont. Anyway, thats for another thread. I do wish you good luck.
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I dont know what it will be in 2025, but I can tell you fairly exactly what the current consensus is of what it will be: $123 (excl inflation).
THink about it, anyone convinced it would be way higher would buy more, anyone thinking it would be way lower would sell. The current price is an exact reflection of what we all combined think it will be worth in the future. A much better indicator than your poll.
Anyone expecting $123 in 2025 would most likely sell, causing prices to drop, and buy something they expected to be higher in the future... I know I would. $123 adjusted for inflation. Your reasoning also doesnt make a lot of sense, are people selling gold when they expect gold to remain stable compared to an inflation adjusted dollar? Are they not buying government bonds anymore that barely keep pace with inflation?
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You will receive hardware that can scan 1733 Ghash/second. If that happens we will send you a 1 * X-3 with all 21 ASICs and 1 x X-3 with 6 ASICs.
I guess the obvious next quesiion is, what happens when the price on X1 drops by 30%, and I ordered just one? If the X3 is too high for your budget, please consider X1. ITs not a matter of budget, but profitability. But like I said, thats not specific to your company, but to the market at large.
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