OMG - A joke post!  It is an ode to shipping on time.  |
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They took 1 of the 6 wafers from the bumping facility to wire it up for testing.
Q: Why?
A: They did this because bumping was taking awhile and they wanted to be able to give the fab the go ahead to put the final layers on the other 6 wafers in waiting.
Q: What happened?
A: They say the test went fine, everything is okay.
Q: So did they tell the fab to finish putting the final layers on the 6 wafers in waiting?
A: No...
Q: Why?
A: They said they're going to wait to do final testing of the first 5 wafers leaving the bumping facility going onto packaging before initiating the final layer production at the fab.
What does this tell you?
Either they're idiots and just threw away 1/6th of their first run for no reason or... something didn't go as they had planned with the wire bond testing. https://forums.butterflylabs.com/bfl-forum-miscellaneous/1221-there-problems-asic-chips-2.html#post17173No, everything is going just fine.  The growing sentiments are frightening. |
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Are you betting against them?
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I hate nothing more than doing customer service and responding to emails. I actually would like to hear the latest controversy on Avalon while I am not looking at some annoying email. If you can find it in you to post (real crap) about what Avalon is or is not doing, by all means, shoot for the moon.
Do you believe you are doing us all a favor? Like some sort of public service? Or am I misunderstanding the bolded part above? No, it is what I do when I am on the computer and am avoiding (email related) work. |
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I just checked, and 35 of your last 40 posts have been in BFL threads. Can you stop? Anyone who cares will be at the BFL forums, and will get all the information they need. Avalon updates only once or twice a month. So why can't you only post once or twice a month? If you're looking for stuff to post on cuz you're bored, there are plenty of other sub-forums to browse. You might have missed the part where I mentioned I come here to check when I will get my hardware. The other forum sections (while vast) are outside of my interest. The lack of Avalon updates Thank you for the validation. I will be "bumping" Avalon threads mercilessly just to throw off your count. (Pun intended on the "BUMPing") [...] has absolutely nothing to do with the fact that the VAST majority of your posts are in BFL threads.
They are the competition. Like I said, you didn't complain when former BFL trolls mercilessly pestered the bASIC threads. Now that it is the company where you are invested in, you have "issues". By the way, there is trouble in paradise: https://forums.butterflylabs.com/bfl-forum-miscellaneous/1221-there-problems-asic-chips.htmlBy your logic I should bombard every Avalon thread with seemingly useful information (i.e. Its March 5th, Avalon still hasn't shipped out most of Batch 1, How dare they take orders for Batch 2, they don't answer most customer service concerns in a timely manner, they screwed up order taking for batch 2, they don't give refunds) Since it is ok for you to do, I guess it should be ok for me to expose this information about Avalon in a new thread every time I read something right? Go right ahead. I encourage people to do this if they want to. It will at least be more entertaining than reading BFL crap. I hate nothing more than doing customer service and responding to emails. I actually would like to hear the latest controversy on Avalon while I am not looking at some annoying email. If you can find it in you to post (real crap) about what Avalon is or is not doing, by all means, shoot for the moon. |
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I just checked, and 35 of your last 40 posts have been in BFL threads. Can you stop? Anyone who cares will be at the BFL forums, and will get all the information they need. Avalon updates only once or twice a month. So why can't you only post once or twice a month? If you're looking for stuff to post on cuz you're bored, there are plenty of other sub-forums to browse. You might have missed the part where I mentioned I come here to check when I will get my hardware. The other forum sections (while vast) are outside of my interest. The lack of Avalon updates Thank you for the validation. I will be "bumping" Avalon threads mercilessly just to throw off your count. (Pun intended on the "BUMPing") [...] has absolutely nothing to do with the fact that the VAST majority of your posts are in BFL threads.
They are the competition. Like I said, you didn't complain when former BFL trolls mercilessly pestered the bASIC threads. Now that it is the company where you are invested in, you have "issues". By the way, there is trouble in paradise: https://forums.butterflylabs.com/bfl-forum-miscellaneous/1221-there-problems-asic-chips.html |
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That is one damn tiny chip!
(If it is ASICMiners specs...wow, they must have a hell of alot of chips worth to bring online.)
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Thanks for the info.  |
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on github? the overclocking para is been in the git for awhile now, it's just not enabled by default. I'll forward the BFGMiner. What is the stock speed (66Ghz) in Mhz? |
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This whole testing fiasco is really a wonderment. To lose that many precious (and expensive) chips to only gain a marginal amount of useful information is insane. At any company I have worked for that kind of decision would have landed someone a pink slip.
To be fair, the cost of a processed 65nm wafer is likely somewhere between $1500-$2000. Not exactly a fortune. Avalon pays (it is estimated) about 4k per wafer at 110nm. How is BFL paying half that at 65nm? Somehow your estimates sounds kinda off. How many chips per wafer does Avalon get? I don't recall. I think it may have been 4,000 chips per wafer. I only recall that the die size is 7x7mm while BFL's is 15x15. |
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Anyone care to place bets on all this? I'm worried another one of my bets are going to lose out  What is your latest bet? (I don't gamble) |
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...
Developers - e.g. bitcoin core dev and other bitcoin contributor we feel deserve this treatment.
Trade-Ins/Old Customers - your unit will ship soon as we receive the FPGA and you've paid the difference.
...
Lucky I don't want one, otherwise if I held them to their word they'd have to ship me an Avalon as soon as I sent them one of my Icarus and paid the difference  I thought you couldn't afford to buy them? |
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I just checked, and 35 of your last 40 posts have been in BFL threads. Can you stop? Anyone who cares will be at the BFL forums, and will get all the information they need. Avalon updates only once or twice a month. There is almost zero activity going on in Avalon threads. What do you want me to post to make the averages seem better? ------------------ By your token reasoning, I should ask the Moderators to delete BFL threads as they already have an offsite forum. |
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This whole testing fiasco is really a wonderment. To lose that many precious (and expensive) chips to only gain a marginal amount of useful information is insane. At any company I have worked for that kind of decision would have landed someone a pink slip.
To be fair, the cost of a processed 65nm wafer is likely somewhere between $1500-$2000. Not exactly a fortune. Avalon pays (it is estimated) about 4k per wafer at 110nm. How is BFL paying half that at 65nm? Somehow your estimates sounds kinda off. |
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BFL is making it look like the chips working are a done deal. To give the aura that things will be done soon. All the while updating people with details on what....well what they actually don't know yet "for sure"...whether the chips actually work at the speed they originally intended.
Josh mentioned at the beginning of the weekend that the chips were about to go through full speed tests a few days ago after they ran a low speed functionality test. Then he turns around at the end of the weekend and reveals that this can't be done without the full packaging.
You can tell they are cowboys. Cowboys that are clearly disconnected from the process or the innate knowledge of what is necessarily possible by the professionals making the ASIC design.
So far, they sacrificed 1,000 chips (a full wafer) for functionality tests. Seemingly without a reason (they are cowboys remember?). Had they actually known that the full speed tests could not be done without proper packaging, they would probably have not scarified a full wafer. When they did sacrifice a full wafer, they seemed to be unaware that full speed tests would not be "do-able".
Next, they have begun finalizing the next batch of 6 wafers before they actually know what will actually happen when all 16 cores hash at full speed. (magic smoke?)
So if there is anything wrong, the second batch will likely suffer from it as well.
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You know what I find interesting?
The fact that in this ASIC project they are using valuable time to test the chips and at the same time convince customer(s) they actually work.
This is what should normally take a few weeks as pointed out by a few hardware folks on this forum. This necessary testing process is being compressed into a few days in an "Ad-Hoc" manner.
What is even more interesting, is that some false impressions are being beamed out.
For example, BFL customers are being comforted with the illusion that their chips will ship soon "for certain". But...they are still running the chips through "functional tests". NOT full throttle performance evaluation(s) mind you, no, just basic low speed functionality tests.)
So in essence BFL is taking a calculated risk for the sake of speed. What normally would have been done in a back room somewhere (away from prying eyes) for a few weeks is actually being done in open view.
That doesn't bother me much as a spectator.
What really does bother me, is that two mixed impressions are being given out. The first false implied impression that the chips work and will ship soon. (they don't know this yet, but thats why they are testing it.)
The second false impression is that the chips are just undergoing a "little testing" to confirm things are in working order. That isn't the case. The testing going on is whether the design actually functionally works, whether it meets (performance/electrical) specs and finally whether the chips ultimately are worth while.
Anyone with a semblance of understanding would read these updates and realize that alot of praying is going on as they rush through each step.
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Keep this in the back of your mind when you read what is being disseminated or at the very least when you ask the next question. Because someone who has a false impression would be disappointed if the chips break at stock speed.
While someone who is an engineer or a semi-conductor designer knows this is simply a reality of the "testing phase" of a design.
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