Grrrrr  been at it for hours today and any version higher than 3.9.0 will not compile with the modified driver. Try again later  |
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Haha! Gold! Fair enough then mate. Still though, you've done pretty well since then. In fact awesome progress. Ur current release is sweet as and runs like a dream
Thanks  On request from BakSAj I am trying  (not yet working) to compile a version under cgminer 4.6.0 |
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Any news regarding a multipool paying in BTM?
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I thought so. What I'm talking about is more in reference to the WU, not the physical miner, which is what this thread and your OS is all about. Apologies to yourself & everyone BTW for simply adding rubbish, to a really good thread
It's alright. I actually added quite some rubbish myself in the beginning of this thread by posting an image that did not work  |
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Thanks mate. I get ya. Example wafflepool suggests making ur password based on ur hashing power. Being mine is between 64mhs and 128mhs, they suggest setting password to d=32768. Is that the sort of thing your referring to also? Or am I goin off topic now?
You are going a little bit off topic  but yes that is possible too. |
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Hi Emdje,
I know this is a really newb question. But what ip address is the new firmware set at? Only asking because my mates placed our internet connection on 192.168.2.... rather than the usual 192.168.1 and am having trouble working out what ip the firmware web interface is set at?
Ive tried 1.125, 1.136, 1.106, 1.163 and im out of guesses now. lol
Any help would be greatly appreciated. Cheers mate
Alex
The OS is set to DHCP. I advise using a port-scanner to find out. Thnx for the answer BakSAj. I logged into the router and looked at the connected devices to figure out which ip-address the miner had. Hi guys, Ive setup the new firmware and it seems to be running smooth at 1320mhz, which most people agree on this thread, is a good stable point for each module.
Only question i have is, whats the best setting to place the DEVICE INITIAL DIFF?
Ive set mine at 128 for the moment, but I'd appreciate any feedback/explanation which anyone may have.
For example, what setting is most suitable and what exactly is the 'DEVICE INITIAL DIFF', in the first place?
cheers again guys, appreciate all the help so far.
Alex
Depends on the mined coin. A very 'fast coin' (fast block time) requires a lower difficulty, a 'slow coin' (slow block time) requires a higher difficulty. A lot of pools have automatic difficulty selection. When that is the case you don't really have to do anything. |
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does anybody know if this will work with the new A2terminator mini, and with what frequency setting, if so?
I have not seen one yet on the inside but I bet it will work on the 'new' a2 miners. Just a new form factor and reduced price I think. |
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I altered the driver, not the actual code of cgminer (and then compiled it). On page 16 from the programming manual http://www.usbminers.nl/Innosilicon_A2_PG_v120140424.pdf there is a column named: io_pll_fb_div. In that column there is a binary code which is related to the clock frequency. Only increments of 20Mhz are accepted otherwise the is_pll_fb_div becomes a comma separated number, and that can't be transformed to binary. So, I added the extra binary numbers to the driver, and 'paired' it to the dropdown menu you see in the browser (index.php) Because it is not a simple change of the index.php you need the whole image. |
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emdje: good job! where did you get the cgminer binary, if I may ask? Might be cool if voltage can be increased.
Someone who makes mining hardware contacted me with a problem I might be able to help with. So we helped each other. I can't give anyone the source code, at least not yet. But I have seen nothing that indicates the voltage can be increased in the code. Seems all hardware. |
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oops, forgot to add..... One last question mate.
Crytptalk mentioned the Scrypta OC firmware I have the link for, mentioned above, doesn't require extra cooling for the a2 chips because the firmware apparently controls the temperature of the a2 chips to prevent overheating.
Question: Does your latest update to your firmware, do the same, so I won't have to build an airconditioner pipping assembly to feed the air con air straight to my miners intake fans?
The temperature is controlled by decreasing the amount of work going to the processors. Just try it out, see what the hash rate (poolside) does and decide what to do. |
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I have seen more of the same article on different websites, but that is about the image I made before this one, where indeed only the values 1000, 1200, 1280, 1300 and 1400 were accepted. In this version the values 1000, 1080, 1200, 1220, 1240, 1260, 1280, 1300, 1320, 1340, 1360, 1380 and 1400 are accepted. However, this time it does not work to simply change the index.php file, you need the entire image: https://mega.co.nz/#!GNMQAIrb!IjkpJvS36O29AfOKc_jR9aezdH5yZnHMiGY5mIGyypk |
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It can take 1220Mhz as effective? So its REALLY set as new frequency and not defaulted to 1200? Which cgminer binary is that? Thanks
Yes it REALLY sets it as a new frequency! Look at post 42 (the first two frequencies, I only have an A2 mini). This was 1320Mhz, it takes that, but it takes the rest as wel. 1320 was always possible as far as i remember. did you try e.g. 1220? Just for you BakSAj : [2014-08-30 05:36:53] Started cgminer 3.9.0
[2014-08-30 05:36:53] Run Reset=1
[2014-08-30 05:36:53] ST MCU hardware reset start
[2014-08-30 05:36:57] SPI Speed 4000 kHz
[2014-08-30 05:36:57] ST MCU - Enable (Pre-header)
[2014-08-30 05:36:57] A1 = 1220,9 <------
[2014-08-30 05:36:57] A1 PLL Clock = 1220MHz <------
[2014-08-30 05:36:57] A1 = 1240,8 <------
[2014-08-30 05:36:57] A1 PLL Clock = 1240MHz <------
[2014-08-30 05:36:57] A1 = 1300,5
[2014-08-30 05:36:57] A1 PLL Clock = 1300MHz
[2014-08-30 05:36:57] A1 = 1300,5
[2014-08-30 05:36:57] A1 PLL Clock = 1300MHz
[2014-08-30 05:36:57] A1 = 1300,5
[2014-08-30 05:36:57] A1 PLL Clock = 1300MHz
[2014-08-30 05:36:57] A1 = 1300,5
[2014-08-30 05:36:57] A1 PLL Clock = 1300MHz
[2014-08-30 05:36:57] AUTO GPIO CS
[2014-08-30 05:36:58] spidev0.0(cs0): Found 8 A1 chips
[2014-08-30 05:36:58] Found chip 1 with 54 active cores
[2014-08-30 05:36:58] Found chip 2 with 54 active cores
[2014-08-30 05:36:58] Found chip 3 with 54 active cores
[2014-08-30 05:36:58] Found chip 4 with 54 active cores
[2014-08-30 05:36:58] Found chip 5 with 54 active cores
[2014-08-30 05:36:58] Found chip 6 with 54 active cores
[2014-08-30 05:36:58] Found chip 7 with 54 active cores
[2014-08-30 05:36:58] Found chip 8 with 54 active cores
[2014-08-30 05:36:58] Found 8 chips with total 432 active cores
[2014-08-30 05:36:59] spidev0.0(cs1): Found 8 A1 chips
[2014-08-30 05:36:59] Found chip 1 with 54 active cores
[2014-08-30 05:36:59] Found chip 2 with 54 active cores
[2014-08-30 05:36:59] Found chip 3 with 54 active cores
[2014-08-30 05:36:59] Found chip 4 with 54 active cores
[2014-08-30 05:36:59] Found chip 5 with 54 active cores
[2014-08-30 05:36:59] Found chip 6 with 54 active cores
[2014-08-30 05:36:59] Found chip 7 with 54 active cores
[2014-08-30 05:36:59] Found chip 8 with 53 active cores
[2014-08-30 05:36:59] Found 8 chips with total 431 active cores
[2014-08-30 05:36:59] SPI(cs2) no device
[2014-08-30 05:36:59] ACK(cs2) timeout:cmd_RESET_BCAST-0.0340s
[2014-08-30 05:36:59] SPI(cs3) no device
[2014-08-30 05:36:59] ACK(cs3) timeout:cmd_RESET_BCAST-0.0325s
[2014-08-30 05:36:59] SPI(cs4) no device
[2014-08-30 05:36:59] ACK(cs4) timeout:cmd_RESET_BCAST-0.0330s
[2014-08-30 05:36:59] SPI(cs5) no device
[2014-08-30 05:36:59] ACK(cs5) timeout:cmd_RESET_BCAST-0.0409s
[2014-08-30 05:36:59] A1 boards=2, active cores=863, Efficient=99%, speed=30.0M
[2014-08-30 05:36:59] Probing for an alive pool
[2014-08-30 05:36:59] Failed to resolve (?wrong URL) /:80
[2014-08-30 05:36:59] Pool 2 slow/down or URL or credentials invalid
[2014-08-30 05:36:59] Pool 1 difficulty changed to 512
[2014-08-30 05:36:59] Switching to pool 1 stratum+tcp://xxxxx - first alive pool
[2014-08-30 05:36:59] Pool 0 stratum+tcp://xxxxxxxxxxalive, testing stability
[2014-08-30 05:36:59] Switching to pool 0 stratum+tcp://xxxxxxxxxxxxx
[2014-08-30 05:36:59] Reconnect requested from pool 0 to xxxxxxxxxxxxxxxxxxxxx
[2014-08-30 05:37:00] Pool 0 difficulty changed to 64
[2014-08-30 05:37:00] Network diff set to 235
[2014-08-30 05:37:05] Network diff set to 28.1K
[2014-08-30 05:37:05] API running in UNRESTRICTED read access mode on port 4028 (8)
[2014-08-30 05:37:05] New block detected on network before longpoll
(5s):12.02K (avg):30.77Kh/s (pool):0.000h/s | A:0 R:0 HW:0 WU:0.0/m
[2014-08-30 05:37:05] Accepted b8993e0b Diff 355/64 BA1 1 pool 0
[2014-08-30 05:37:05] Accepted b7e4d8bf Diff 356/64 BA1 0 pool 0
[2014-08-30 05:37:05] Accepted 014b4607 Diff 197/64 BA1 1 pool 0
[2014-08-30 05:37:05] Accepted a3f39325 Diff 399/64 BA1 1 pool 0
[2014-08-30 05:37:06] Accepted 01d60a79 Diff 139/64 BA1 0 pool 0
[2014-08-30 05:37:06] Accepted 01ac8489 Diff 152/64 BA1 1 pool 0
[2014-08-30 05:37:06] Accepted 014bd77a Diff 197/64 BA1 1 pool 0 |
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It can take 1220Mhz as effective? So its REALLY set as new frequency and not defaulted to 1200? Which cgminer binary is that? Thanks
Yes it REALLY sets it as a new frequency! Look at post 42 (the first two frequencies, I only have an A2 mini). This was 1320Mhz, it takes that, but it takes the rest as wel. |
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Mark, I'm pretty impressed with Bitmark, especially the level of professionalism you've brought to it. In the last day or so I've had several people who are enthusiastic about BTM contact me about setting up a pool for it. We ( Simple Crypto) are nearing completion for a beta launch of a multipool, and are considering adding BTM as a payout option - if there is enough interest. Cheers Yes I would be interested |
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Good news: [2014-08-26 04:33:05] Started cgminer 3.9.0
[2014-08-26 04:33:05] Run Reset=1
[2014-08-26 04:33:05] ST MCU hardware reset start
[2014-08-26 04:33:09] SPI Speed 4000 kHz
[2014-08-26 04:33:09] ST MCU - Enable (Pre-header)
[2014-08-26 04:33:09] A1 = 1320,4
[2014-08-26 04:33:09] A1 PLL Clock = 1320MHz
[2014-08-26 04:33:09] A1 = 1320,4
[2014-08-26 04:33:09] A1 PLL Clock = 1320MHz
[2014-08-26 04:33:09] A1 = 1300,5
[2014-08-26 04:33:09] A1 PLL Clock = 1300MHz
[2014-08-26 04:33:09] A1 = 1300,5
[2014-08-26 04:33:09] A1 PLL Clock = 1300MHz
[2014-08-26 04:33:09] A1 = 1300,5
[2014-08-26 04:33:09] A1 PLL Clock = 1300MHz
[2014-08-26 04:33:09] A1 = 1300,5
[2014-08-26 04:33:09] A1 PLL Clock = 1300MHz
[2014-08-26 04:33:09] AUTO GPIO CS
[2014-08-26 04:33:10] spidev0.0(cs0): Found 8 A1 chips
[2014-08-26 04:33:10] Found chip 1 with 54 active cores
[2014-08-26 04:33:10] Found chip 2 with 54 active cores
[2014-08-26 04:33:10] Found chip 3 with 54 active cores
[2014-08-26 04:33:10] Found chip 4 with 54 active cores
[2014-08-26 04:33:10] Found chip 5 with 54 active cores
[2014-08-26 04:33:10] Found chip 6 with 54 active cores
[2014-08-26 04:33:10] Found chip 7 with 54 active cores
[2014-08-26 04:33:10] Found chip 8 with 54 active cores
[2014-08-26 04:33:10] Found 8 chips with total 432 active cores
[2014-08-26 04:33:11] spidev0.0(cs1): Found 8 A1 chips
[2014-08-26 04:33:11] Found chip 1 with 54 active cores
[2014-08-26 04:33:11] Found chip 2 with 54 active cores
[2014-08-26 04:33:11] Found chip 3 with 54 active cores
[2014-08-26 04:33:11] Found chip 4 with 54 active cores
[2014-08-26 04:33:11] Found chip 5 with 54 active cores
[2014-08-26 04:33:11] Found chip 6 with 54 active cores
[2014-08-26 04:33:11] Found chip 7 with 54 active cores
[2014-08-26 04:33:11] Found chip 8 with 54 active cores
[2014-08-26 04:33:11] Found 8 chips with total 432 active cores
[2014-08-26 04:33:11] SPI(cs2) no device
[2014-08-26 04:33:11] ACK(cs2) timeout:cmd_RESET_BCAST-0.0336s
[2014-08-26 04:33:11] SPI(cs3) no device
[2014-08-26 04:33:11] ACK(cs3) timeout:cmd_RESET_BCAST-0.0321s
[2014-08-26 04:33:11] SPI(cs4) no device
[2014-08-26 04:33:11] ACK(cs4) timeout:cmd_RESET_BCAST-0.0314s
[2014-08-26 04:33:11] SPI(cs5) no device
[2014-08-26 04:33:11] ACK(cs5) timeout:cmd_RESET_BCAST-0.0322s
[2014-08-26 04:33:11] A1 boards=2, active cores=864, Efficient=100%, speed=32.7M
[2014-08-26 04:33:11] Probing for an alive pool
[2014-08-26 04:33:11] Pool 2 difficulty changed to 32
[2014-08-26 04:33:11] Pool 1 difficulty changed to 512
[2014-08-26 04:33:11] Switching to pool 2 stratum+tcp://xxxxx - first alive pool
[2014-08-26 04:33:11] Pool 1 stratum+tcp://xxxxx alive, testing stability
[2014-08-26 04:33:11] Switching to pool 1 stratum+tcp://xxxxx
[2014-08-26 04:33:11] Pool 0 stratum+tcp://xxxxx alive, testing stability
[2014-08-26 04:33:11] Switching to pool 0 stratum+tcp://xxxxx
[2014-08-26 04:33:11] Reconnect requested from pool 0 to xxxxx
[2014-08-26 04:33:12] Pool 0 difficulty changed to 64
[2014-08-26 04:33:13] Network diff set to 261
[2014-08-26 04:33:17] Network diff set to 28.5K
[2014-08-26 04:33:17] API running in UNRESTRICTED read access mode on port 4028 (9)
[2014-08-26 04:33:17] New block detected on network before longpoll
(5s):13.01K (avg):33.32Kh/s (pool):0.000h/s | A:0 R:0 HW:0 WU:0.0/m
[2014-08-26 04:33:17] Accepted 01177391 Diff 234/64 BA1 0 pool 0
[2014-08-26 04:33:17] Accepted 75124b09 Diff 559/64 BA1 1 pool 0
[2014-08-26 04:33:18] Accepted 01207814 Diff 227/64 BA1 1 pool 0
[2014-08-26 04:33:18] Accepted ba2b3b60 Diff 352/64 BA1 1 pool 0
[2014-08-26 04:33:19] chip(cs0) 1: invalid nonce 0x8c303900
[2014-08-26 04:33:19] Accepted e06f0d3d Diff 292/64 BA1 0 pool 0
[2014-08-26 04:33:19] Accepted 6e626f3c Diff 593/64 BA1 1 pool 0 The miner can send work to 8 boards, I only have 2. But as you can see the 1320Mhz is accepted by the miner  I will test some more, but this looks promising end of update |
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Hi guys and girls, I am trying, for the first time, to compile cgminer on my PI but I run into the following error: How do I install libbcm2835?? pi@raspberrypi ~/Documents/cgminer-3.9.0-a2-dg $ make install
/bin/bash ./config.status --recheck
running CONFIG_SHELL=/bin/bash /bin/bash ./configure --enable-bitmine_A1 --without-curses --no-create --no-recursion
checking build system type... armv6l-unknown-linux-gnueabihf
checking host system type... armv6l-unknown-linux-gnueabihf
checking target system type... armv6l-unknown-linux-gnueabihf
checking for a BSD-compatible install... /usr/bin/install -c
checking whether build environment is sane... yes
checking for a thread-safe mkdir -p... /bin/mkdir -p
checking for gawk... no
checking for mawk... mawk
checking whether make sets $(MAKE)... yes
checking whether make supports nested variables... yes
checking for style of include used by make... GNU
checking for gcc... gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables...
checking whether we are cross compiling... no
checking for suffix of object files... o
checking whether we are using the GNU C compiler... yes
checking whether gcc accepts -g... yes
checking for gcc option to accept ISO C89... none needed
checking dependency style of gcc... gcc3
checking how to run the C preprocessor... gcc -E
checking for grep that handles long lines and -e... /bin/grep
checking for egrep... /bin/grep -E
checking for ANSI C header files... yes
checking for sys/types.h... yes
checking for sys/stat.h... yes
checking for stdlib.h... yes
checking for string.h... yes
checking for memory.h... yes
checking for strings.h... yes
checking for inttypes.h... yes
checking for stdint.h... yes
checking for unistd.h... yes
checking minix/config.h usability... no
checking minix/config.h presence... no
checking for minix/config.h... no
checking whether it is safe to define __EXTENSIONS__... yes
checking whether to enable maintainer-specific portions of Makefiles... no
checking for gcc... (cached) gcc
checking whether we are using the GNU C compiler... (cached) yes
checking whether gcc accepts -g... (cached) yes
checking for gcc option to accept ISO C89... (cached) none needed
checking dependency style of gcc... (cached) gcc3
checking for ranlib... ranlib
checking whether gcc needs -traditional... no
checking whether gcc and cc understand -c and -o together... yes
checking how to print strings... printf
checking for a sed that does not truncate output... /bin/sed
checking for fgrep... /bin/grep -F
checking for ld used by gcc... /usr/bin/ld
checking if the linker (/usr/bin/ld) is GNU ld... yes
checking for BSD- or MS-compatible name lister (nm)... /usr/bin/nm -B
checking the name lister (/usr/bin/nm -B) interface... BSD nm
checking whether ln -s works... yes
checking the maximum length of command line arguments... 805306365
checking whether the shell understands some XSI constructs... yes
checking whether the shell understands "+="... yes
checking how to convert armv6l-unknown-linux-gnueabihf file names to armv6l-unknown-linux-gnueabihf format... func_convert_file_noop
checking how to convert armv6l-unknown-linux-gnueabihf file names to toolchain format... func_convert_file_noop
checking for /usr/bin/ld option to reload object files... -r
checking for objdump... objdump
checking how to recognize dependent libraries... pass_all
checking for dlltool... no
checking how to associate runtime and link libraries... printf %s\n
checking for ar... ar
checking for archiver @FILE support... @
checking for strip... strip
checking for ranlib... (cached) ranlib
checking command to parse /usr/bin/nm -B output from gcc object... ok
checking for sysroot... no
checking for mt... mt
checking if mt is a manifest tool... no
checking for dlfcn.h... yes
checking for objdir... .libs
checking if gcc supports -fno-rtti -fno-exceptions... no
checking for gcc option to produce PIC... -fPIC -DPIC
checking if gcc PIC flag -fPIC -DPIC works... yes
checking if gcc static flag -static works... yes
checking if gcc supports -c -o file.o... yes
checking if gcc supports -c -o file.o... (cached) yes
checking whether the gcc linker (/usr/bin/ld) supports shared libraries... yes
checking dynamic linker characteristics... GNU/Linux ld.so
checking how to hardcode library paths into programs... immediate
checking whether stripping libraries is possible... yes
checking if libtool supports shared libraries... yes
checking whether to build shared libraries... no
checking whether to build static libraries... yes
checking sys/mman.h usability... yes
checking sys/mman.h presence... yes
checking for sys/mman.h... yes
checking wchar.h usability... yes
checking wchar.h presence... yes
checking for wchar.h... yes
checking for stdint.h... (cached) yes
checking for mprotect... yes
checking for sigaction... yes
checking for sigaltstack... yes
checking for siginterrupt... yes
checking for mmap... yes
checking for MAP_ANONYMOUS... yes
checking whether memchr works... yes
checking whether memmem is declared... yes
checking for memmem... yes
checking whether memmem works... yes
checking for C/C++ restrict keyword... __restrict
checking for uid_t in sys/types.h... yes
checking for inline... inline
checking whether the preprocessor supports include_next... yes
checking whether system header files limit the line length... no
checking for wchar_t... yes
checking for unsigned long long int... yes
checking for long long int... yes
checking whether stdint.h conforms to C99... yes
checking whether memmem is declared without a macro... yes
checking whether mempcpy is declared without a macro... yes
checking whether memrchr is declared without a macro... yes
checking whether rawmemchr is declared without a macro... yes
checking whether stpcpy is declared without a macro... yes
checking whether stpncpy is declared without a macro... yes
checking whether strchrnul is declared without a macro... yes
checking whether strdup is declared without a macro... yes
checking whether strncat is declared without a macro... yes
checking whether strndup is declared without a macro... yes
checking whether strnlen is declared without a macro... yes
checking whether strpbrk is declared without a macro... yes
checking whether strsep is declared without a macro... yes
checking whether strcasestr is declared without a macro... yes
checking whether strtok_r is declared without a macro... yes
checking whether strerror_r is declared without a macro... yes
checking whether strsignal is declared without a macro... yes
checking whether strverscmp is declared without a macro... yes
checking whether memmem works in linear time... yes
checking for memmem... (cached) yes
checking whether memmem works... (cached) yes
checking for struct sigaction.sa_sigaction... yes
checking for volatile sig_atomic_t... yes
checking for sighandler_t... yes
checking whether sigaction is declared without a macro... yes
checking whether sigaddset is declared without a macro... yes
checking whether sigdelset is declared without a macro... yes
checking whether sigemptyset is declared without a macro... yes
checking whether sigfillset is declared without a macro... yes
checking whether sigismember is declared without a macro... yes
checking whether sigpending is declared without a macro... yes
checking whether sigprocmask is declared without a macro... yes
checking for sigprocmask... yes
checking whether NULL can be used in arbitrary expressions... yes
checking for ANSI C header files... (cached) yes
checking syslog.h usability... yes
checking syslog.h presence... yes
checking for syslog.h... yes
checking for size_t... yes
checking for working alloca.h... yes
checking for alloca... yes
checking for pthread_create in -lpthread... yes
checking for bcm2835_init in -lbcm2835... no
configure: error: Could not find bcm2835 library - please install libbcm2835
make: *** [config.status] Error 1
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junglecat Newbie * Posts: 7 Re: Innosilicon A2 88 MH/s Scrypt ASIC Miner $3999 « Reply #9 on: August 07, 2014, 09:58:13 AM » Quote from: Forceflow on August 03, 2014, 01:42:36 AM I will say that the machines actually pull way more from the wall than advertised. That being said, they are currently the most efficient. That also being said, you can get 44Mh/s for $799 @1kwh now, so I think your prices probably need some tweaking to sell here (since this audience is more informed). No it doesn't pull "way more" from the wall than advertised and it runs 102-112 MH/s at the pool with the cgminer update. Code: [Select] [2014-08-07 18:02:18] Started cgminer 3.9.0 [2014-08-07 18:02:22] A1 PLL Clock = 1350MHz <== [2014-08-07 18:02:22] A1 PLL Clock = 1350MHz <== [2014-08-07 18:02:22] A1 PLL Clock = 1350MHz <== [2014-08-07 18:02:22] A1 PLL Clock = 1350MHz <== [2014-08-07 18:02:22] A1 PLL Clock = 1350MHz <== [2014-08-07 18:02:22] A1 PLL Clock = 1350MHz <== [2014-08-07 18:02:23] Found chip 1 with 54 active cores [2014-08-07 18:02:23] Found chip 2 with 54 active cores [2014-08-07 18:02:23] Found chip 3 with 54 active cores [2014-08-07 18:02:23] Found chip 4 with 54 active cores [2014-08-07 18:02:23] Found chip 5 with 54 active cores [2014-08-07 18:02:23] Found chip 6 with 54 active cores [2014-08-07 18:02:23] Found chip 7 with 54 active cores [2014-08-07 18:02:34] Stratum from pool 0 detected new block (5s):118.26M (avg):117.49Mh/s (pool):106.0Mh/s | A:14652928 R:340992 HW:87 WU:75763.9/m It will soon do 150 MH/s at less than 1K watts per Innosilicon. Quote Its per chip performance has reached over 1.6MHs to 1.8MHs at only 10W power consumption, which can allow for the unbeatable up to 150MHs per box performance within only 1KW power supply & very quiet fan cooling. The device was designed to be able to tweak to twice the nominal speeds. Go read it on their website and get "informed". « Last Edit: August 07, 2014, 10:07:00 AM by junglecat » At https://litecointalk.org/index.php?topic=21399.0 someone shows a device that works on 1350Mhz after an updated cgminer..... Someone know something about that??
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