Spreading across a pair of 750W, unless the PSUs are pretty tired and/or underperforming, will likely run more efficient than a single 1200W. Efficiency curves typically peak near the middle of the load range so you might squeak a percent or two out of it by loading down 1500W to the 2/3 point over loading 1200W to the 5/6 point.

But if BitFury does it, nobody gets to share the wealth?

BlackArrow still has money? How?

That's all the S2 is, is sorely underclocked S1 - even used the same VRM hardware. Twice as many chips per bank, half the speed and half the power. Underclocking new hardware is really a discussion in arbitrary stock setpoints - when a new ASIC is released, they could say "the stock point is 0.5W/GH but it underclocks to 0.2W/GH" or they could say "the stock point is 0.2W/GH but it overclocks to 0.5W/GH" and nothing really changes (except maybe the retail price). All mining will go the way of economically-efficiently-clocked ASICs; whether that's "underclocked" or not is mostly semantics.

Hey, HF still made a heck of a good chip. It's just too bad they only made about ten of them and forgot to tell everyone that they were months behind schedule until the day they slipped the deadline. Who knows, maybe this guy's got some really good stuff in the works and will keep insisting on a February ship date right up until the end of May.

Also, klondike_bar, pretty sure it's a 15-segment string.

The only issue I've ever had with the S2 was when I accidentally tore up one of the fans at the tail-end of a 16-hour shift getting stuff ready so I could leave for a week over Thanksgiving. I didn't have time to fix it and it shut off for overheating on the one end. Once I put a fresh fan in it, it lit right back up. The thing's been running spot-on with almost zero crash/downtime since... July? Might have been June I fetched it.

I have no complaints about the Tube, as far as hardware reliability (though of the 30-odd in my care for hosting, I started with 5 DOA boards and two of them did smoke VRM controllers, which was an easy fix) - the crap about them is the BE controllers. Of course the 11 Prismas in my care for hosting also haven't had any hardware problems yet, but that may be a statistical aberration? The Prismas sucked balls on BE controllers, but for the most part behave on USB adapters.

In any case, philipma, I look forward to reading your test results. I also look forward to the engineers getting back with some answers. I'm apparently a businessman these days, but I'm actually an engineer and one conversation with good numbers means a lot more than any amount of hard-sell.

Righto, thanks. I doubt anyone goes out of their way to trust my opinions, but I really like Bitmain gear (for disclosure, I own about 15 undervolted S1, run an S2 Kit and an S3) and I can't recommend the S5 until I trust a few things have been taken care of. It'd be really nice to have gotten ahold of one of those evaluation units, but then a thousand other people could say the same thing.

I've still got some questions that I think went unaddressed - besides the holiday I've been phlegmatic and unconscious for most of this week. Regarding the expected hashrates from a 0.8V chip (22GH according to the first-post chart) and 60 chips per machine, why the machine's hashrate is rated at 14% under that. Also what provisions were made to keep node currents stable during chip use fluctuations. One user keeps asking for the ability to disable individual chips, which for a string miner would be a pretty bad thing to have happen but if chips disable themselves, what provision is there for proper currents to keep flowing? Are there any provisions for chips overvolting? Like say, using a server PSU that's reading high and outputting 13V instead of 12 (which isn't terribly uncommon), giving you an 8% overvolt - say one node in your string fails short and now you're running 14 nodes. You're now 15% overvolted on all chips. How is that handled? I'm not really looking for proprietary trade secrets, I already know how I'd do it if I were making a string miner. I just want to know that some of these safety measures were not overlooked. It's entirely too common for string miners to catch on fire - they're a really good idea, but with a few particular tricky details that shouldn't be left up to chance.

Is the punchline VB.Net?

I sat down one morning last week and worked up a rough design for relatively-low-bandwidth (maybe good for 1MHz, which should work for any practical miner's UART or SPI) logic level shifters and a constant-node-voltage current dump circuit which could, in theory, be used to chain any kind of chip with any arbitrary voltage. It's probably just a loose implementation of ASICMiner's proprietary PMS01 chip, which looks to be a pretty nifty device.
We're also contemplating working up a high-current (and hopefully high-efficient) inline regulator to make undervolting string miners easier off existing 12V PSUs. The basic design coincides with some other projects we're working on anyway. Something like that would be handy to strap some S5 (or Prismas) behind here in a few months.

I don't know if the S5 uses isolated or level-shifted comms, or some daisychain implementation like the Bitfury chips did. Haven't scrutinized the PCB photos enough yet to make an educated guess.

Also, the S5 has 15 steps in the chain (30 chips) so 9V would drop to an even 0.6V per node.

Dang. I really hope he used an isolation transformer. That's a buttload of chips too.

Novak and I were chuckling earlier today, wondering how long it would take for someone to ground-isolate and stack three server PSUs, and stack four S5 in series to get 9V per machine. The only problem there will be ground loops on the ethernet cables causing your switches to explode, but it could be interesting nonetheless.

This is the fourth string miner that I know of - the others being the OneString and Yazio (or whatever) boards with Bitfury chips, and the Prisma. I know plenty about how reliable the Prismas are, but not enough about the Bitfury-based boards. (A previous post mentions a fifth design I had not previously seen, so chalk that one up).

klondike_bar's assessment is not entirely correct; the active players in the circuit are voltage and also current. The capacitors at each string node will help balance out brief changes in current (which are natural occurrences with all the switching going on in the chips) to help maintain a constant node voltage, but won't really help much if one of the chips drops out entirely. Suddenly the current path at one node is cut in half, which means that, unless external provisions are made to compensate, the second chip in the node will have to push twice as much current as otherwise expected. This might result in the voltage across that node increasing until the chip is allowing that much current through, which will greatly increase the power dissipation (potentially quadrupling it) on that chip which very well might roast it. The best case would be the chip fails short, in which case you now have an unbroken current path, but with one of 15 nodes out, the rest of your chips' voltages increase by about 7%. If the chip fails open, you now have no current path and the entire board is down.
If, on the other hand, instead of the node voltage increasing until the current draw is in accordance with the rest of the two-chip banks, the current stays low and starves out the other banks, now you have a board which technically works but does not operate stably.
If each bank is provided with an active dummy impedance working alongside the capacitor, the two systems can effectively buffer the node voltages and chain currents to keep every chip functional. If one node's voltage starts to increase beyond what capacitor ripple can handle, this indicates it's not passing full system current and the dummy impedance can open up a bit to allow excess current through, keeping the system operating and the local node voltage at the expected value. If there's a stably controlled system like this in place, I'd have a lot fewer qualms about running one of these boards (we're actually toying with designing one of our own using that principle). I don't really trust unregulated strings as they are, but if there's some node-level regulation at least, it's certainly got more potential for stability and reliability than just trusting the chips to all operate within a narrow tolerance of "identically".

Another thing that's probably not something anyone wants to do, but could greatly assist the reliability of a chained design, is individually fused chips (alongside a controlled dummy impedance). If one fails short and overcurrents, the fuse blows and now that portion of the bank is an open circuit. Your dummy impedance will have to take its full share of the current, so with a chip like BM's where it's expected to draw around 9W you'll need a well-sinked dummy but that's not difficult. If an entire bank goes out, the dummy impedance will have to take the entire load, but it avoids the problem of overvolting the rest of the chain.

That's why I've asked about parallel current paths (like the FETs on Prismas and such), which can pick up the load slack if a chip drops out. Of course, you also need to not have daisychained comms for that to work perfectly.

Each board has 30 chips; each chain is 15 pairs. At 12V it divides to a Vcore of 0.8V per chip.

So what you're saying is "if you don't want to listen to jackasses flailing madly about nothing instead of discussing the product release, please ignore the thread started to discuss the product release"? I believe that is stupid.

Yeah can we um, talk about the product instead of various pissing contests? I've still got some questions about the advertised chip and machine specs. As long as accurate numbers are presented, I don't really care who pays who to tell who about what. Just give us accurate numbers and let them speak for themselves.

So a 15s2p string. At 12V that gives 0.8V per chip, and an expected hashrate (according to your charts) of 1320GH - about 14% more than the listed 1155GH. Where's that come from?

Also, how susceptible are your chips to under/overvolting from ripple currents when some chips in the string underperform? Is there a parallel current path to loop around underperforming nodes to keep load currents and node voltages relatively constant? Just wondering about stability and such.

Better check the keying on the connectors if they're going to be used on GPU. We got a batch of ends in some time ago that, either due to a hardware-spec error or some oversight somewhere, weren't keyed right for PCI-e standard. They've worked on every bitcoin miner we've ever plugged them into save one (Bitfury M-board), but the top center block is not keyed correctly so they don't quite fit in a proper GPU. It can be whittled just a bit if necessary (and I have done that on a few), but as the cable manufacturer technically I can't recommend that method to end users. Not saying it's the case, just saying it's worth checking just in case.

Lifting the inductors (the big grey squares) should physically disconnect power to the low-voltage side of the board, which can be a problem if FETs and other things fail short and fry your ASICs. I've seen a lot of dead miners with that problem. As for the PCB, depending on what copper still exists in different layers, that could be a relatively permanent fire hazard. Looks like the high-side power traces are mostly not in the top layer, so it won't be easy to cut them if you want to kill power specifically to that module. I really like it when manufacturers fuse-protect each VRM in a multi-VRM setup like that (which, in truth, almost none of them fuse anything anywhere), since it avoids almost all of the catastrophic-hardware-failure problems the customer will ever see.