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I know, but I would like to be able to control this custom designed enterprise solution to suit my setup.
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It's a fact, lightbulbs used to last 2500 hours, then the manufacturers agreed they would guarantee 1000 hours... Ink jet printers for example have electronic chooking once the pad soaking up the ink gets wet, you can install software that ignores it. I have stopped buying "consumer" products. Professional gear doesn't have fail counters and are built to last.
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I think you need to wakeup, every product in your home has been designed to break after a certain time after your warranty expires.
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Ok, could you add a zero error rate command... that lowers the frequency until error rate is = 0.00% forever? I understand it's bad for business if the cards never break, because then we wont buy new ones, but we would like to be ABLE to control the heat. It should be easy no? Basically can you try to add anything for the passive community to control longevity. |
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ztex can we please, with sugar on top, get a -f XXX commandline flag that hardcodes the frequency so that we can underclock the chips this summer?
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Also catfish: please post the rig in FPGA Photo thread later, can't wait to see this thing!  |
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 They go with the hook through the board and the spring on the metal wing end. Also you have to turn one of the wings so it doesn't poke the big black square component (not because it's hot, but because you can't properly center the heatsink otherwise), but you'll notice; it only goes one way. Also I used pliers to gently narrow the hook a bit so I didn't have to force the hooks through with too much pressure. I would use some quality grease though, not the zalman one. How are you going to cool these, passively? |
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Ah, sorry it was related to MPBM.  |
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TheSeven, nice summary and thanks for working on the MPBM support for ztex.
Are you getting high CPU load for the ztex boards with MPBM? Ztex's java process doesn't use the CPU much and will run on an atom. There was a bug during firmware programming that caused high CPU loads that was fixed.
Well, I said relatively high. It's like 5-10% per board on a dualcore 1.8GHz atom, and most of that can probably be done way more efficiently in C or even Java. It's just a damn lot compared to those <1% needed by the SimpleRS232 or Icarus protocol. No, your setup is buggy, my 5 card cluster has 0% CPU usage on D510MO Atom with Java 1.6 on Suse. |
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Are those ztex boards?
Are you running at full speed with passive cooling?
I'd ideally like to run passively albeit with X6500s.
Yes, 1x3 and 4x3N, and it's not completely passive. You see that knob/sill under the edge of the windowboard, that's an outside air inlet. So I have air blowing onto the heatsinks. They are running at 3x216 and 2x208. I use a D510MO with SSD and PicoPSU as computer, so my whole digital setup is completely silent! I think that without the active cooling they might run at maybe 3x208 and 2x200 instead, but the wear/lifetime would be very different. We'll see how they run during the summer (if the balcony door or a window is open, there's no airflow) and if there is a problem I'll add some kind of active cooling. |
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Hi, just a place share and discuss how we setup our FPGAs. I'll start by posting an image of my passive setup:  I'm also looking at providing active cooling via an aquarium pump. |
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So the entrance is circular and the exit is a very thin and long rectangle.
Maybe you should have a look at cross flow fans? Hm, no but thanks for the suggestion. I'm actually thinking about aquarium air pumps now for the "octopus" solution... but I know the final solution will be convection, even if it means wearing my chips a little. |
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What I have noticed using 10 board vertical stacking is that a thermal stratification occurs inside the case. Not the air, but material and pcb. Higher boards have higher temps. Horizontal might be a more efficient method if running in a high ambient temp area. I put fastest of the boards in top slot and installed the rest in order going down. 10 boards running in cluster mode have had a combined speed of 2077.9 MH/s for weeks now on P2Pool.
Yes, It's best to not stack vertically or inline (Turbor). Best is bottom up, heat rises. Another solution to the above is to build a web of small pipes, one to each heatsink. Like an inverted octopus vacuum cleaner! The point here is that you don't need a large area of air if your air is fast and/or cold. |
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Totally agree... One big silent fan instead of lots of humming small ones. I need something like this:
/ * FPGA
/ * FPGA
FAN= * FPGA
\ * FPGA
\ * FPGA
Like a big vacuum cleaner piece. Wonder if it exists?
That wouldn't work but something like this would: ______ F FPGA A FPGA N FPGA ------- and 2-3 side by side. Depending upon the fan size, this would create a 2x2 or 3x3 box, depending upon spacing ofc. That funnel would fail to work because too small pressure differentiation and airflow speed, for the funnel to force the airflow to spread. Pressure being the more important factor. Yes but the funnel would slim out on the other diagonal, to even the airflow. Like so: Topview: / FPGA - FPGA FPGA FAN FPGA FPGA - FPGA \ FPGA Sideview: - \ FAN FPGA / - So the entrance is circular and the exit is a very thin and long rectangle. |
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Totally agree... One big silent fan instead of lots of humming small ones. I need something like this:
/ * FPGA
/ * FPGA
FAN= * FPGA
\ * FPGA
\ * FPGA
Like a big vacuum cleaner piece. Wonder if it exists?
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Yup, but for me passive cooling computing means so much more than MH/s... silence to hear yourself think! I have 1GH/s and that draws 40W with ZTEX.
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Silent? Hm, I run my D510MO and 5 x 1.15x passively. That's silent! You just hear the chips chirp as they meet hard work. You can actually hear what the CPU is doing... actually very useful when you have a server and it's getting lots of load; you hear it... specially when you wrote the software, performance tuning by ear!  |
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I'm not opposed to letting you know our sales figures. We've sold 100 X6500s so far, and have another 100 produced that will start shipping very soon.
Thumbs up! |
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Yes, but if there is a bug, your chip is toast (f.ex. say the firmware = software raises the frequency to 400Mh = bye bye chip). Compare it to Intel vs. AMD a few years ago; Intel has always had hardware temperature shutdown of it's chips while AMD, well many friends have toasted their CPU because of software/fan malfunction. If you are serious you have temperature hardware control or at least temperature software control.
Of course, you get what you pay for.
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Ok, I'll live with it.
I didn't quite get that the error/frequency mechanism was in the firmware. I would make the Java code decide frequency instead.
It's weird that there is no protection on expensive hardware yes! From xilinx and from ztex, would be a good addition to the Artix-7 series.
What about the "Algorithmically placed FPGA miner", will you look at that or is it doomed to fail too?
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