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2013-06-17 22:37:11: Listener for "6850": stratum.bitcoin.cz:3333 17/06/2013 22:37:11, Verification failed, check hardware! (0:0:Barts, ce5273db)
2013-06-17 22:37:13: Listener for "5850": stratum.bitcoin.cz:3333 17/06/2013 22:37:13, Verification failed, check hardware! (0:1:Cypress, 727d93c7)
2013-06-17 22:37:20: Listener for "6850": stratum.bitcoin.cz:3333 17/06/2013 22:37:20, Verification failed, check hardware! (0:0:Barts, a2952421)
2013-06-17 22:37:29: Listener for "5850": stratum.bitcoin.cz:3333 17/06/2013 22:37:29, Verification failed, check hardware! (0:1:Cypress, 70fe5733)
2013-06-17 22:37:29: Listener for "6850": stratum.bitcoin.cz:3333 17/06/2013 22:37:29, Verification failed, check hardware! (0:0:Barts, 0df11781)
2013-06-17 22:37:31: Listener for "5850": stratum.bitcoin.cz:3333 17/06/2013 22:37:31, Verification failed, check hardware! (0:1:Cypress, 0558f90a)
2013-06-17 22:37:37: Listener for "5850": stratum.bitcoin.cz:3333 17/06/2013 22:37:37, Verification failed, check hardware! (0:1:Cypress, 1e22764a)
2013-06-17 22:37:40: Listener for "6750": stratum.bitcoin.cz:3333 17/06/2013 22:37:40, Verification failed, check hardware! (0:2:Juniper, 00d0bf18)
2013-06-17 22:37:44: Listener for "6750": stratum.bitcoin.cz:3333 17/06/2013 22:37:44, Verification failed, check hardware! (0:2:Juniper, a415432f)
2013-06-17 22:37:44: Listener for "6850": stratum.bitcoin.cz:3333 17/06/2013 22:37:44, Verification failed, check hardware! (0:0:Barts, fb1cb804)
2013-06-17 22:37:45: Listener for "5850": stratum.bitcoin.cz:3333 17/06/2013 22:37:45, Verification failed, check hardware! (0:1:Cypress, 9e719e0e)
please help me diaganosis this
Probably a Catalyst problem. Are you using 12.8, and what driver version? I would backoff to catalyst 11.11 for the older graphics cards. This worked for me. |
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Fix for the infamous GUIMiner interface not showing up...
I had the same problem that others have had with the interface not showing up (it appears in the task bar, but the window never materializes). The usual fix (using keyboard shortcuts to move the window) did not work. The window was not hidden or otherwise out of sight. It simply was not there. I figured out that the culprit is the AMD APP SDK v2.8 installation.
I have verified this on two completely separate systems (both Windows 7 x64 - but no other SW or HW similarities). I can fix the issue by uninstalling SDK v2.8 and installing v2.7. I can reproduce the problem by uninstalling v2.7 and re-installing v2.8.
I am guessing the program hangs before the window is created when it polls the 2.8 OpenCL SDK drivers for devices, etc... (Just a guess).
I don't know if this will help anyone else, but I wanted to share in case is does.
I have Win7 x64 box as well. I uninstalled SDK v2.8 and installed v2.7, but didn't have any success. The windows is not hidden. The icon is in the system tray, but if you hover on it with the mouse it quickly disappears. You also can't alt-tab to the application. Any other ideas? I'm running GUIminer as administrator. |
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So, looking into this whole mining with fpga system, and this code you people are working on, what is the required Logic cells/gates required for a full roll out? also whats the smallest unit you can get it running on? (the bare minimal for a half roll out (what ever you call it?)) I just want to dip my toe into the FPGA mining with a cheap and nasty chip set  just tell me to piddle off else where if its the wrong spot to ask AJRGale, I think you'll want at least a Spartan6 LX150. This is the cheapest device I would use. I would only run a fully pipelined implementation -- one that can do one hash per clock cycle. If you can get a hold of a Kintex7 or Virtex7 board you'll be a lot better because you can instantiate more miners. fpgaminer has posted a lot of useful code on github. I don't speak Altera, so not sure on specific devices. |
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IIDX, The addressing would be constant, so no decoding would be needed. They would be tied off to constants. The 2.0ns is the clk-to-out time for a data output. Since all outputs are in parallel, (each BRAM configured as x72, and grouped together to give very wide access),the individual BRAM bit delay would not change. No demuxing of outputs would be necessary. The number of BRAMs needed is only half what you show, since you can use both sides (Port A & Port B) independently (assign each side a fixed, but different address). Yes, you are right though re getting the data from the BRAMs to the LUTs needed for the computation. There is a routing delay which is probably too large. Obviously this is not the optimum solution, only bringing it up as a last resort if available flip flops have expired. Regards, ihtfp I think the problem is linking 11 BRAMs together requires a lot of LUTs for address decode/routing since the BRAMs are arranged in columns throughout the chip. Plus linking 11 together would probably result in a minimum period much higher than 2.0ns (2.0 ns is for 1 BRAM I think). So, you would need 128 (hashers) * 11 (BRAMs) for one pipeline stage = 1408 total BRAMs. Of course, you're not suggesting you use BRAM for all the delay. However, I think the slices you would sacrifice to connect the BRAMs and create their address logic would be more expensive than just using the built in FFs or DMEMs (plus the speed hit). I'm hoping by floor planning each hashing module I can get to quick speeds. Currently the logic delay I am facing is only around ~2.0 ns, with the routes taking the rest. So with some nice routing I would hopefully meet my target. The V6LX130 isn't even as big as the S6 150, but at least is has DSP48s. I may also need to cut down the PCIe link from 4x to 1x and reduce its performance settings to regain some of the space that is being used up. IIDX Looks good! I tried to do the same thing on a V6 LX130T (use almost all DSPs and pipeline the rest of the LUT adders), but there aren't enough registers in that device for tx_w and tx_state delays  . so many 512 and 256 bit registers... If you are short on flip flops, have you considered using the BRAMs? You would need 11 primitives (there are 264 in the LX130T) to make a by 792 bit wide memory. You can set the BRAM to 'write first' mode, which will echo the data to the output. The clk-to-out for unpipelined BRAM is ~2.0ns...slower than FF. Since the BRAMs are dual port, you can use both sides of the memory (with different locked addresses), you can get enough storage for 48 stages of a fully unrolled algorithm. I've never tried this, but was just thinking of how to make use of all the unused BRAM laying around. I usually run out of LUTs, but need to rethink if this is worthwhile with the DSP48 implementation. |
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Looks good! I tried to do the same thing on a V6 LX130T (use almost all DSPs and pipeline the rest of the LUT adders), but there aren't enough registers in that device for tx_w and tx_state delays . so many 512 and 256 bit registers... If you are short on flip flops, have you considered using the BRAMs? You would need 11 primitives (there are 264 in the LX130T) to make a by 792 bit wide memory. You can set the BRAM to 'write first' mode, which will echo the data to the output. The clk-to-out for unpipelined BRAM is ~2.0ns...slower than FF. Since the BRAMs are dual port, you can use both sides of the memory (with different locked addresses), you can get enough storage for 48 stages of a fully unrolled algorithm. I've never tried this, but was just thinking of how to make use of all the unused BRAM laying around. I usually run out of LUTs, but need to rethink if this is worthwhile with the DSP48 implementation. |
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hi, total newbs here.  just wanna ask since i got this fpga for free (my friends bought it and decide not use it for whatever reason), could i use this for BTC mining? Genesys™ Virtex-5 FPGA Development Board http://www.digilentinc.com/Products/Detail.cfm?Prod=GENESYSthank you for your kind answer. regards, hi, total newbs here. just wanna ask since i got this fpga for free (my friends bought it and decide not use it for whatever reason), could i use this for BTC mining? Genesys™ Virtex-5 FPGA Development Board http://www.digilentinc.com/Products/Detail.cfm?Prod=GENESYSthank you for your kind answer. regards, Probably you can use it, but it will be slow, because 50k logic gate is not enough to use fully unrolled pipes. As i know Spartan-6 LX90T produces 90MH/s, and it has almost twice gates. I wouldn't use it. This FPGA only has 28k flip flops. The Spartan6 LX150 has 184k for comparison. As Reggie0 said, you wouldn't be able to use fully unrolled logic. |
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Hi,
This looks interesting, but I don't think it will be able to compete with the Avalon ASIC. The 64 cores are certainly nice, but a single Avalon ASIC can do 275 Mhash/s.
Even if each Epiphany-IV core can produce one full hash every 640 clock cycles, it will only generate 80 Mhash/s. I'm more of an FPGA/ASIC person, so I'm basing the 640 clock cycles on 10 clocks per individual SHA256, and 64 rounds per hash, which might even be low.
I think it is hard to compete with the Avalon ASIC custom chip, which was custom designed for mining.
Regards,
Pat I see your point, I'm quite new to the world of ASIC and FPGA's and I so I thought this could compete. I will still be using this as a server and a second board for a custom PC. Also can ASIC's run applications or are they designed for mining? An ASIC is just a custom computer chip, designed for an intended application. http://en.wikipedia.org/wiki/Application-specific_integrated_circuit |
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Hi - I'm late to the party, but want to do FPGA/ASIC mining.
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Increasing posting count... Joke: Where does the general keep his armies?
In his sleevies.
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Hi,
This looks interesting, but I don't think it will be able to compete with the Avalon ASIC. The 64 cores are certainly nice, but a single Avalon ASIC can do 275 Mhash/s.
Even if each Epiphany-IV core can produce one full hash every 640 clock cycles, it will only generate 80 Mhash/s. I'm more of an FPGA/ASIC person, so I'm basing the 640 clock cycles on 10 clocks per individual SHA256, and 64 rounds per hash, which might even be low.
I think it is hard to compete with the Avalon ASIC custom chip, which was custom designed for mining.
Regards,
Pat
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