I don't think they are interested in demand - they should make miners for themselves. They race with other ASIC manufacturers. So the only limitation is their assembly capabilities. Which they will increase as soon as they can.

Until they reach a point where other "regular" miners are virtually eliminated (1,000 TH/s for each ASIC manufacturer?, 3-5 PH/s total?) - then it would be advisable to form a kind of cartel with other ASIC manufacturers to stop fighting each other, stop manufacturing more miners, wasting money and electicity, divide the market (the total hashing power) equally (or not) and keep mining until 2040

P.

That looks almost like a classic "societas leonidas" - customers "invest" their money into a new company. They take all the risks - like BTC price crash, company's inability to design a working ASIC, competitors designing ASICs faster and driving difficulty up, etc. In such case company just declares bancruptcy and customers get nothing. In case of a success company owners get all the shares, all the technology, manufacture as many ASICs as they want and "print" as many BTC as they can. Customers get their ordered devices (which are much less profitable than in the beginning) - so that's I call it "almost" a leonine company. Customers take all the risk and a tiny profit, company owners take no risk and most of the profit.

And it's legal!

In one word: Brilliant!

P.

Hi,

I have one suggestion - now there's possibility to set difficulty increase rate in percent. I think that the difficulty will rise in linear fashion now - the ASIC manufacturers have a constant rate of releasing new devices that depends on their manufacturing capabilities (it doesn't matter if they manufacture them for the customers or for themselves), so the total hashrate will rise linearly (on average). There will be changes in that increase rate - if one of these ASIC companies opens new manufacturing facilities. But it will be still close to linear.

So it would be nice to set daily increase rate (like 1,000,000 increase in difficulty per day). Calculator could suggest the value basing on, say, 7-days average.

P.

And won't have. Why should companies that invested millions in ASIC design sell their money-printing-machines instead of just using them to print money?

P.

They don't have to mine on customer's hardware, they could make hundreds times more of their own hardware. But they may also not send miners to customers to keep all the profit for them.

P.

Well, it's very risky 6-8 months. Current lead-time for Artix-7 from the manufacturer is 2 months. The difficulty in 2 months? Currently it's rising at 1-1.5M per day, so it should be around 70-100M then. So the ROI will be counted in years. And who knows what happens during that time? The ASIC manufacturers will keep their arms race, the difficulty will rise even more and the ROI will never come. Not thinking about actual income.

P.

The key difference is that you could make your own miner on a CPU, on a GPU and even on a FPGA (I recently made a miner with 4 Artix-7 FPGAs mining at 1.6 GH/s for $650). But you can't make yourself an ASIC miner, that costs too much. So you can only beg companies like Avalon or BFL to sell you some. But it will be more profitable for them to mine on their own than to sell chips/devices to you (constant, controlled income vs one shot). What if they stop selling miners and mine on their own? We'll have to shut down our miners after some time and whole mining will be controlled by 3-4 ASIC companies. That's the end of mining.

I gave up my FPGA project - even if it's cheaper than ASICminer - because at current difficulty (and difficulty increase rate) the ROI rised to 6-8 or even more months. I have better investments than that :/ I'll leave these two PCBs I already made running and forget the whole thing.

P.

Hi,

I connected MPBM through RS232 to a custom board running at 400 MH/s (Kintex 325) and I'm getting 9% cancelled shares. Is that acceptable value? Does that mean that I loose 9% of my computing power?

I'm wondering if it's better to connect two such boards to two RS232 ports or design a new dual-FPGA board that shares work between two FPGAs - in the first case the canceled rate should remain the same and in the second case it should be halved. But does that matter? Or is there any other way to fix that problem?

P.

I used 2-stage adders, because DSP adders worked in 2 cycles and I didn't want to debug too much. IP core generator recommended 3 cycles for the best performance - I'll try that next.

After replacing dsp_e, dsp_wp and dsp_t1p I got 46% DSPs used - so it's enough to fit two cores.

I compiled fpgaminer's DSP code on A7 200 and I got 356 MHz on -3 grade, 311 MHz on -2 grade and 262 MHz on -1. The -3 variant only exists in extended temperature version, so it's much more expensive - so the -2 is the best choice in my opinion.

The usage was 20% slice logic, 34% slice logic distribution and 92% DSP.

What were your results? I.e. what maximum clocking do you have without DSP?

Now I'm trying to replace some DSPs with adder IP core - I think best candidates are these that don't use PCIN input (because they are simpler), like dsp_e, dsp_wp and dsp_t1p. When I replaced dsp_e with adder I got 302 MHz (-2 version), 23% logic, 37% distrib, 75% DSP. Then I replaced dsp_wp: 271 MHz, 24% logic, 38% distrib, 63% DSP. Compilation took over 5 hours, while it takes 30 min when using only DSP. Then I replaced dsp_t1p and the compilation takes ages to complete (it didn't complete yet)

The estimation is that DSP usage will be 49%, so theoretically I should be able to fit two such cores. Even if I have to lower the clock to, say, 200 MHz then total output would be 400 MH/s, which would be better than 311 MH/s with one DSP-only core.

Are they really shipping? They promise to ship by end of April...

I also think that their intentions were sincere... but apparently devices didn't work as expected. I already saw that they lowered MH/s rate (Google still can find some old webpages on theis site). Perhaps too much current, perhaps too high temperature

Congratulations

Hope it will stay there until my FPGA board arrives

OK, so it's my first post