Has anyone received any K16s without ASICs? I know several people have suggested that. I could use one or two for Gen2 ASIC development.

On a related note. Anyone willing to part with a fully functional K16? Once again, for Gen2 ASIC development. I would be willing to be lightly gouged on price. If so, please PM me ASAP.

My goal is to send SB new PCBs and ASICs (and three other part replacements) and have those assembled.

I understand the POV of the Avalon haters here, (I am one as well) but just trying to be pragmatic.

[And yes, also understanding that any assembly refunds would be in USD, not BTC.]

As one of the many people here who have paid for assembly (and test) but who got a refund on ASICs I can’t help but think about revising the Klondike design to use the new ASICs.

Looking at the design, it looks like the changes would be minimal - The PCB would need to be changed because the pinout has several changes, the oscillator would need to changed, a few resistors would need to be changed to generate a DVDD of 0.9V (instead of 1.2V) and the PIC code that sets the clock control register would need to be changed, and the golden nounce offset would need to be changed. This does not seem like a lot of work.

I know a lot of people after having been bit by Avalon refuse to do business with them again, but it seems the A3256 ASICs are readily available - in stock in the states, not pre-order. At 0.024BTC per chip they are less than a third the price and 4 times the performance as compared to the first generation A3255. The power requirements are comparable as well.

It looks too me like the ROI on the incremental cost could be achieved in about month.

What do people think?

A question: I’ve been away from this thread for a while, what is the current state of the Klondike design? I know I2C chaining and USB Bootloading are not yet supported, but is it working with all 16 ASICs? Where is the archive for the most recent, up-to-date version of the design?

I also did not get the email. I got a PM telling me the email bounced - they had an incorrect email address. I replied to the PM and also sent an email yesterday - but still have not gotten the form.

…and 10% + 5% = 15% total markup.

I’m not saying it’s profit. I’m not making any value judgements - I’ve read the whole thread, I know work is being done. I think SB is being generous. I’m just saying it’s a total overhead of 15%, 5% of which is not incurred if you don’t cancel your order.

We do agree that he is not refunding half of the original 10% as some have suggested, right?

Funny

Good point, except that you canceling your order is the reason the transaction isn’t completing. And canceling your order wasn’t even an option when you made the investment.

When we made this investment we all agreed to:

And the Avalon website says:

"made to order from TSMC foundry, this also means no refunds”

So SB planned on there being no possibility of refunds and that planning enabled us to make this investment at all. Without it this thread wouldn’t exist. I’m guessing that like me, you chose this group because of the expedience which SB promised - a promise enabled by the assumption that he could pay to expedite.

Then Avalon changed the rules mid game to invalidate the assumptions SB relied on to enable the service you chose and SB is doing (what many here believe to be) the best he can to accommodate that change.

You already agreed to the 10%. If you don’t want to pay the extra 5%, don’t cancel your order. Your choice.

[Note: Some have suggested the total overhead paid to SB is only 5% after cancellation. The chips cost SB .078BTC each - he charged .086BTC, but is only refunding .081BTC. Sure looks like 15% to me.]


Edit: Added some detail regarding refund percentage.

Well there’s your problem right there - you’re thinking of this as a retail transaction. It isn’t. It never was. You were told repeatedly that it wasn’t. Think of SB as a broker - that’s much closer to the actual situation.

A couple thoughts:

1) Surely the number of refund requests will not exactly equal a multiple of 10K. What will happen to the remainder? Clearly, some refunds will not be processed.

2) I’m wondering how many later batch purchasers have not paid for assembly but would be willing to if given the opportunity to move to an earlier batch - especially if rumors of impending shipments of ASICs are true.

I believe steamboat will do the right thing, a fair thing, regarding refunds on assembly - his past performance has been a clear demonstration of this - even if some here are too impatient for his methodicalness.

However, if his situation does not allow him to come through (i.e. he has sunk funds into infrastructure that is not recoverable), could we not solve the situation in some cases ourselves? I’m suggesting purchasers of earlier batches not request ASIC refunds but sell their assembled K16s to later batches of chip only buyers who claim a refund on their chips in order to fund the purchase of assembled miners. I’m hoping that the silence from SB on this matter is him trying to organize a similar solution. If such a thing is possible it is a very complex problem that depends on how many of which type of order was received and in what order - and in the end, as with refunds, not everyone would get what they want.

Thanks so much, it looks like you guys are the first to actually receive sample chips!

I believe BkkCoins has yet to receive any sample ASICs. Maybe you could send him one or two ASAP priority. I’m sure I’m not the only one here who would be willing to help pay for shipping and reimburse you for the parts - or replace them from a later sample shipment - I’m expecting samples from steamboat batch #2.

I also would like to help with testing, but BkkCoins really should be highest priority.

Drew

I’d love to check out his design philosophy, anyone got a link?

I think there's enough inertia in the current migration to ASICs to drive difficulty past 100M this year. So much of the cost of hardware is not ASIC, so I don't think Moore's law will help for a while.

I guess it depends on the value of the currency.

Am I wrong, but doesn't mining end around 2040?

Actually, I think quantum computers becoming viable will end the effectiveness of many crypto systems - including bitcoin.

I wanted to talk about this, bit didn't want to pollute this thread:

Will the bitcoin arms-race end with this generation of ASICs?
https://bitcointalk.org/index.php?topic=215394

This came up in a different thread, and I wanted to talk about it, but not polute that thread, so, here I ask:

Does anyone think there will be another round in the bitcoin mining arms-race after ASICs have saturated the market?

I can’t see it. I think after ASICs are done flooding the market the difficulty will be so high there will be no way to justify purchasing mining hardware. Only people who’ve already made the capital expense will be mining - and some of those will not recoup their expenses - at least not for a long time.

I think this will happen on the first generation of ASICs from the current vendors.

Anyone see it working out differently?

Actually, I don't think the math supports it. At current difficulty should be about 8K per month.

BkkCoins,

I just put another BTC in your OScope fund. Maybe if you get enough extra you could get more than two channels. Just a suggestion.

I have a question about the design: How are you generating the ASIC resets? Is it driven by the PIC? The Avalon design of one RC per ASIC seems to me the worst possible design - more components for inconsistent resets per ASIC.

drewh

That seems reasonable.

Sorry to change the subject from Heatsinks.

I'm a little concerned about the plan for reading RESULT using the ESAUSRT. It seems like a nice hack but what happens if the serial port gets into a bad state - if an extra clock edge is caused by a reset, noise, or a result collision, and the framing comes out of sync - the serial port's bit count is wrong.

I agree that result collisions will be rare enough that they can be ignored - as long as the failure mode is simply a dropped share, but if the failure mode is that it stops being possible to get a valid result until a system reset, that would not be acceptable. It could also be very difficult to debug.

The solution might be as simple as a periodic process that detects that the serial port is in a bad state, has been for minimum amount of time, and does a firmware reset of the port to correct the situation.

I've seen this type of problem in other designs and just wanted to make sure you were aware of it.

Some people have asked about the FPGA bitstream. It makes sense that the FPGA bitstream would be one of the last things they provide in order to work out any bugs. It could be changed very last minute.

On the other hand, it should be noted that they want to keep the bit stream to themselves. Do we know that they don’t mind completing with others using their reference board design? They might have just released the design as a form of documentation with no plan of allowing other to use it as a competitive product. Technically this is very easy. The Spartan 6 allows its bitstream to be encrypted - this makes it impossible to steal the bitstream.

Oh, and BTW, I know others are designing board which require no FPGA, but until we have communication protocol specifications we don’t know if that approach will work, or is even possible.

I don’t mean cry the sky is falling, but do we actually have a commitment on their intention with the ref board release? Personally, I’m planning on using the klondike design, but wanted to be clear that there are still risks.

Drew

> I guess the question now is, how much of a premium are you guys willing to pay for fast turnaround?

I guess that question is best asked right before the orders are placed, when we have a better idea what the difficulty rate is and what the time is worth.