Thanks for the explanation.  Would the large page support be irrelevant for GCN assembler code that loads uncacheable data like the ethash DAG using FLAT_LOAD_DWORD with the SLC and GLC bits set?  By bypassing L1 & L2, that should mean skipping the access to the tag RAM and the page tables.  I haven't actually tried it myself yet, but comments by Wolf0 and zawawa seemed to say it was actually a bit slower.

I was confused by the comment about page size, since the AMD GCN Whitepaper claims "Like the L1 data cache, the L2 is virtually addressed, so no TLBs are required at all" on pg 10.
https://www.amd.com/Documents/GCN_Architecture_whitepaper.pdf