Hi,

I already posted twice, but now I can't :-( Is this "newbie" policy recently new?

Anyhow, I'm helping with FPGA miner implementation (take a look at my posts) and my github contributions
https://github.com/udif/Open-Source-FPGA-Bitcoin-Miner/network

I just uploaded a new "upload" branch on my fork of fpgaminer's code.
The code now supports another parameter, CONFIG_MERGE_LOG2.
This allows you to drop some of the registers between pipe stages.
Warning - code has not been tested yet - this is just a preview
I'm having some issues with my FPGA card, so I couldn't test it yet.
In addition, the golden nonce adjustment isn't fixed in this code yet.

For example - using existing code:

using CONFIG_LOOP_LOG2=3 and CONFIG_MERGE_LOG2=0 creates 8 stages that takes 8 clock cycles each (for each SHA).
On my EP3C25, this took ~23K LEs, 14.5K FF's, and achieved ~60MHz.
A new result is received every 8 clock cycles ~7.5MH/s
This is equivalent to the old code.

using CONFIG_LOOP_LOG2=4 and CONFIG_MERGE_LOG2=0 creates 4 stages that takes 16 clock cycles each (for each SHA),
On my EP3C25, this took ~13K LEs, 8.5K FF's, and achieved ~50MHz.
A new result is received every 16 clock cycles, or ~3.1MH/s

Using the new code:

using CONFIG_LOOP_LOG2=3 and CONFIG_MERGE_LOG2=1 creates 4 stages that takes 8 clock cycles each (for each SHA),
but each stage is equal to 2 regular SHA stages.
On my EP3C25, this took ~17K LEs, 8.5K FF's, and achieved ~40MHz.
A new result is received every 8 clock cycles, or ~5MH/s

As you can see, the new option gives more size/speed options.

The verilog code was updated on my fork of fpgaminer's git, and seems to be working under the simulator. I will try on real HW later today.
You should now be able to fold the 2x64 pipe stages to 2xN stages where N is 1,2,4,..64 (for N=64 it behaves as the original code).
Ofcourse folding the HW pipe into loops means that it will run 64/N times slower.

I was able to fit an EP3C25 at >90% capacity with N=8.