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hi every one
our team is looking to find a way to mine ethereum using a FPGA or another suitable Alternative way.
Ethash algorithm contains DAG file so it needs a memory (~ 2GB, that's a lot more than any FPGA's BRAM), by the way increasing the difficulty made mining harder so we need more bandwidth than a regular FPGA chip, in this case, we are trying to know that is there any way for FPGA to have a parallel processing to achieve more bandwidth and hash rate ?
to solve the memory problem we need to use RAM for fpga's but is there any way to have parallel processing (several fpgas) with just one main RAM to decrease the cost ?
our team is looking to find a way to mine ethereum using a FPGA or another suitable Alternative way.
Ethash algorithm contains DAG file so it needs a memory (~ 2GB, that's a lot more than any FPGA's BRAM), by the way increasing the difficulty made mining harder so we need more bandwidth than a regular FPGA chip, in this case, we are trying to know that is there any way for FPGA to have a parallel processing to achieve more bandwidth and hash rate ?
to solve the memory problem we need to use RAM for fpga's but is there any way to have parallel processing (several fpgas) with just one main RAM to decrease the cost ?
Hi this board maybe interesting for you https://www.bittware.com/fpga/xilinx/boards/xupvv4/#datasheet
It doesn't contain the GDDR5, but contain DDR4 and it has ultraBRAM
So you can solve memory problems designing the new board with like this chips to solve the memory bandwidth problem
https://www.xilinx.com/support/documentation/white_papers/wp485-hbm.pdf
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01264-stratix10mx-devices-solve-memory-bandwidth-challenge.pdf
I'm also interested in design IP core for ethash, analyzing the architecture of ethereum, haven't found yet any problem why it can't be implemented in FPGA SoC
