Found it, thanks.

131 on MintPal vote page..
What about poloniex?

Where can I buy SFR?

1942/6= ~323 -> 160-164MHz per chip, which is very low.  I've played 4MHz to 8MHz more on spartan grade 2 clones with older v3 bitstream. With latest bitstream I am able to hit 200MHz without HW on grade 3 chip, with slightly R12/R13 mod.

You can also try manual frequency clocking for each ztex separately to find good settings.

BTW, there were two revisions of original 1.15x with different R12 value, so core voltage differs +/-0.02V.

If you get problems with IMPACT loading bitstream to CM1, try like CM1 wiki says:

https://en.bitcoin.it/wiki/CM1Quickstart, but remember about hashvoodoo spartan-3 controller firmware.

I've got that problems with CM1 too in IMPACT&Xilinx JTAG and don't know why? Too long JTAG chain or bad PCB design?? Who knows that?

Did you see Skeincoin thread? They're probably going on cryptsy soon... Skeincoin is nearly same as Blakecoin, but has no FPGA support. And that's at least one point more for Blakecoin. Do more advertise on your local country forums. I've done that already...

BR

Who decides which coin gets on exchange?

Improved Ztex 1.15x bitstream (168-180MHz) will be available soon (max tomorrow).

Thanks for hints. Indeed select logic is different, and three or four other lines need small changes.

I've succesfully compiled cgminer 3.1.1 with your patched sources under Debian 6, good work!:) ; it can detect and work with 1.15x board, but of course it is doing HW only because of original ztex bitstream... but it sends work:). I've started doing changes to original 1.15d4 verilog code. Wasn't so hard and even synthezises. But how did you constrained TIMESPEC clk PERIOD? From where did you get 100MHz 50%? NET fxclk_in is driven by 48MHz from Cypress FX2.

Now waiting to implement design.. hours or days with Smartxplorer...
tuned: resource sharing off, register duplication on, equvalent register removal off, register balancing yes

Do You plan to support Ztex 1.15x fpga boards for mining? I've got four of them lying down around and could play with them.
Is there only need to bitstream changes or in cgminer sources too?

If bitstream then I think that constraints file changes will not be enough to work ztex 1.15x properly because of CPLD chip absence in 1.15x version.

Could You give me any other hints, i'll give a try. Contraints .ucf file changes should be easy for me, I've done some easy HDL projects so far.

BR
hal7

Welcome, I am interesting BitCoin for last 2 years. But now I am registered user. Regards

I am guessing that 1BTC will be worth ~3500$ at the end of year.