I personally think a very memory intensive single-algo comprised of multiple algos that also reconfigures its order and settings with each block (configuration determined using the block number as a seed) is the way to go.
Something in some ways similar to an x16r, but constantly reconfiguring itself to make asics/fpgas nearly impossible or horribly impractical.
Its gonna need memory hardness and massive transistor width requirements for the component algos.
The wider the transistor width required the harder it is to put into asic/fpga. And if you combine that with settings that usually dont require the full width, you make them build tons of realestate that is normally dark, whilst a general purpose cpu or gpu will have no issues with the task changing every 90 seconds.
Also nobody is here to P&D The same development team has been working consistently on the coin since 2017. It is here to stay.