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 Help me with this error. Enter in front of the pool address ssl: // like ssl://zec.pool.minergate.com:3357 |
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says not enough memory intensity value reduced (3). what memory?? version miner 12.2 after last update  |
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While my initial analysis was focused on the external GDDR5 bandwidth limits, current ZEC GPU mining software seems to be limited by the memory controller/core bus. On AMD GCN, each memory controller can xfer 64 bytes (1 cache line) per clock. In SA5, the ht_store function, in addition to adding to row counters, does 4 separate memory writes for most rounds (3 writes for the last couple rounds). All of these writes are either 4 or 8 bytes, so much less than 64 bytes per clock are being transferred to the L2 cache. A single thread (1 SIMD element) can transfer at most 16 bytes (dwordX4) in a single instruction. This means a modified ht_store thread could update a row slot in 2 clocks. If the update operation is split between 2 (or 4 or more) threads, one slot can be updated in one clock, since 2 threads can simultaneously write to different parts of the same 64-byte block. This would mean each row update operation could be done in 2 GPU core clock cycles; one for the counter update, and one for updating the row slot.
Even with those changes, my calculations indicate that a ZEC miner would be limited by the core clock, according to a ratio of approximately 5:6. In other words, when a Rx 470 has a memory clock of 1750Mhz, the core would need to be clocked at 1750 * 5/6 = 1458Mhz in order to achieve maximum performance.
If the row counters can be kept in LDS or GDS, the core:memory ratio required would be 1:2, thereby allowing full use of the external memory bandwidth. There is 64KB of LDS per CU, and the AMD GCN architecture docs indicate the LDS can be globally addressed; i.e. one CU can access the LDS of another CU. However the syntax of OpenCL does not permit the local memory of one work-group to be accessed by a different work-group. There is only 64KB of GDS shared by all CUs, and even if the row counters could be stored in such a small amount of memory, OpenCL does not have any concept of GDS.
This likely means writing a top performance ZEC miner for AMD is the domain of someone who codes in GCN assembler. Canis lupus?
Core speed has more of an effect on 480s but they are still limited by memory bandwidth. I'm very funny that you even still protect 290,390 here is about the memory of 4xx According to AMD According to a CU efficiency increased by 15% compared to the Radeon R9 290. When processing tessellation in conjunction with heavy duty AA efficiency gains can be double or even triple. Supported data compression, thus improving memory bandwidth. In particular, supported by Delta Color compression algorithm that allows you to encode the color difference. On this technique we described in the description of the architecture NVIDIA Pascal. AMD has such compression is maintained including the Radeon Fury X, but the effectiveness of the algorithms at Polaris 10 above. With this increase in the efficiency of a data chip content bus word length of 256 bits. The Radeon RX 480 uses GDDR5 memory chips with an effective rate of communication 8 GHz. And for that AMD has introduced new regulations of memory !!! such as FP16 and 16 Int. Which I think Claymore's does not use, for this reason, the new data on the time of top 480 does not operate at full capacity. And at the same time using the old manual of memory with which he revived the old 7xxx to work at such speeds And compared to the 7xxx, 290 and 390 may be given even greater speed, including 480 if you use the new instructions of memory that only support new models 290-390-480, though only suffer 7xxx model that greatly impact on mining in overall, since the data pattern immediately lose their significance in mining  |
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I don`t know how exact you can adjust memory access to GPU memory, but ppl that compare and cry here thet RX 4xx should be fast as 390x should first learn that any architecture is different, the driver is accessing GPU memory as best as it can, if zcash need many small accesses and if 256bit bus is not wide enough its logical that 384 or 512bit bus will be better, even when we know with 2xx and 39x GPU and memory clock is more "aligned" and in sync then on RX cards which usualu work 11xx/2000
CRYING here RX4xx is pointless if you know NOTHING about internel GPU arhitecture and even less about zcash prof of work algo and how its computed
Even if 480 and memory bandwidth 256bit bus still only used 50% of its capacity !!! And I think that the manufacturer knowingly went to such a move is likely for this new chip Polaris dostochno and bandwidth 256bit bus, with his new memory controller that provides a slightly lower performance than the 390 !!! Sorry for my English That would see the controller load from 390 models think it will give a small concept in this issue R9 290 MC usage: 
Do you also know if you want to check if a algo is memory limited, you can go into GPUZ and check out the MCU (memory controller unit) and see the load on it?
I think this is wrong. Although I primarily mine using Linux, I have a Windoze box that I use for testing cards. GPU-z appears to show only external bus bandwidth use (to the GDDR), and not the utilization of the bandwidth between the controller and core. In practical terms, a miner kernel may be using 200GB/s of memory bandwidth, but a significant percentage of it can be from the L2 cache. The collision counter tables in SA5 would be an example of this. Do you have a source for this hypothesis? In all memory restricted algos that correlates to MCU usage. Pretty sure it pertains to any sort of memory overload, bandwidth or bus width... My knowledge of the AMD GCN architecture (and computer architecture in general), and my experience writing OpenCL. Loading controller slightly higher than the 480, but the GPU BPM temperature2 temperature is about the same as the GPU BPM temperature1, there is likely to interfere with the speed of the memory controller already that little bandwidth 256bit bus |
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I don`t know how exact you can adjust memory access to GPU memory, but ppl that compare and cry here thet RX 4xx should be fast as 390x should first learn that any architecture is different, the driver is accessing GPU memory as best as it can, if zcash need many small accesses and if 256bit bus is not wide enough its logical that 384 or 512bit bus will be better, even when we know with 2xx and 39x GPU and memory clock is more "aligned" and in sync then on RX cards which usualu work 11xx/2000
CRYING here RX4xx is pointless if you know NOTHING about internel GPU arhitecture and even less about zcash prof of work algo and how its computed
Even if 480 and memory bandwidth 256bit bus still only used 50% of its capacity !!! And I think that the manufacturer knowingly went to such a move is likely for this new chip Polaris dostochno and bandwidth 256bit bus, with his new memory controller that provides a slightly lower performance than the 390 !!! Sorry for my English That would see the controller load from 390 models think it will give a small concept in this issue |
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This is the quote I was refering to:
"Memory bandwidth:
RX480: 256 GB/s
390X: 384 GB/s
ZEC uses a lot of memory operations. Do you still think that RX480 can work as fast as 390X?"
I never said the 480's can do as much as 390's Please read posts carefully Yes I know the differences that's why I said that the 480's can do better than what they do right now if tweaked as per their OWN advantages I also have 390x's and I am really happy with them although they burn much more than the 480's for those of us that do pay for electricity In terms of raw computing power, the 390 has 2560 processors, while the 480 only has 2304 cores. The 390 memory is also faster. I never compared these 2 GPU's in my posts But since we are doing this please note that the 2304 cores of 480 are giving out in reality more than 2800 While the 390's in reality give out 2600 If I find the article from experts I will post it in my next post  As for the fact that 480 390 gives so much, I think all the same mistake in the code. I enclose a screenshot of my 480 so, it issues at 190 i6? So take a look at the load on the memory controller !!! He is always loaded with no more than 50% It turns out there is the load limit that is, if correct the error in the code while working with the controller, and if the load Lift at least 90%, then the rate should be about 360M / h is just slightly less than the 390 - 384M / h but better enegroefektivnosti 480 model 110-150 watts. That is half of the memory 480 is not used, so the picture is seen in the temperature GPU VRM temperature1 67C, and the second is the same in a simple GPU VRM temperatura2 26C Most likely a problem in the new processor 480 used, it works with the other memory technology, not as in the previous models. Claymore's application writes on the old technology this reason, even older models such as the 7790 cards and the like get such speeds, as well as 480 in the growth of only 15-20% with each version |
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Suprnova is under Ddos at this moment. Hash is safe but stats doesnt There was a stuck cronjob at the ZEC pool, it's catching up now and all queued payments should be processed in the next 2 hours this with twitter https://twitter.com/SuprnovaPools |
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Dear Claymore
There is a farm of 2x STRIX-RX480-8G-GAMING win10 crimson 16.11.2
So when miners including 5 and 6 version 1 video card is not detected.
2 Defined only if you add the launch of miners in the startup menu at startup. If you start miner and then close the miner and run on the new defined only 1 card.
In version 4 this happened
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People like Mein pos  There is a purse with a small amount Dnet After staking sync icon is lit, but maynin dnet happens that you need to do to mining pos involved? sorry for my English Leave wallet unlocked for staking. Eventually you will get some coins. The more coins you have the more likely/often you will get a stake Masternode payment enforcement is disabled, accepting block 2016-09-04 07:42:51 ProcessNewBlock : ACCEPTED 2016-09-04 07:42:53 CMasternodePayments::IsTransactionValid - Missing required payment - D82knDqhYkuhd5MTfySP8PSP4WBydMvGF3 2016-09-04 07:42:53 Invalid mn payment detected CTransaction(hash=c02a9db76d, ver=1, vin.size=1, vout.size=3, nLockTime=0) CTxIn(COutPoint(3d5050d89e18b136995235eb08a72b893465577d124113caece598d18367dc58, 1), scriptSig=304402201c6fa2c3d40b2975) CTxOut(nValue=0.00000000, scriptPubKey=) CTxOut(nValue=2044.99994800, scriptPubKey=039e3660d8d7944db5e05b3606909d) CTxOut(nValue=29.25000676, scriptPubKey=OP_DUP OP_HASH160 1fb5632c2f0d) |
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People like Mein pos There is a purse with a small amount Dnet After staking sync icon is lit, but maynin dnet happens that you need to do to mining pos involved? sorry for my English |
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