MC_SEQ_RAS_TIMING - RW - 32 bits - MCIND:0x61
TRCDW    4:0 5bit    Number of cycles from active to write
TRCDWA   9:5 5bit    Number of cycles from active to write with auto-precharge
TRCDR  14:10 5bit    Number of cycles from active to read
TRCDRA 19:15 5bit    Number of cycles from active to read with auto-precharge 
TRRD   23:20 4bit    Number of cycles from active bank a to active bank b
TRC    30:24 7bit    Number of cycles from active to active/auto refresh

#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f
#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0     5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0
#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5    5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00
#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa     5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000
#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf    5 bits

#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000
#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14     4 bits

#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000
#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18      7 bits


MC_SEQ_CAS_TIMING - RW - 32 bits - MCIND:0x62
TNOPW    1:0 2bit    Extra cycle(s) between successive write bursts
TNOPR    3:2 2bit    Extra cycle(s) between successive read bursts
TR2W     8:4 5bit    Read to write turn
TCCDL   11:9 3bit    Cycles between r/w from bank A to r/w bank B.
TR2R   15:12 4bit    Read to read time
TW2R   20:16 5bit    Write to read turn
----   23:21 3bit    Unused.
TCL    28:24 5bit    CAS to data return latency


#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3
#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0    # 2 bit

#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc
#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2    # 2 bit

#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0
#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4     # 5 bit

#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00
#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9    # 3 bit

#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000    # 4 bit
#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc     

#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000  # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10

#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000 # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18 


MC_SEQ_MISC_TIMING - RW - 32 bits - MCIND:0x63

TRP_WRA   5:0  6bit   From write with auto-precharge to active - 1.
----      7:6  2bit   Unused
TRP_RDA  13:8  6bit   From read with auto-precharge to active - 1.
----    16:14  3bit   Unused
TRP     19:16  4bit   Precharge command period - 1.
TRFC    26:20  7bit   Auto-refresh command period - 1.
TCKE    31:28  4bit   CKE power down exit timer.

#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f     
#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0        # 6 bit
 
#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8        # 6 bit

#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf            # 4 bit

#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14          # 7 bit

# TCKE is not defined in gmc_8_1_sh_mask.h as a SEQ_MISC_TIMING