The BFL reps responded to one of Avalons claims...with very vague mentions of a ~unique~ workflow arrangement enabling them to do...well, the impossible. (IMO)

https://forums.butterflylabs.com/bfl-forum-miscellaneous/500-josh-plz-give-us-some-comments-about.html#post7363

While I appreciate the technical prowess of the Avalon team, the fact of the matter is they simply don't have the resources or experience we have in this area.

I think you have no sense of humility after doing business for 25 years in these regions that you lost the ability to talk to another person like a regular human being. I had no intention to hide who these people were, I simply uploaded the picture from my phone on-the-go and now had the chance to do a proper follow up, not to mention many of these faces are not new and often seen in public involving bitcoin.

It would be much appreciated in the future, especially when directing questions at me. Brush up on how to be a gentleman, remove any trace of prejudice and cynicism you have obtained from a past that has nothing to do with me.

This update is mainly to address the uncertainty that have been surrounding the ASIC scene recently due to the lackluster performance by our competitors. We will be walking you through our process of getting the ASIC fabricated. Unlike our competitors we are a in-house team and everyone is always on the same page.

Another update will address the actual status of our chips as we have obtained word from TSMC whom will offer us weekly updates on their website. All in all, see our arguments below regarding our competitors and wait for weekly updates directly from TSMC.

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Anyhow, any of our numbers, estimates, and shipping date have not changed, just in case somebody got the wrong idea about this update.

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First things first. the following Gallery is our contract with TSMC with pricing and other sensitive information removed. http://imgur.com/a/DnUNm


Some background information on ASIC production process, before tape out, 3 day before uploading GDS, we fill out a MT form with TSMC detailing the ASIC specific information so they may understand what we are doing. The gallery is here http://imgur.com/a/YOLez


to put simply, to create the physical ASIC goes something like this.

sign contract -> submit GDS for review -> mask making -> wafer making -> ship to packaging company -> packaging -> shipping.
Only then can the chips be in your hands or placed on PCB for finalization.

This whole process will take 30-50 days depending on the processor node technology used, mainly due to the increasing in layer number as you go down in processor size. for example, we have 29 layers, and since TSMC is one of the big companies in fabrication, each layer take 1.2 ( normal lot ) day per layer. in addition, accordingly to friedcat, their fab is producing 4 layers every week [odd, but I guess it is possible if fab is small].

This also means while you wait for the wafer(chips) fabrication you can not do anything else, it is usually around this time you make sure you have everything else ready.

a few things to note is,

1. while this wafer making process is going, you can't cancel it, or make adjustments, and if you wish to change anything, you will have to re-run this whole work flow all over again ( the large amount of the NRE upwards of 6 digits in USD is paid when you make the MASK). so anytime, BFL mention they are waiting for chips to come e.g. next week, but if they are still making adjustments, then this is physically impossible. In addition, fabrication company don't do chip packaging, if they are expecting the chips to arrive next week that means the production is already finished and they are probably in the chip packaging company (it is usually this time you find out if your chips work or not. which can also take some time since you'll have to test each of the chips for defects.)

2. the whole chip fabrication is very mathematically predictable based on the number of layers your ASIC has and the speed which the fabrication company can produce a layer. There is no such thing as a fabrication company giving a "fuzzy" date when it comes to when the chips will come from the assembly line. The only number that can vary is the shipping time from the fabrication company to the packaging company, but even that is no more than a few days of difference, depending on the shipping method.

3.a if bASIC made an MPW to start (which is the correct way to save money, but not time). the cost to get large amount of chips during this time is astronomical, however the average size is about 50. It is unheard of for somebody to only produce 2 chips to built a prototype and now no longer have any chips left over to build another prototype.

3.b. Even after testing MWP and everything is fine, it'll take the same amount of time to produce a new MASK ( cost and everything ) then make wafers, which will take another 30 - 50 days, which I suppose is consistent with bASIC's new mid-Jan shipping date, ( but this is optimistic estimate, the regular workflow is about 2 month)

3.c. what we think that happened is bASIC has licensed a SHA256 core, the IP company has already produced demo ASICs that utilizes this core, and did some math on how many core you can placed in the chip to obtain the 14GH/s estimated hashrate, while regular SHA256 and Bitcoin's blockchain hashing algorithm is not very different but it is not something you can compare via simulation without making an actual chip, and if they made an actual chip, even if it doesn't perform up to specifications you can still demonstrate it and be world first.

the conclusion is as follows.

1. If BFL really have chips coming, then they are not making any so-to-speak "clock buffer adjustments", either that or they don't have any chips coming and have not tape-out at all, it is also entirely possible that they have not make the MASK yet either. I guess we will find out on the week of the 11th, in this month hopefully.

2. we believe bASIC has no prototype, or have any chips. Also we at Avalon have also explored the possibility of licensing an IP core, but after some in-house comparison, none of the core on the market is superior to our own, thus we eliminated that option.

Questions, Comments are welcome.

LOL,
So funny to read this nonsense about "shares"... read up on China Law guys.

I think luke-jr must have stopped looking in that thread.

They are at the stage of wafer-process, which is the last one before slicing and packaging, and is the most time-consuming. They have finished 13 layers out of the total 29, and there are 16 layers to go. The speed was originally very low (1-2 layers a week), and had become quicker in recent weeks.

Yet you boldly ordered a Jalapeno, and BFL cancelled it. And yet you lent a broke-ass guy who would go mining with a 12btc graphic card he could not afford and needed a loan for, 6 coins, which he would pay back of the profits, while the fine for being late on that loan (did you ever hear from him again?) was more than he could earn with it? Math, it ain't easy.

Maybe someone at BFL went to the Duke Nukem Forever School of Hardware Design?

Here's the actual list:

1. The CEO is a convicted felon who
1.a. Is in probation/supervised release.
1.b. Is prohibited by the terms of his deal from doing a number of things BFL is doing, such as taking money from people.
1.c. Failed to disclose this; once discovered by 3rd parties he made a half-assed statement about "the mean government". Promised post with further details "over the weekend", never materialized.

This was explained away on the vague theory that while convicted "he wasn't really guilty" and while the CEO "he doesn't really have anything to do with the company".

2. BFL is a company that
2.a. Consistently made promises which were then not kept, such as to the time of delivery (blown in the past by 4 months +) and specifications of the items delivered (significantly larger power consumption).
2.b. Consistently takes money from perspective customers in exchange for products that do not actually exist. These don't constitute pre-orders, even if BFL calls them that, but loans to the company.

This was never explained other than "doing things is hard".

3. BFL PR is a guy who
3.a. Is a loudmouth just like I am, except he makes a lot less sense, rarely has a point and also lacks tits.

Enjoy.

(And yes, my personal opinion is that dud run = bankruptcy.)

So ... who's planning a better hardware interface

No. As bitfury demonstrated in practice, tiny hashing cores are superior to unrolled designs. He gets 300 Mh/s compared to 220-240 Mh/s for the competition, on an LX150. Some of the gains are attributable to overclocking and overvolting, but most come from its superior design.

I think you're suggesting that unrolled cores are the answer. They aren't. You run into timing problems, and you also pay for that silicon to be produced no matter how sparse or packed it is. The best option seems to be iterative rolled up cores that take ~110 cycles to do a nonce, but you have ~100 times more cores.

Plus, it increases yields as the controller hardware can just test which cores work and ignore known broken ones (ie, intentionally binning parts ala modern GPU design).