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Double check me on this: tx_pre_w <= s0(rx_w[2]) + rx_w[1]; // Calculate the next round's s0 + the next round's w[0].
tx_new_w <= s1(rx_w[14]) + rx_w[9] + rx_pre_w;
right.. though the tx_pre_w can be saved at w[0]'s place that is to be transmitted to next loop, it will save a register.. |
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if the above solution is applied, the calculation of new_w will be the new critical path... new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];again s0_w can be calculated a loop ahead and added to rx_w[31:0]. this way our new_w will be shortened to: new_w = s1_w + rx_w[319:288] + rx_w[31:0];dcreasing the critical path and possibly increasing the clock frequency... Can anbody tell me the %age LUT utilized after synthesis... there may be a possibility of replacing the adders logic...  |
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well i had used LX150_test. and i dnt have a lx150 dev board, so i think i will just share my ideas here.. the critical path in this circuit is " t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k".. but k and rx_w[31:0] can be calculated one loop ahead and added to rx_state[`IDX(7)] at the point below:
state_buf[`IDX(7)] <= rx_state[`IDX(6)];the new code should look like this: state_buf[`IDX(7)] <= rx_state[`IDX(6)] + rx_w[31:0] + k;----> where k and rx_w are of next loop This will reduce the adders to: t1 = rx_state[`IDX(7)] + e1_w + ch_w;this should improve clock speed, provided routing issues dont interfere.... |
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hi to all,
i am having a little trouble here. I had some experience in designing sha1 hash cracker on fpga, so this project caught my interest. When i downloaded the code and tried to compile it for S6 lx150, it took about an hour to just synthesize the code and then the software said i had overused my resources.. so i wanted to knw, where did i go wrong?...
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other people can use the generated design without the software
If the benefit of the work is open to the whole community and designers(who already have the software) have the freedom to tweak it then i think its pretty much open source... Tough as it already is, including the price of the software means dropping the bounty altogether... |
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My FPGA design can do 1GH/s on Stratix IV 530. The dev board costs USD$8k, and would need fan/heatsink added. I'm guessing that power usage would be around 40-50W?
Is it stand alone? or a computer is required? Usually the designing software could provide the power requirements of a system, try checking that.. |
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sorry, i wasn't talking about design feasibility, rather the market feasibility... what any designer would need to know is the worth of his effort... if i develop a system and people still prefer GPU's over fpga rigs, then why would i want to waste my time?... in short if i could such a system in the market, how many people would want to buy it?
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I am a newbie in the BTC world and I was wondering what would be the feasibility of an fpga based hardware with these specs:
900Mhashes/sec
about 5 watt power consumption
$1300-$1500 unit price
Hi. I'm also new to the BTC world, but I'm an electrical engineer and I've been following the threads on FPGA mining recently. I think that for that hash rate, your power target is off by about a factor of 25 and your price target is off by at least a factor of 2. Disclaimer: I have not yet built, designed, used or measured an FPGA based mining rig. If one of the experienced FPGA miners drops in here, they may be able to provide a more accurate estimation. Maybe I'll play around with FPGA mining myself sometime, if I don't get distracted by a shiny object first.  well what are fpga's worth for if they consume 5*25=125 watt?? it may rise upto 10 watt but not more.... I can design the system with above specs but i really need to know if such a system is feasible.... |
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Hi,
I am a newbie in the BTC world and I was wondering what would be the feasibility of an fpga based hardware with these specs:
900Mhashes/sec
about 5 watt power consumption
$1300-$1500 unit price
??
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well i see that most of the people here are in favour of GPU's.. but fpga are not as costly as we think...
I am not a miner, rather an fpga system developer. and if the estimates on these forums are accurate, i am quite sure that the fpga can take over gpu anytime. it is just till the right product gets in the market.
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Hi, I am an engineer and i saw this thread while surfing, http://forum.bitcoin.org/index.php?topic=8543.200. I believe i have some great updates to share as i am working on an fpga mining system which is hoped to outclass GPU mining. So, can you please drop the restrictions as i am writing this request to you instead of preparing for my exam due on monday. regards, |
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