What gmaxwell did with his covert-asic-boost post and BIP was a test balloon smeared with shit. The test was "how many flies can we catch with it" and on this measure it was a great success. It is greatly valuable in discovering who will write about it without having a foggiest understanding of electronic device manufacturing and operation.

So your stance is that 20% more or less efficiency doesn't matter in the electronics industry. I have my doubts about that. As I told you already, I think you are confusing the standard deviation on an individual chip, and the fact that the average over a lot of them, shifts.

I would agree with you that if the technique, used to gain 20% more efficiency, would INCREASE the dropout rate by 20% or more, then, yes, this is not a good idea. But if you get the same per-wafer dropout (even if it is 20%), and your *average* efficiency increases by 20%, that's something that, in most competitive markets, wouldn't be neglected, I'm sure. If all else equal, there's no reason NOT to profit from 20% more efficiency.

Firstly, don't repeat the propaganda number of "20+%" gain. This is a pure marketing bullshit. Tightly coupling 16 pipelines will greatly reduce the maximum possible clocking rate or lowest possible supply voltage. Additionally the yield of useable chips will be lower. From my general observation of modern semiconductor devices the optimum number of coupled pipelines would be 2,4 or 8, hard to tell. 16 would be past "diminishing returns" and into a "diminishing" territory. I've seen full simulation and analysis made for a different chip (not related to mining) and after doing some substitutions I arrive at the first guess of "-2%", i.e. small loss from synchronous 16-way hashing.

Secondly, by the very fact of using "standard deviation" in you argument you show the depth of your misunderstanding. It is hard for me to guess what you don't understand. My two best guesses are:

1) you may be thinking in terms of some unimodal distributions, where in reality they are always bimodal or multi-modal.

2) you continue to use simplistic textbook statistical models in your estimates. "In statistics, a trial is a single performance of well-defined experiment (Papoulis 1984, p. 25), such as the flipping of a coin,..." This maybe a good approximation of one hashing pipeline pass, where one trial block header is processed in microseconds at the cost of probably nano-dollars. Yet you seem to use it completely exchangeably with chip manufacturing workflow that takes months and costs kilo-dollars or mega-dollars.

Please upgrade your arguments to something more professional. Thanks in advance.