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1  Bitcoin / Mining / Re: Mining operations in venezuela on: May 23, 2016, 04:22:52 PM
That would make sense IF they interacted with the venezuelan community, but they are strangers to most of us... and i'm mod/admin on some of the venezuelan groups.
This is actually a good sign when the various factions of the underground movement don't know about each other. It is crucial to their resiliency against subversion.
2  Bitcoin / Hardware / Re: Email from Avalon on: May 14, 2016, 01:18:17 PM
You make money from the sale of chips; with the exception of providing technical information to a very few technically competent people there is no customer service required on your part.
He can't do this because it is too risky for him. It is possible that your design would be better than his. That would mean a "loss of face" or loss of respect (and self-respect) for him. That's why he can't and wont risk doing what you propose.
3  Bitcoin / Hardware / Re: Email from Avalon on: May 14, 2016, 01:09:51 PM
I understand you want to make money , but having your chips in other peoples designs would make you money not cost you money.
This is your mistake. It isn't about money. It is about respect, and by "respected" it one from the Occident should probably think "feared". My shortest explanation is that ngzhang belongs to a class of people for whom having 90% of $1000 is more than having 10% of $100000. It isn't about getting more money, it is about getting more respect. It is a fundamental difference in motivation.
4  Bitcoin / Hardware / Re: Community Miner Design Discussion on: May 11, 2016, 10:17:46 PM
Request for clarification: is your "maybe obvious generalization" serial power idea any different than what Bitmain's done for string power on S4+, S5 and S7?
I don't know the details of BitmainTech's PCBs layout nor for the fact details of any other company. I can't really answer your question. All I've seen are some prototype designs with Bitfury chips, which were parallel connections of strictly serially connected chips. The more general layout is serial connections of groups of parallel connected chips. In the simplest case of four chips:
  +--- C1 --- C2 ---+
Vdd                 Vss
  +--- C3 --- C4 ---+
is parallel-serial a.k.a. "string"
  +--- C1 --+-- C2 ---+
Vdd         |        Vss
  +--- C3 --+-- C4 ---+ 
is serial-parallel. The 2nd is more general and easier to control and stabilize.
5  Bitcoin / Hardware / Re: Community Miner Design Discussion on: May 11, 2016, 08:18:31 PM
A brief email conversation from last fall.
Oh, so I presume some internal/unpublished document from Spondoolies. My take on this is that it may be true with their implementation only. The general implementation shouldn't (or needn't) have such limitations. Or maybe there's some additional trade-off included in their design that wasn't disclosed or covered by the patents.

IIRC the SP50 drawings released showed large number of small power supplies, so my speculation about power distribution optimization was not really well-grounded.
6  Bitcoin / Hardware / Re: Community Miner Design Discussion on: May 11, 2016, 07:59:31 PM
"To achieve those power numbers (actually a bit better then the published numbers), in addition to full custom design, we're doing some pre-computation per job, which needs the cooperation of large number of ASICs. Hence, the ASIC isn't suitable for usage in small machines."

"For now, we decided not to share more info abut the design, due to a patent we're implementing."

Could be something else, but it's completely unrelated to power supply changes.
Who do you quote? Edit: I mean, which document do you quote?
7  Bitcoin / Hardware / Re: Community Miner Design Discussion on: May 11, 2016, 07:14:24 PM
Assuming Spondoolies NDAs are no longer effective since they're closed down: I wonder if that lines up with something I heard from Guy about last September or so. When they announced the new chip for SP50, I talked to him a bit about availability and was told they had changed something in the design which gave them the efficiency boost when many chips were utilized together. So a single-chip or probably even SP20-scale miner would, I assume, not approach the 0.16J/GH efficiency given for the 800-odd chip SP50. The conversation about chip sourcing ended before any real information changed hands in October when he said they were patenting the innovation.
I doubt any of those patented "boosts" involve any inter-chip data sharing. I think they are all limited to intra-chip inter-engine sharing.

The obvious inter-chip efficiency "boost" is just a different name for "string power supply", which indeed would be new for Spondoolines. Or maybe obvious generalization: serial power connection of small parallel clusters (2-4) of chips. Much less finicky that strict serial power to properly stabilize.
8  Bitcoin / Hardware / Re: Community Miner Design Discussion on: May 11, 2016, 06:37:18 PM
Just tossing this out there to see where the cow pie plops Wink
you said it needs high level pre conditioning of the data the actual sha hashing cores handle and that cpu-type of operation normally is not present in each ASIC. Very true now and in the past but what if say a tiny ARM core or other MC was put inside of each ASIC to do that? That would be very easy to do these days. Possibilities there?
There's now more information available publicly:

1) There's a competing patent application by Spondoolies entitled "System and method for providing shared hash engines architecture for a Bitcoin block chain" filed at the end of March of this year.

2) There's a discussion "Making AsicBoost irrelevant" on bitcon-dev:

The ASICBoost patent seems to be slight generalization of the Spondoolies' method. But their patent application is way more readable than AsicBoost's paper. That is very rare case and it puts Timo Hanke in bad light.


3) Relevant ASICBoost patent had been apparently published almost a year ago:
9  Other / Meta / Intentionally misspelling domain on: May 06, 2016, 11:52:33 PM
There's apparently a fraudulent domain misspelling the world "silicon" in the "" with two lower case "ll".

It is currently being used on the main discussion board here in the thread "BREAKING NEWS: SATOSHI FINALLY REVEALED!" Can some moderator go there and obfuscate the HTTP: link to avoid spiders from increasing the rank of that fraud?

Unfortunately I slightly worsened the situation by not obfuscating the http link in one of my quotes. I'm posting over a bad connection in a pizzeria that is closing shortly. I'm going to delete my bad posts in that thread and paste them here.

Thanks in advance.

{{Citation needed}}

How about hxxp://

This is fraudulent website that misspells the word "silicon". The correct website doesn't have this post:

Please quote my post for posterity.

Edit: Also, you may want to obfuscate the fraudulent link so it doesn't get spidered by the search engines

How about hxxp://

Was hoping for something not made up by an author.

This is fraudulent website that misspells the word "silicon". The correct website doesn't have this post:

Please quote my post for posterity. You should probably also obfuscate the fraudulent link so it won't get scanned by the search engines.

Why would it need quoting?
I want to be out of this thread as soon as possible, so I will delete my original messages. At the same time I want everyone to be warned against referring to that fraud.

Please re-edit your post to obfuscate the working http link I accidentally left in the open.

I will delete this message to once somebody quotes it.

10  Bitcoin / Hardware / Re: Community Miner Design Discussion on: April 30, 2016, 02:58:42 AM
...are you kidding? Perhaps, I misunderstood, or it is true in chip design, but it (what the prof said) makes absolutely no sense in other sciences, like physics, chemistry or biology.
Yeah? In which science you will get recognition for publishing a paper that would effectively say: "we worked hard trying to improve previously published results, but failed"? It is a common problem that gaining a negative knowledge doesn't get you promoted.

The only way to get promoted is to improve or falsify somebody's else results. And falsification may brand you a spoilsport.
11  Bitcoin / Hardware / Re: Community Miner Design Discussion on: April 30, 2016, 02:16:48 AM
Just tossing this out there to see where the cow pie plops Wink
you said it needs high level pre conditioning of the data the actual sha hashing cores handle and that cpu-type of operation normally is not present in each ASIC. Very true now and in the past but what if say a tiny ARM core or other MC was put inside of each ASIC to do that? That would be very easy to do these days. Possibilities there?
I think that you are still thinking at a too low level.

My reading of Timo Hanke's paper is that it is some high-level algebraic-combinatorial transformation that has to be done only once, very early in the design stage. Once that transformation is done no further software/hardware/logic would be required in the implementation.

Edit: Let me put it in different words. The Bitcoin SHA256D hash can be written as one very long equation with 80*8=640 binary variables. Then the conventional miner changes only 32 of those 640 binary variables (32-bit nonce). Each hashing core would be a hardware implementation of that single very long equation, but for all cores on the chip the other 76*8=608 bits are the same.

Timo Hanke apparently found a mathematical way of reorganizing that computation by changing other bits out of the 640 binary input variables. His transformation seems to be some sort of common subexpression elimination when that very long equation is written multiple times. So in other words the hashing cores in a chip would be no longer independent but would have some shared parts in groups of e.g. 16 for 23.4% total savings versus 16 completely independent cores.

My understanding is that it should be completely possible to explain his transformation with mathematical symbols. Be he had chosen to not publish the details. It is possible that those details could be prohibitively long for normal scientific publication, like hundreds of pages.
12  Bitcoin / Hardware / Re: Community Miner Design Discussion on: April 30, 2016, 01:05:20 AM
Reading through their whitepaper is answering a lot questions I've been accumulating in the back of me mind on just what a mining chip Wizard is doing behind its curtain. Well, under its hood actually... Ever since Sidehack mention at least passing interest in mebe learning chip design my Muse's cat, Curiosity, has been bugging me about it... Wink

EDIT: Thoughts on from ASICboost on their idea? So far looks like they say they have a different and more efficient use of gates achieved by using a different logic structure/flow than other folks.

Only 1 person I can think of can give me insight as to a 'yesss......' or , 'meh' and and they are not into BTC per se but are Wizard of chip-level data flow the likes I've rarely seen.

Gotta say ever since making a chip was brought up my natural curiosity into everything got me to thinking about what goes on inside a mining ASIC and methinks that paper is answering a some of that.
Firstly: ASICboost isn't any company. It is Timo Hanke, a German scientist who was the only technical employee of Cointerra that was willing to show his face in their marketing video (aside from the CEO). My quick take on the guy: he was forced to work/shill for Cointerra due to some immigration paperwork screwup/problem. His permanent residency and employment seems to be in Germany. The ASICboost publication seems like a quick way to salvage his academic career in Germany. It is also very dirty work, the PDF still has embedded links to website to allow editing the figures.

Other than this the paper is too short on information to make an informed decision. First of all: it has nothing to do with ASICs, it is pure marketing. This is some sort of high-level transformation that could be reproduced in CPU/GPU/FPGA miner. But those are no longer commercially competitive, therefore the reference to the ASICs.

There's only one table (Fig.6) showing percentage gains up to 23.4%. But those seem to be purely combinatorial figures, there's no estimation of saved power or lowered gate counts.

One of my professors at school had an advice for young scientists: If the numbers are good: multiply them by 2 and publish widely. If the numbers are bad: divide them by 10 and hide in the bottommost drawer.

arXiv is a pre-print archive, there's no peer review of the papers published there. The peer review could however happen later.
13  Bitcoin / Hardware / Re: Bitfury: "16nm... sales to public start shortly" on: April 29, 2016, 09:43:37 PM
Don't worry, I don't take this personally. The more posts from 2112 I read, the more I get the feeling that he is probably a little bit too long out of the real world ASIC business
That portion agrees with my self-assessment.
and if he ever got to know it, then more from an academic point of view.
This doesn't.

By the way, he is not the only one who had strange experiences with Apache (now Ansys) tools and these are only niche tools, which you need for a very small part of the overall design flow (sorry for the CAD monkey terms).
This portion show that you've didn't read my post with understanding. I never used Apache, I quoted Hashfast's CEO.

You have of course to do a design exploration of different variants of hashing cores. And if you want a complete picture then you have to do it in different technologies. But I doubt that you have to tape-out all these variants to get to know, which one is the best and should be used in the final ASIC. If you are an experienced CAD monkey Wink you can determine which of your variants is the best with high confidence without silicon, at least relatively to each other. Real silicon results will be +/- 15%, maybe +/- 20%, but not more, otherwise you missed something very important during the design phase.
-15% -20% (or any mention of +%) is pure science fiction. The "very important" thing missed by HyperMega (and others) is that coin miner is unlike nearly every digital chip it will be only operated  overclocked/undervolted, in the regions where digital model don't apply and one has to use the mixed-signal or analog design flows.
And in any case, finally every working mining ASIC will be a layout based on a replicated highly optimized hashing core, because there is no other efficient way to implement so called multi/many core systems.

If I would do a prototyping run like discussed above (based on a MPW run), then I would try to get as close as possible to the final ASIC with respect to performance, die size and packaging concept to be able to pipe clean the complete miner system design including cooling setup, string regulation concept and so on. That does not exclude that you include different variants of hash cores in the prototype.

Anyway you should keep in mind, that the complete prototyping cycle AFTER you have finished the design will take at least 6 months including packaging, measurements and analysis. That is why almost everybody who has “successfully” brought a miner to market skipped this step.
Yeah, I'm slowly getting the "new way" of selling the ASIC design services. There are no plans for repeat business, it is strictly one-time hit-and-run affair.

Personally, I wonder about why Spondoolies' subcontractor designed POST (Power-On Self Test) circuitry into otherwise quite competent ASIC design. Then Spondoolies' software had to explicitly re-enable hashing cores that only failed POST when cold, but hashed fine when hot. No other vendors made such a mistake.

This got be something related to the contract between Spondoolies' and their vendors, like somebody doing excessive sandbagging to cover their asses. I wish somebody familiar with current practices (and not bound by NDA) could post their SWAG (Scientific Wild-Ass Guess).
14  Bitcoin / Hardware / Re: Bitfury: "16nm... sales to public start shortly" on: April 27, 2016, 12:21:17 AM
Hypermega: Thank you for a very useful reply to Sidehacks questions vs the snarkasim from 2112. Needing to ask questions about things outside of ones core competency is not a bad thing and should be met with better than Ivory Tower attitude.
It takes different kinds of bait to catch different kinds of fish. A touch of snarky-bait convinced eldentyrell to surface his submarine and post a reply after more than a year of underwatersea navigation. Also a salesperson from some fabless boutique made a post.

On smarmy-bait you'll catch fish like Mr. Kashif. Bitfury folks would be crazy to invite him to their office. After exchanging some PM's with him I'm sure that if he somehow had shown up in my company's office the security would escort him out.

It takes a certain appropriate mix of "school smart" with "street smart" to swim in the ASIC waters and not get eaten by sharks.

I'm actually dedicating this post to all of non-engineers who can't understand all that semiconductor industry jargon. For them I wanted to recommend a book by Feng-Hsiung Hsu from 2002 entitled "Behind Deep Blue: Building the Computer that Defeated the World Chess Champion". He was the lead engineer who designed the chip, but he co-authored this book with some professional writer and the result is a page-turning thriller. There are absolutely no equations. Neither engineering nor chess knowledge is required to enjoy this book.

Obviously the actual technical material and example prices are obsolete. But the book will show the reader how to successfully skate the edge between academia and commerce (in case of Hsu it was Cornell and IBM). His opinion about using commercial "layout services" for repetitive ASICs in my opinion still stands as valid.

Use the above link if you are the person who likes to pay and be treated with respect.

Use the above link if you are OK with reading this book for a price of smile and a wink to your friendly neighborhood librarian.
15  Bitcoin / Hardware / Re: Bitfury: "16nm... sales to public start shortly" on: April 26, 2016, 11:50:59 PM
That is definitely not true.  I have a chip I designed and fabbed through Europractice sitting in front of me right now and neither I nor my company have any connection to Europe.

For a while TSMC would not let them quote US customers, but that restriction was for that one fab only and it has since been removed.  The only thing Europe-only is the academic discounts.

Europractice's IMEC team in Belgium (the ones who do UMC+TSMC tapeouts, but not GF) are absolutely top-notch, outstanding people.
I'm glad you were able to catch and correct my error. Admittedly I'm nor really familiar with the merchant terms for one-off designs. I always worked either through academia or with the long-term projects that involved purchasing options for masks and wafers.

WIth SHA256D miner isn't any issue of secrecy or intellectual property. Getting into partnership with some academic institution would not be problem at all. That was what Bitfury did with their first chips. Here's a quick example of a subject for a master thesis or a post-doc paper:

Comparison of combinatorial constant-propagation gains versus passive transmission loses through varying unroll factor in digital circuits with high toggle ratio.

That would be about 75% to 90% of work required to optimize a Bitcoin miner ASIC. For particular example Bitfury used unroll factor 2 in his original chip.
16  Bitcoin / Hardware / Re: Bitfury: "16nm... sales to public start shortly" on: April 26, 2016, 11:40:31 PM
Yes, but this is not much for a mining ASIC even in 22nm. I guess it should equate to about 10 ... 15 unrolled hash cores, because this 22nm GF node is only a 80% shrink of the GF 28nm node, not a true 50% shrink like other 20nm nodes. But therefore the 22nm masks cost only a little bit more than a 28nm mask set.
This is a perfect example of daft thinking of a CAD monkey. No sane hardware engineer would waste that valuable real estate (50 plots of 3 square millimeters each) to fill it out with identical unrolled cores and try to commercially mine with them. The sane engineer would fill those 3 with as many different interesting designs as he/she could think of and then compare simulated results with actual results to gauge the accuracy of the toolchain. That is the whole point of prototyping.

I understand that some people find "CAD monkey" term offensive. But such proposal as above is equally offensive to the normal hardware engineers. That is why epithet was invented to quickly distinguish a narrow subset of programmers.

And yes, Universities have these tools almost for free, but for strictly non-commercial use. As soon as you want to design something, which could be commercialized directly or indirectly it is illegal to use University licenses for it. If something like this would be discovered by the EDA vendors, you and the University would have huge problem.
This never happens to students or faculty at non-profit schools. It does happen in for-profit schools or maybe at non-profits when administrative staff gets involved in theft or unauthorized resale. In normal schools the and will easily trump the short term commercial concerns.
If you like to get your feeds in the water here, it would be better to cooperate with a IC design service company at least for the first project. You bring the chip concept and architecture, they help you to design, manufacture, package and test it.
From my point of view, it is almost impossible to build up the required competences from scratch, despite you hire some experienced IC designers in your company.
Where is your company located?
I worked for a while for EDA vendor and I start sensing a sales-critter. I'm the last person to try to blame the sales person for trying to earn the commission. In fact I'm still grateful for being invited the celebratory party of one salesman who with single sale funded (pre-paid) college education of two of his kids.

I also remember particular post trade-show dinner party (in Anaheim,CA or Las Vegas,NV) with various EDA industry bigwigs. One thing I remembered was one founder being asked how he got money to start up. His story was that out of school he was reselling used office furniture.  One time they bid several k$ for a closed office of some major US automotive concern (Ford? can't recall anymore). It turned out that the cabinets were filled with Ford's(?) internal paperwork related to hard-to-fix warranty repair problems. They actually successfully blackmailed Ford(?) into buying those cabinets back for some 1M$.

Why I'm retelling this story? People need to learn how to bargain with EDA vendors. Here's a quick example:

So power consumption variance is +-20%, can we infer the same with hash rate then? Since usually more power  means more heat to dissipate.

Most commonly the power consumption of real silicon comes in better (lower) than the predictions from the Apache Redhawk tool we are using. The cooling system in the Baby Jet is massively over engineered, to give some margin, and to support overclocking.

Cheaply buy out of the bankruptcy the intellectual property that went through that Apache Redhawk simulation with gross errors. Then talk to Ansys to fund a research grant that would establish the reasons for such large errors and ways to correct their products. It is not much of business idea but it is an idea of how to not only get expensive EDA tool for free but also get funding/grant for its use at a research university.
17  Bitcoin / Hardware / Re: Bitfury: "16nm... sales to public start shortly" on: April 25, 2016, 04:30:39 PM
If I'm thinking right, VHDL would get me FPGA design, which is probably a good place to start making sure I at least know how to do the basics right with some real-world implementation. It wouldn't directly help me build anything ASIC but it'd be a start. I'd like to have more of a foundation to build on.
This looks like you want to have career as a CAD monkey at a defense contractor. In the USA VHDL is mostly used by those who are paid by Department of Defense (VHDL being an offshoot of Ada, also sponsored by DoD). The civilian industry mostly uses Verilog.

Anyways, learning VHDL or any other hardware description language emphatically isn't learning foundations. This is just a front end, one of many ways of inputting the design into the design workflow. If you have solid foundations, you could pick up VHDL, Verilog, SystemC or any other language in about a week or two of full time work (8hrs/day 5days/week). I know I did just that at my first job. Within first month I started filling bugs against the VHDL compiler (they were quite immature then.)

Overall, learning such a shallow stuff like would be a waste of time and money at a college for somebody who is already working and not looking to extend his childhood. To make the college costs worthwhile you'll need to make their enrollment/intake people really work for you. Here's how to do it properly (I'm assuming that your educational goal is to learn how to design a really good Bitcoin mining ASIC).

Don't mention Bitcoin. Mention the following problem: I have a 28nm ASIC in which the critical path is in the expression temp1 := h + S1 + ch + k(i) + w(i), all values being 32-bit registers. This ASIC works at about 300MHz. On the other hand I know that Intel CPU could execute instructions like mov eax,[ebx+4*esi+offset] at a rate of about 3GHz when still using about 100nm process (Pentium 4 a.k.a. Netburst). There are only two visible additions in the Intel instruction, but more are hidden in the segmentation/paging/caching hardware. I don't want to compete with Intel, I just want to learn how to make my little ASIC run at a real competitive speed. Can your school teach me something that would help me achieve this goal?

I don't know the admission process in your school, is it just a single administrative person or are you going to face an admission committee consisting of a mix of administrative and teaching faculty people? You may also want to visit your school on some "open days" and talk to the prospective professors.

Your original idea (asking for VHDL course) looks exactly like you were trying to fit yourself into some job posting from a defense contractor. It is your life and I can't tell you what to do with it. But in my opinion focusing on minutia is a wrong way to pursue education.
18  Bitcoin / Hardware / Re: Bitfury: "16nm... sales to public start shortly" on: April 24, 2016, 04:24:12 PM
I'll see what classes they have on VHDL when I'm talking to enrollment folks this coming week.
And pray tell, how would learning VHDL help with developing efficient ASIC mining chip? How that thought popped in your mind?

Also, possible this line of discussion should shift over to the Community Miner thread, since - and yes I know it's my fault - we're tangented pretty far off topic now.
Or we could maybe invoice Bitfury for shilling services in their thread?
19  Bitcoin / Hardware / Re: Bitfury: "16nm... sales to public start shortly" on: April 24, 2016, 04:17:22 PM
Since it's obvious I couldn't find my ass with a map in the chip fab world, how about clarifying a couple of things:

"unpackaged" means the bare die with no carrier? right?

"3mm2" is the die size?

What is "... the required CAD/toolchain" to design (tape out?) something like sidehack was proposing?

We, as a company, have a couple of other chip concepts outside the crypto currency world.
If the cost of the S/W isn't to prohibitive and we knew what we were looking for/pricing we might spring for it.

Thanks in advance.
You won't like my answer, but I have to reiterate what I wrote in response to sidehack. You can't afford to ask stupid questions. If you behave like a time-wasting crank, people will treat you like a crank or crackpot. Both MOSIS and Europractice don't have funds to employ salesforce that could tolerate such inquiries. It is presumed that the prospective customer of theirs is sufficiently intellectually inquisitive to read information on their websites.

Europractice serves only European countries plus some culturally related territories, like ex-Euro colonies or ex-USSR. PlanetCrypto is based in US, so you will only qualify for MOSIS. I referred to Europractice partly because of my background and partly because more of the Europractice's site is available for non-members, before signing off the NDA.
20  Bitcoin / Hardware / Re: Bitfury: "16nm... sales to public start shortly" on: April 24, 2016, 05:00:55 AM
Real, no bullshit, prices from slightly out-of-date Europractice access to GlobalFoundries 22nm process:

50 prototype dies, unpackaged, untested

48,000EUR for up to 3mm2 plus 16,000EUR per each additional mm2.

I'm not up to speed, but by my understanding is that access through MOSIS (sidehack is based in the USA) is both slightly cheaper and has somewhat more frequent shuttle runs.

A young, personable individual could do the tape out for free by pretending to audition some EE courses in some local (US or EU) school that has the required CAD/toolchain available in the student's labs. I remember from my student days several groups of people that manufactured prototypes on the side while taking courses. The only time my school objected/prosecuted was when some lamers actually physically took the test equipment out of the lab (in effect stealing). Many people overbooked the computer lab time in ridiculous amounts to run side consulting jobs.

Good luck to you, sidehack, personally.

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