because mining didn't need a computer. 
it's possible to use a DD-WRT based router instead.

  looks like EMS is much faster these days.

 Problems solved? 

package sent yesterday. tracking NO. also sent by email. 

maybe after this project, when i have some free time. i will build a small FPGA(LX16 FT256) dev board with DDR2 RAM and FT232 connect as you describe and sell it at a ultra low price(50$) for learning.

short answer:
1, yes!
2, TXD,RXD,CTS,RTS
3,
4, clock buffer
6, TMP102 temperature sensor
7, yes
8, no.

 
sch and PCB design files will release to github this week.

add order details and some new pictures.

for Chinese readers only:

yep, so we must use manually PAR. this really cost a LOT of man hour which is very very expensive.

PS:

i will check and answer personal messages after i finish the bitsteam work, unless you placed a developer order.

yeah, so i don't like  to withdraw any pre-order money to give me any more pressure when i focus on doing something.

these days:
still very busy at multiple works. 70% is school work, and i put all my spare time on lancelot project. to 3~4:00AM everyday.

i work together with the software guys, now the new bitsteam is doing the optimization work. we must push it to 500-550MH/s.

hardware is ready 5 days ago.

a reason of delay is one of the software guy go to USA, we only have another 1 people to do the work. (not including me) a good news is he will come back at 2/8, but we want to release the bitsteam earlier.

apologize for any misbehavior about didn't replay the PMs or mails.

PS:

accept bitsteam developer orders form now.

smart 

The answer is a big YES.
But only for MY Icarus customers. 

 
wait for a few days.

certainly, will release both .bit and .mcs files.

i will release .mcs files for all bitsteams, unless it's a UNrecommended test bitsteam (like 200m beta).

 

V4 ..

will have a final bitsteam update next week(i hope). and completely change the architecture.
please wait for that before do any optimization effort.

UP.

add some information. 

sorry guys, i'm extremely busy these days... my adviser give me tons of work to do, and i review the HDL codes with other developers to mid-night everyday. 

will catch up with all emails and messages next week.

yes， it didn't scan the nonce range form 0. approx: 132

maybe, but not optimism as their delivery date.

we (my team and some other core people) consider BFL have not spend any money on ASIC development yet. BFL's business flow is: announce dreamlike specs -> taking pre-orders -> find people to development -> if succeed, release and shipment. if fail, run. BFL sell products at super low price because their customer take all risks.
so now BFL is just collecting money for their ASIC project and avoid current delivery pressure (means they are running out cheap FPGAs).
if this business model succeeded, i will classified this as a shame of human intelligence.

and let me explain what is the "now in final stage development" mean. in ASIC design flow, this means RTL design is nearly finish. as a SOC or some other complex ASIC, RTL design and testing will take most of the development time. but mining ASIC is not a RTL complex design, it is a high computing density chip. most of the work is physical design, packaging and thermal design. RTL is less than 10% of the entire work.


nearly finish.
the price will let the ROI in ~6 months.

  let's see what will happen in the next 6 months.

ok, report is here:
good news:
fixed all small bugs on the present Lancelot PCB, waiting for heat-sink sample for a final check. will push it to production stage. that means Lancelot will come out in batch in ~3 weeks. 
bad news:
bitsteam build meet with some difficulties. no ETA can be  estimate. 

should i make Lancelot as a hardware platform only? you know there are a mass of 3-rd party mining bitsteams, and running really fast. is it good for me to sell Lancelot at a extreme low price and cooperate with those bitsteam makers?  Lancelot have the best power module(14A continuous and 25A peak, 85% efficiency, for each FPGA) and  encryption support (eFuse key  storage and volatile memory key storage). and opensourced. 


about the mining ASIC:

it's really easy to make a mining ASIC, but hard to make a "good" mining ASIC. that's  my point of view.

PS: please feel free to discuss or off topic in my thread. i'm a chinese and in chinese forums, all threads are off topic. it's  a usually situation for me.