I need this one post so that I can post a post where I want to post.

Will do, thanks a lot!

Many many thanks for that. It didn't take me long to get working. The import for worker.theseven.simplers232 needed adding to my config.py.

I'll send a few bitcoins your way for your help (not sure what's a reasonable rate, 1?)  and keep the other pools active too, although I won't be mining constantly.

Is there any chance you'd let me have your vhdl code and ucf file for it too? One of the reasons I was interested in getting it working was to practice my VHDL. I'd understand if you wanted to keep that to yourself however. There's also a board with a Virtex-6 LX760 lying around that I might be able to test it on, not sure if anyone's tried that yet.

Thanks again.

Hi

I realise this is probably unlikely to happen, but I've joined as I'd really like some advice from TheSeven if they have the time. I have the same XUPV5 -LZ110T FPGA board as you (I think, judging by a picture I saw) and I'm trying to get the VHDL miner to work.

Firstly, I could only get it to synthesize when I reduced the depth, it was 6, I now have it at 2, it might work higher but I haven't tested it yet, is this to be expected? Also, what should I connect the clk_in port to? I had to it connected to CLK_33MHZ_FPGA (AH17) but got errors from the python program saying that it timed out waiting for a response. I then read the post about adjusting the UART clock divider, which I attempted to do based on the formulas you posted, but then got the "got bad message from fpga: 28" error.

Basically, am I connecting the right pin to clk_in? I'm just trying it with CLK_27MHZ_FPGA now. Is there anything else I should be changing, such as CLKIN_PERIOD in top.vhd? I have tried changing it to 30ns (i.e. 1/33MHz-ish) with no joy.

Hopefully you'll read this, or someone else might help.

Thanks for reading..

Hi 

I'm a PhD student from the UK and mainly wanted joined to try to get some help getting the FPGA miner working on the board that sits on my desk doing nothing most of the time.