25-09-2012: First Look at BFL's ASIC Hardware (Coding In My Sleep)

[JMAHH]

(concerns Single SC's)

http://codinginmysleep.com/first-look-at-bfls-asic-hardware/

[The-Real-Link]

Very neat.

[BTC-engineer]

(concerns Single SC's)

http://codinginmysleep.com/first-look-at-bfls-asic-hardware/

Nice.
But it looks to me like this is not the final version of the board, because some components are hanging over the edge of the PCB.

[QuantumQrack]

Great, some 3D representations of the boards.  If this is all they have at the moment, then I would say the shipments are a hell of a long way off.  We now return to our originally scheduled program:  http://www.youtube.com/watch?v=DIslhp9vqqw

[Littleshop]

This shows a simple assumption of mine is probably right.  I thought that the Jalapeno would be a single chip and the single would not be a single but a combination of Jalapeno chips.  Of course the math does not add up, I see 8 ASICS there and 8 x 3.5 does not equal 40.....  Maybe I am wrong or the Jalapeno is downclocked?

[Fjordbit]

This shows a simple assumption of mine is probably right.  I thought that the Jalapeno would be a single chip and the single would not be a single but a combination of Jalapeno chips.  Of course the math does not add up, I see 8 ASICS there and 8 x 3.5 does not equal 40.....  Maybe I am wrong or the Jalapeno is downclocked?

The current theory is that the chips are made and the ones that don't rate 5.0 GHps get put into the Jalapeno pile.

[szuetam]

This shows a simple assumption of mine is probably right.  I thought that the Jalapeno would be a single chip and the single would not be a single but a combination of Jalapeno chips.  Of course the math does not add up, I see 8 ASICS there and 8 x 3.5 does not equal 40.....  Maybe I am wrong or the Jalapeno is downclocked?

The current theory is that the chips are made and the ones that don't rate 5.0 GHps get put into the Jalapeno pile.

Is there going to be some fan with jalapeno?

[crazyates]

This shows a simple assumption of mine is probably right.  I thought that the Jalapeno would be a single chip and the single would not be a single but a combination of Jalapeno chips.  Of course the math does not add up, I see 8 ASICS there and 8 x 3.5 does not equal 40.....  Maybe I am wrong or the Jalapeno is downclocked?

The current theory is that the chips are made and the ones that don't rate 5.0 GHps get put into the Jalapeno pile.

Is there going to be some fan with jalapeno?

A heansink/enclosure that only needs to dissipate 5W worth of heat doesn't really need a fan.

[jjiimm_64]

Great, some 3D representations of the boards.  If this is all they have at the moment, then I would say the shipments are a hell of a long way off.  We now return to our originally scheduled program:  http://www.youtube.com/watch?v=DIslhp9vqqw

This image could be from 4 months ago....  they are not going to publicly release the most current info!

[420]

Great, some 3D representations of the boards.  If this is all they have at the moment, then I would say the shipments are a hell of a long way off.  We now return to our originally scheduled program:  http://www.youtube.com/watch?v=DIslhp9vqqw

awww