Logo Competition:We will announce a winner this week.
A1, BitMain and BitFury ChipsThe 2 - A1 samples got delivered today. Our feeling is that a Metal-core PCB for the A1s and their buck controllers is necessary, and then cutting slots in the FR4 Wasp will allow us to attach copper heatsinks to the metalcore, and Bergquist pads to the tops of the chips and the passives, filling the gap for an aluminum sink for the top. Hoping this initial prototype design keep the temps down in the 40s, with air. All this is necessary so as to increase the potential lifetime of these A1 first run prototype chips. This all takes time so the A1 prototype will be later than the prototype PCB's for the BitMain / BitFury Wasps. Soon as we have working prototypes we will release that information on our website. BitFury will be the first prototype to be built followed closely by the BitMain and then A1. We plan on a Minion Wasp prototype beyond these 3 initial chips. The members have put in all the funding required to pay for all the components, chips and fabrication.
WPC Mining PoolLatest update is that the whole pool team now has access to the servers and that means it is only a matter of days before we have the pool up for testing.
Membership:We are keen to find more firmware people to help develop a range of functions we have planned for the Wasp & Hive. If you have experience in the following areas or are keen to learn and have some background in firmware please PM me with your skills set and experience. I will push that information to our EE and see if that is what we require. If he is good with that then we can expedite your membership on that basis. As for those without those skills sets at this time we are going to hold off any new members until at least February and all membership will be through the website at that point.
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Firmware Objectives by SystemThis system has the following objectives:- provide initialization of MCU resources in a safe sequence, and configuration of pin assignments that connect processor resources to their off-chip nets as specified
- provide safely sequenced initialization of off-chip resources such as CPLD programming, bus-power distribution fail-safes, and regulator initial configuration
- provide safe access abstractions for use of on-chip and off-chip resources, once they have been initialized
- provide a launch service for tasks of both classes, allowing them to register for scheduling, and to perform any requisite initialization on their data structures prior to scheduling startup
- schedule real-time bounded tasks in a fixed priority rotation
- schedule background tasks in round-robin dispatch mode, whenever no real-time tasks are ready
- preserve non-real-time context when a background task is preempted , and restore that context after the real-time tasks have all been serviced
- provide a single-shot timed event service with a minimum interval approximating 256 uS, and allow those events to be cancelled before they occur
- provide a watchdog service that prevents firmware failures from rendering the device inaccessible
- provide a fail-safe power distribution system controller, and keep it running
- provide services for driving multi-color LEDs with on-board Pulse Width Modulators, both hardware and firmware implementations
- provide safe shutdown services that can rapidly bring the system to a known-safe operational state
Operating Environment Layer Subsystems- Initialization Subsystem
- Thread Launcher Subsystem
- Low Level I/O Subsystem
- Task Scheduler and Timer Subsystem
- Watchdog Subsystem
- Fail-safe Power Distribution Subsystem
- Shutdown Subsystem
- Registry Subsystem
Communications Layer Subsystems
ObjectivesThe communications layer has the following objectives for providing services to the application:
- provide an API for sending and receiving SPI messages
- provide an API for sending and receiving TWI messages
- provide an API for sending and receiving PMBUS messages, using the TWI transport
- provide an API for using the USB client link, including device descriptors and multiple endpoints
- provide the necessary management of an endpoint for Device Firmware Update (DFU) protocols
Communication Subsystems - SPI Subsystem
- TWI Subsystem
- PMBUS Subsystem
- USB Subsystem
- DFU Subsystem
Firmware Development GuidelineDevelopers please note the following process for source code management.
GIT Repository Guidelines To avoid chaos in the production and developer (a.k.a. examples) source repositories, please follow these guidelines:
- code for Atmel dev boards or non-production hardware belongs in xxxxxxxxxxxxxxxxxxxxxxxxx
- code for production and pre-production hardware belongs in xxxxxxxxxxxxxxxxxxxxxx
- your development code belongs in a personal branch of the appropriate repository. The master branch is used ONLY for polished bug-free code.
- the tip of the master branch of all repositories must always build and be as bug-free as possible. I.e. DO NOT check into the master branch development code with known bugs or that does not compile and run on device hardware. Again, development code belongs in a personal branch of the appropriate repository.
Following these guidelines will minimize the time wasted by developers chasing bugs that have been introduced into the source tree by another's unfinished code. They should easy be easy to follow since creating and managing code branches is what GIT is all about.
How to Add a New App to the CodebaseIn the wasps repository there is an Atmel Studio solution with a library and two application projects. To add a new application that uses the library:
- create new debug and release solution configurations in visual studio with the name of the application in the configuration; e.g. 'Debug_bitfury' and 'Release_bitfury'
- add a new application project to the solution with name that matches or can be identified with the new configuration names; e.g. 'bitfury' or 'bitfuryWasp'
- in Configuration Manager specify that only the library and new application project are built for each new build configuration
- modify library and application project settings:
- for library project in Toolchain >> Compiler >> Symbols add APPID=<new app name>; e.g. APPID=BITFURY
- for app project in Toolchain >> Linker >> Libraries >> 'Library search path' add path to directory where the linker will place the library built for this configuration
- add any other symbols needed to compile the library for the specific to the app. The number of these definitions should be few to none since every special case introduced into the library makes it more fragile and harder to maintain.
- in the library project compiler symbols define LIB_BUILD
APPID can be used in library code to build anything needed in the library for this specific app. Again, this should be done VERY sparingly and only when absolutely necessary.
LIB_BUILD is used in the library header file so that the header can be included in both the library and app builds.
Atmel Dev ToolsTo develop firmware and learn firmware development for AVR-based Wasps, we use the following tools:
JTAGICE3UC3-A3 Xplained dev board XMEGA256-A3BU Xplained dev boardAtmel Studio (free download) Atmel tools and development kits are available from
Atmel,
Mouser,
DigiKey and other sources. Mouser and Digikey are recommended over Atmel since they usually ship more quickly.
The following videos provide a good introduction to the development process for Atmel parts and boards using Atmel Studio and Atmel Software Framework (ASF).
A software design process for the ASF ASF Getting Started 1 ASF Getting Started 2These videos describe how to use Atmel Studio to create a customized ASF-based library for specific hardware and a single firmware application. Follow the described processes to learn how to write firmware for Atmel dev boards or non-wasp hardware.
For production wasp firmware, we will need to modify the processes described in the video since we want to create a single ASF-based library customized for wasp hardware, but this library will be used by many firmware applications: namely, one application for each for type of wasp and probably (a) test/diagnostic application(s) for each wasp as well.
MAX V CPLD Dev ToolsTools for CPLD firmware are a development board, downloadable development software and tutorial pdf and video. Downloads may require login to free Altera account:
DK-DEV-5M570ZN" development board Quartus II Web Edition" development software (free download) "My First FPGA" Tutorial (login to free acct may be required) "Introduction to Quartus II" and the FPGA (or CPLD) design process
