Ah, then you should edit the OP topic title like I just did to reflect your actual question...
That said, it is probably a combination of both the chips and pools limiting it to 4 midstates. My guess is that the chip circuitry only supports 4 and the pools expect that. The
whitepaper on AsicBoost makes mention of it increasing chip complexity and to the Foundries making chips complexity = higher cost. I seem to recall discussion long long ago when ASICboost was introduced about using more midstates introducing too much lag into the miner communications which is why using 4 was settled on as a good compromise.
