"Avalon" ASIC, announcement & pre-order. pre-order over. project started.

[ngzhang]

Hi Dr.Zhang,

I am glad to hear this news.

How could customers inside of China to order it ?  Through taobao ?  or contact with you via email directly ?

我也在具体考虑这件事。不过国内的话，很容易吧。

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[kano]

Hmm - actually I'm a little surprised - the embedded linux - what will it be?

There are some advantages to having the device just a device and not a completely contained computer.
. Things like having less hardware to fail and thus less problems
. Allowing a much broader choice of network configuration
. Not having to regularly update the controller software
. Self contained means an all in one failure point?
. Self contained means a higher cost due to supplying hardware that many already have (a computer)

Though of course there are the advantages of having it self contained also.
Mainly to simplify it's use for the technically challenged

I wonder if you would consider two versions:
The second one as a pure mining device like we have now with most FPGA - a USB device you plug into a computer with multiple internal mining devices to also solve the issue of having a single failure that wipes out everything?

Just putting out ideas - since you've said it not final yet

[flynn]

Though of course there are the advantages of having it self contained also.
Mainly to simplify it's use for the technically challenged

IMO it simplifies clusters. And we know ngzhang has been considering this point quite a lot with his FPGA boards.
Also, if the system is only one board, it simplifies the communications between the ASIC and the CPU
Not to mention the fact that one 60GH board on a computer is one thing, 10x60GH board one one single computer may be a problem to allocate work from the pool at a decent rate. With this architecture, the problem is up to the pool, not the computer.

But it's just my opinion.

[Carlton Banks]

Though of course there are the advantages of having it self contained also.
Mainly to simplify it's use for the technically challenged

IMO it simplifies clusters. And we know ngzhang has been considering this point quite a lot with his FPGA boards.
Also, if the system is only one board, it simplifies the communications between the ASIC and the CPU
Not to mention the fact that one 60GH board on a computer is one thing, 10x60GH board one one single computer may be a problem to allocate work from the pool at a decent rate. With this architecture, the problem is up to the pool, not the computer.

But it's just my opinion.

I agree broadly, mining software allocating 60GH/s of work is not going to be an insignificant load on the CPU that's running the show, particularly if the CPU is just an off the shelf ARM Cortex (imagine a single Cortex running 60GH/s of FPGAs). Avalon could potentially be a pretty power efficient device should this be the case.

[gyverlb]

I agree broadly, mining software allocating 60GH/s of work is not going to be an insignificant load on the CPU that's running the show, particularly if the CPU is just an off the shelf ARM Cortex (imagine a single Cortex running 60GH/s of FPGAs). Avalon could potentially be a pretty power efficient device should this be the case.

You are kidding right ? 60GH/s -> ~15 nonce ranges/s. If the CPU load is anything but a small blip even on a Raspberry Pi, change your miner software.

[kano]

I agree broadly, mining software allocating 60GH/s of work is not going to be an insignificant load on the CPU that's running the show, particularly if the CPU is just an off the shelf ARM Cortex (imagine a single Cortex running 60GH/s of FPGAs). Avalon could potentially be a pretty power efficient device should this be the case.

You are kidding right ? 60GH/s -> ~15 nonce ranges/s. If the CPU load is anything but a small blip even on a Raspberry Pi, change your miner software.

Well ... I know one person mining with 2 MiniRigs ~51GH/s that uses less than 2% on his CPU.
I'll get the info later about the CPU and the downclock it's running also ...

[ngzhang]

the controller itself only cost about 15USD. running open-wrt OS.

[crazyates]

Very interesting! Your MHs/$ beats the competition, and that's what I care the most about.

[Carlton Banks]

I agree broadly, mining software allocating 60GH/s of work is not going to be an insignificant load on the CPU that's running the show, particularly if the CPU is just an off the shelf ARM Cortex (imagine a single Cortex running 60GH/s of FPGAs). Avalon could potentially be a pretty power efficient device should this be the case.

You are kidding right ? 60GH/s -> ~15 nonce ranges/s. If the CPU load is anything but a small blip even on a Raspberry Pi, change your miner software.

the controller itself only cost about 15USD. running open-wrt OS.

Well, it appears then that with the right kind of lean hardware and software combination, it's achievable. If that's all possible with <2% rejects/invalids, it would be impressive.

[ragingazn628]

I'm interested in buying one

[nedbert9]

I'm glad to see you enter the asic market, ngzhang.

I'm sure it will be a quality product.  Clever move by using open wrt.


Technical questions:

How many asic chips per pcb?
Unit dimensions?
Cgminer has DD WRT support on mipsel chip.  Do you foresee any problem with open wrt/chip and cgminer? (This question is better put to the miner dev's, but knowing what type of embedded chip is important)
At ~600W per unit, what heat management solution will be used?

[tacotime]

At ~600W per unit, what heat management solution will be used?

I would guess it will be computationally split between 6-10 dies...  This would enhance yield.  I doubt they would be making 4000mm^2 dies as that's pretty much unheard of.  And then those smaller dies would be cooled with $10 HSFs.

[Valle]

All these asic preorderings looks like scam. Yes, and the BFL's preorderings also does not look good. There are no photos, no documents, no ID papers, links, prototype tests, nothing, but everybody are in "final stage" and take money.

[crazyates]

All these asic preorderings looks like scam. Yes, and the BFL's preorderings also does not look good. There are no photos, no documents, no ID papers, links, prototype tests, nothing, but everybody are in "final stage" and take money.

Take it elsewhere.

[Sitarow]

Great News!

Hope that the pre-orders get filled!

So we can't pre-order until the websites up?

[eestimees]

Thumbs up! 

[theasian09]

3, this ASIC will manufacture by SIMC.  0.11 or 0.13 process.

Couldnt find a company called SIMC (maybe I just suck with google) do you mean SMIC?

[ngzhang]

I'm glad to see you enter the asic market, ngzhang.

I'm sure it will be a quality product.  Clever move by using open wrt.


Technical questions:

How many asic chips per pcb?
Unit dimensions?
Cgminer has DD WRT support on mipsel chip.  Do you foresee any problem with open wrt/chip and cgminer? (This question is better put to the miner dev's, but knowing what type of embedded chip is important)
At ~600W per unit, what heat management solution will be used?

quick answer:
1, our plan is about 15~ 30 very small chips per 60GHs machine.  means: 2~4GHs pre chip.
2, will much smaller than a normal MicroATX case. you can just imagine it as a small ITX case.
3, similar controller is already running.
4, forgot the 600Watt number please. but we will design a chip have some "Steampunk style" to handle the heat.

At ~600W per unit, what heat management solution will be used?

I would guess it will be computationally split between 6-10 dies...  This would enhance yield.  I doubt they would be making 4000mm^2 dies as that's pretty much unheard of.  And then those smaller dies would be cooled with $10 HSFs.

maybe more dies. and the heat-sink will about 0.03$/ea. reduce cost is very important.  

All these asic preorderings looks like scam. Yes, and the BFL's preorderings also does not look good. There are no photos, no documents, no ID papers, links, prototype tests, nothing, but everybody are in "final stage" and take money.

i understand your worry about. i think now what i have is only my personal reputation but i ensure Avalon project will much transparent than any other project. during Oct. we will have enough technique details. include documents, accurate specs, etc.

Great News!

Hope that the pre-orders get filled!

So we can't pre-order until the websites up?

yep, but please give me your intention by e-mail. it's very important for me to adjust the plan.

3, this ASIC will manufacture by SIMC.  0.11 or 0.13 process.

Couldnt find a company called SIMC (maybe I just suck with google) do you mean SMIC?

sorry, it's a stupid typing mistake.. 

[theasian09]

I will be incredibly excited if I see an order for test equipment from smic with a device name of "avalon" on my desk in the near future, but I am guessing it wont happen.

[Valle]

i understand your worry about. i think now what i have is only my personal reputation but i ensure Avalon project will much transparent than any other project. during Oct. we will have enough technique details. include documents, accurate specs, etc.

Thank you! I would be happy to find out that I'm wrong now. Please don't think that I want to insult anyone, I just want people make good and weighted decisions.