Why is Butterfly Labs so secretive?

[Unacceptable]

I demand to know what color socks each employee wears. Until I have photos of each employee's foot next to a driver's license, I will assume that BFL is a scam.

Yeah,what HE said!!!!!!!!!!!!!!!!

Also,what kind of cars do they drive??? So I can understand how long it takes them to get to work & how much gas they use!!!!!!!!!!!

[1713898522]

1713898522

[1713898522]

1713898522

[1713898522]

1713898522

[1713898522]

1713898522

[1713898522]

1713898522

[1713898522]

1713898522

[Bogart]

I think BFL appreciates the art of trolling.

Just look at how worked up they have y'all in here.

[enmaku]

I demand to know what color socks each employee wears. Until I have photos of each employee's foot next to a driver's license, I will assume that BFL is a scam.

Funniest thing I've read all day, and man did I need a laugh today

[scrybe]

Ask BFL if they have talked to any Gov officials. I am not the spokes person lol

No, I'm asking you if you filed a complaint, and what the status of that complaint is.

I'm not going to interrogate a vendor on something that I don't think is an issue. They have passed the bar for Snake Oil, I was wondering how loud the AG's office laughed, or if they just told you to contact them if BFL failed to ship.

[Zeek_W]

I think we all need to:

http://www.youtube.com/watch?v=sGWEI390Pe8

 

[scrybe]

Companies like Intel are selling products that are available in stores, people do not have to ask questions to find out whether their products work. just buy.

I seem to remember Pentium75 and Pentium90 couldn't add two floating point number together without crashing.

They do not build computers out of FPGA's

Many 8bit computers were FPGAs

That was the Pentium 60 and 66. (additional trivia, too many chips failed at 66, so they released at 60Mhz instead, lead times on the 66Mhz chips were bad for a few months)

(IIRC) It was an actual mistake in an x87 multiplier and was the trigger that caused Intel to add microcode update capabilities to the Pentium 75+

That is a great example because BFL et. al. face a similar risk. What if you get 60Gh/s of rejects when the ASIC comes back from the foundry?

[scrybe]

Companies like Intel are selling products that are available in stores, people do not have to ask questions to find out whether their products work. just buy.

I seem to remember Pentium75 and Pentium90 couldn't add two floating point number together without crashing.

I seem to remember Pentium 60 - had more bugs. What if the chip from the BFL will have bugs? No one has ever done ASICs at such a level as BFL, is a new technology.  They want to spend a few days only on  testing of their chips.
I found only a few ready-made ASIC to sha256:

http://www.heliontech.com/downloads/fast_hash_asic_datasheet.pdf#view=Fit
http://www.cast-inc.com/ip-cores/encryption/sha-256/index.html
Hardcopy HC210F48-C - ALTERA

All of these chips offer several % of performance which offer BFL.

That was a cutting edge process at the time. All the BFL ASICs appear to be happening on process nodes that are 7-10+ years old, so the chances of a technology failure are low. Since everyone has done a prototype run (I think) at this point, the chances of a fundamental logic error are fairly low.

[scrybe]

I demand to know what color socks each employee wears. Until I have photos of each employee's foot next to a driver's license, I will assume that BFL is a scam.

Yeah,what HE said!!!!!!!!!!!!!!!!

Also,what kind of cars do they drive??? So I can understand how long it takes them to get to work & how much gas they use!!!!!!!!!!!

+1

[DoomDumas]

  Never invest what you can't afford to lose.
 Unhappy with BLF ? Ask for a refund and buy elsewhere.
Stop crying about info or delays, as the promise date is'nt even met.

I bought from BLF (preorder) and I'll take it when it will arrive at my doorstep...  whenever !

Happy to buy from BFL !

[BitcoinINV]

Im sure they laughed at me just like Inaba did or as they call him BFL_Josh. Same way people said I was bullshiting when I said I talked to the S.E.C lol

I call Shennanigans!

Kinda felt like you were calling me out so have at it, and yes I have been contacted by My attorney general. Once again another closed investigation lol


Edit: forgot to add A federal agent added a note to it aswell.... guess which one lol

[PuertoLibre]

Companies like Intel are selling products that are available in stores, people do not have to ask questions to find out whether their products work. just buy.

I seem to remember Pentium75 and Pentium90 couldn't add two floating point number together without crashing.

They do not build computers out of FPGA's

Many 8bit computers were FPGAs

That was the Pentium 60 and 66. (additional trivia, too many chips failed at 66, so they released at 60Mhz instead, lead times on the 66Mhz chips were bad for a few months)

(IIRC) It was an actual mistake in an x87 multiplier and was the trigger that caused Intel to add microcode update capabilities to the Pentium 75+

That is a great example because BFL et. al. face a similar risk. What if you get 60Gh/s of rejects when the ASIC comes back from the foundry?

Just make them into Little Singles? BTC

[scrybe]

Im sure they laughed at me just like Inaba did or as they call him BFL_Josh. Same way people said I was bullshiting when I said I talked to the S.E.C lol

I call Shennanigans!

Kinda felt like you were calling me out so have at it, and yes I have been contacted by My attorney general. Once again another closed investigation lol

So they are required to respond to the AG's office by 10/20. How is that case closed? I'm interested to see what the response is. I'm betting it will be a rehash of information that is already released along with their existing statements as to the utility and performance of the product.

FYI, just because this was sent does not mean that Josh or anyone else we have contact with at BFL has direct knowledge of it. In our company the Finance and Legal guys would handle it without anyone that produces for he company being bothered by it.

Thanks for going all out with the photos, it helps a bunch! I eagerly await a response in a week or so.

[bitmar]

Nobody produces ASICs to achieve several times better performance than FPGAs, there are other advantages.

Gibberish.

I wrote - several times faster. ASIC may indeed be faster than FPGAs, but this is not so big difference. This is the difference of approximately to 100%, no  1000% and more.  BFL offers us about 500% faster ASIC than existing FPGA.

I found an old comparison table:

and newer:
http://www.heliontech.com/fast_hash.htm

What you need to understand is that this table does not show how many hashing cores can be placed on a chip.

The XC2V2000 for example only has 10 thousand slices. The table shows a SHA-256 core takes ~1000 slices and does ~1Gbps [16], so by putting 10 cores per FPGA the whole chip would do only ~10Gbps.

On the other hand, a 180nm ASIC of small size (50mm^2) has about 10 million gates. The table shows a SHA-256 core takes ~20 thousand gates and does ~2Gbps [21], so by putting 500 cores per ASIC the whole chip would do ~1000 Gbps.

Tada! There is your 100x difference. Roughly what BFL is promising (Single 832 Mhash/s vs. Single SC 60 Ghash/s.)

it is easy to say in theory, try to do this in practice  
more gates = more heat = lower frequency
more core = more heat = lower frequency
you can not use gates and cores as you like Sometimes, in some operations less gates at a higher frequency will give better performance than many gates at low frequency.
From what gives BFL: working frequency, energy consumption, they must use the 90nm process technology or below. (http://csrc.nist.gov/groups/ST/hash/sha-3/Round2/Aug2010/documents/papers/SCHAUMONT_SHA3.pdf) .

ASIC 90nm technologies and lower are very expensive, so if they gathered enough money, they have a chance of success of course.
(http://www.design-reuse.com/articles/12360/fpgas-and-structured-asics-low-risk-soc-for-the-masses.html
http://www.dz.ee.ethz.ch/?id=1592 -> http://www.dz.ee.ethz.ch/fileadmin/user_upload/dz/files/asiccostestimator.xls  ->  ASIC cost estimator)
The standard ASIC designs are still in 130nm, although this technology has more than 10 years. This is why the current FPGAs are often better than the ASIC. Of course, this is changing. (http://www.eetimes.com/electronics-blogs/eda-designline-blog/4375159/Will-your-next-ASIC-ever-be-an-FPGA-#164386). That is why I wrote (a few posts up) that BFL is entering a new level of technology. BFL creates a very ambitious project,  creates a "FAST HASH ASIC" fastest ever existed. It's very exciting to watch how they create such an ambitious project with such a small budget it is amazing LOL  

 

[mrb]

Nobody produces ASICs to achieve several times better performance than FPGAs, there are other advantages.

Gibberish.

I wrote - several times faster. ASIC may indeed be faster than FPGAs, but this is not so big difference. This is the difference of approximately to 100%, no  1000% and more.  BFL offers us about 500% faster ASIC than existing FPGA.

I found an old comparison table:

and newer:
http://www.heliontech.com/fast_hash.htm

What you need to understand is that this table does not show how many hashing cores can be placed on a chip.

The XC2V2000 for example only has 10 thousand slices. The table shows a SHA-256 core takes ~1000 slices and does ~1Gbps [16], so by putting 10 cores per FPGA the whole chip would do only ~10Gbps.

On the other hand, a 180nm ASIC of small size (50mm^2) has about 10 million gates. The table shows a SHA-256 core takes ~20 thousand gates and does ~2Gbps [21], so by putting 500 cores per ASIC the whole chip would do ~1000 Gbps.

Tada! There is your 100x difference. Roughly what BFL is promising (Single 832 Mhash/s vs. Single SC 60 Ghash/s.)

it is easy to say in theory, try to do this in practice  

Actually, yes, it is easy to do and has been done. To continue my example, a 180nm ASIC with 10+ million gates at 350MHz+ was done 13 years ago by Intel with the Pentium III 500E: 180nm, 28 million gates, 500MHz, at a tiny 13 Watt(!) http://en.wikipedia.org/wiki/List_of_Intel_Pentium_III_microprocessors#.22Coppermine.22_.28180_nm.29

I personally estimate BFL developed at 65nm, which is only $500k in NRE costs: https://bitcointalk.org/index.php?topic=95762.0 By all estimates, they have at least $1.5M+ of preorders (85+ Thash/s), so yeah they can afford 65nm.

If you don't believe that BFL can do at least as good as that, then please put your money where your mouth is by betting on http://betsofbitco.in/item?id=665 (I did with 50 BTC). You could double your money if you are right.

[bitmar]

Nobody produces ASICs to achieve several times better performance than FPGAs, there are other advantages.

Gibberish.

I wrote - several times faster. ASIC may indeed be faster than FPGAs, but this is not so big difference. This is the difference of approximately to 100%, no  1000% and more.  BFL offers us about 500% faster ASIC than existing FPGA.

I found an old comparison table:

and newer:
http://www.heliontech.com/fast_hash.htm

What you need to understand is that this table does not show how many hashing cores can be placed on a chip.

The XC2V2000 for example only has 10 thousand slices. The table shows a SHA-256 core takes ~1000 slices and does ~1Gbps [16], so by putting 10 cores per FPGA the whole chip would do only ~10Gbps.

On the other hand, a 180nm ASIC of small size (50mm^2) has about 10 million gates. The table shows a SHA-256 core takes ~20 thousand gates and does ~2Gbps [21], so by putting 500 cores per ASIC the whole chip would do ~1000 Gbps.

Tada! There is your 100x difference. Roughly what BFL is promising (Single 832 Mhash/s vs. Single SC 60 Ghash/s.)

it is easy to say in theory, try to do this in practice  

Actually, yes, it is easy to do and has been done. To continue my example, a 180nm ASIC with 10+ million gates at 350MHz+ was done 13 years ago by Intel with the Pentium III 500E: 180nm, 28 million gates, 500MHz, at a tiny 13 Watt(!) http://en.wikipedia.org/wiki/List_of_Intel_Pentium_III_microprocessors#.22Coppermine.22_.28180_nm.29

If you don't believe that BFL can do at least as good as that, then please put your money where your mouth is by betting on http://betsofbitco.in/item?id=665 (I did with 50 BTC). You could double your money if you are right.

what you wrote does not bring anything to the discussion. Do not compare CPU with ASIC. Do not compare Intel with BFL. Gbps <> Ghash / s (http://Http://www.sisoftware.net/?d=qa&f=cpu_vs_gpu_crypto). It was a old comparison of the old ASIC to old FPGA. ASIC technology is now better and also FPGA technology. FPGA technology is more advanced than ASIC technology.

[mrb]

You bring that table to attempt to prove your point, then find out it proves you wrong, so you retract it saying it is old and does not apply anymore?  

The observation I made from this table is still valid to this day. I was comparing one of its 180nm ASIC with a 120nm Virtex 2 FPGA (180/120 = 1.5x feature scale difference). Today, you would be comparing a 65nm ASIC (presumed process node for BFL ASIC) against the 45nm FPGAs that all other Bitcoin mining vendor use (Spartan6 LX150), that's a 65/45 = 1.4x feature scale difference. So in both cases the power efficiency of FPGAs over the ASICs (that I am comparing them with) is the same, because power efficiency is directly inversely proportional to the square of the feature size.

One more time: please put your money where you mouth is if you are so convinced of yourself: http://betsofbitco.in/item?id=665

[bitmar]

You bring that table to attempt to prove your point, then find out it proves you wrong, so you retract it saying it is old and does not apply anymore?  

The observation I made from this table is still valid to this day. I was comparing one of its 180nm ASIC with a 120nm Virtex 2 FPGA (180/120 = 1.5x feature scale difference). Today, you would be comparing a 65nm ASIC (presumed process node for BFL ASIC) against the 45nm FPGAs that all other Bitcoin mining vendor use (Spartan6 LX150), that's a 65/45 = 1.4x feature scale difference. So in both cases the power efficiency of FPGAs over the ASICs (that I am comparing them with) is the same, because power efficiency is directly inversely proportional to the square of the feature size.

One more time: please put your money where you mouth is if you are so convinced of yourself: http://betsofbitco.in/item?id=665

You trying to say that a typical 65nm ASIC is "several times faster" than a typical 45nm FPGA? what order of magnitude is the difference? I think many of us are interesting your observation. Do you know what is avarage costs of production  65nm ASIC?



"You bring that table to attempt to prove your point, then find out it proves you wrong, so you retract it saying it is old and does not apply anymore?  "
See how I signed table  

You do not proved anything except that ASIC is more energy efficient. I know it. Conversation is whether ASIC can be "several times faster" than a similar FPGA.

[Meatball]

I just don't get these people that have such a hate on for BFL.  If you don't like what they're doing or think they're shady, just go elsewhere with your business.  Every company under the sun is crazy secretive.  Go to Coke or Pepsi and ask for their formula and see what you get. 

If another ASIC company is giving you more info than BFL and you trust them more, then by all means, spend your money with them.  Just cut it out with all these frigging "BFL is Cthulu!" posts arleady, I'm getting tired of reading them.

[bitmar]

I just don't get these people that have such a hate on for BFL.  If you don't like what they're doing or think they're shady, just go elsewhere with your business.  Every company under the sun is crazy secretive.  Go to Coke or Pepsi and ask for their formula and see what you get.  

If another ASIC company is giving you more info than BFL and you trust them more, then by all means, spend your money with them.  Just cut it out with all these frigging "BFL is Cthulu!" posts arleady, I'm getting tired of reading them.

Who hate BFL ? and why ?

[scrybe]

You bring that table to attempt to prove your point, then find out it proves you wrong, so you retract it saying it is old and does not apply anymore?  

The observation I made from this table is still valid to this day. I was comparing one of its 180nm ASIC with a 120nm Virtex 2 FPGA (180/120 = 1.5x feature scale difference). Today, you would be comparing a 65nm ASIC (presumed process node for BFL ASIC) against the 45nm FPGAs that all other Bitcoin mining vendor use (Spartan6 LX150), that's a 65/45 = 1.4x feature scale difference. So in both cases the power efficiency of FPGAs over the ASICs (that I am comparing them with) is the same, because power efficiency is directly inversely proportional to the square of the feature size.

One more time: please put your money where you mouth is if you are so convinced of yourself: http://betsofbitco.in/item?id=665

You trying to say that a typical 65nm ASIC is "several times faster" than a typical 45nm FPGA? what order of magnitude is the difference? I think many of us are interesting your observation. Do you know what is avarage costs of production  65nm ASIC?



"You bring that table to attempt to prove your point, then find out it proves you wrong, so you retract it saying it is old and does not apply anymore?  "
See how I signed table  

You do not proved anything except that ASIC is more energy efficient. I know it. Conversation is whether ASIC can be "several times faster" than a similar FPGA.

FFS: http://en.wikipedia.org/wiki/Field-programmable_gate_array
"Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study has shown that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and are three times slower than the corresponding ASIC implementations.[22]"

40 times less area * 3 times faster = 120x at the same process node

It's really simple guys, every logic block and interconnect needs a bunch of transistors to control them, but on ASIC you just lay the circuit down as you want it to run. Because of this you have far more transistors actually performing the work rather than controlling internal functions.

So even though the underlying features are the same at a given process node, FPGA suffers a disadvantage in area and speed, but makes up for it with flexibility. ASIC is locked in function, but very, very fast at execution.