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Author Topic: [Announcement] Avalon ASIC Development Status [Batch #1]  (Read 154123 times)
loshia
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December 06, 2012, 07:28:22 AM
 #221

I guess they are pretty bad Tongue

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December 06, 2012, 07:30:33 AM
 #222


yeah, some bad news.  Wink
With a smile like that...I am guessing they are about to call BS on certain claims made by other vendors, then list the [technical] reasons why they think it is so?


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December 06, 2012, 07:31:18 AM
 #223

That'd be my take as well. These Avalon guys are having fun milking it anyway. Smiley

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December 06, 2012, 07:36:16 AM
 #224

It could be read either way. English is not their primary language, so the semantics of certain sentences is ambiguous. I was just relating how I primarily read and understood BitSyncom's posts.
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December 06, 2012, 07:37:04 AM
 #225

I am smiling because i feel the news will be good for us for sure. I do not care about other vendors at all. There is pretty good chance Avalon to be the first! that matters for me. No power consumption no hash rate. It is most likely that they will say something good and push the delivery to happen soon. Once again it is just personal feeling..

Please help the Led Boy aka Bicknellski to make us a nice Christmas led tree and pay WASP membership fee here:
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December 06, 2012, 07:37:19 AM
 #226

You guys are all excited, but, to me, it sounds like BitSyncom is about to announce a bad news.

"deciding what to say" -> it is only when the news is bad that time is spent deciding how to say it.

"my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them" -> the last "them" refer to his engineering team, IOW the engineering team was correct to be skeptical of the competition's power efficiency claim, IOW the engineering team found out their own efficiency is a lot worse than the competition (which makes sense given that Avalon is 110nm, which should be theoretically 3x worse in terms of power efficiency when compared to 65nm (BFL)).

"what I'm talking about is actually the very opposite" -> he was expecting better results, but the engineering team's number look bad.
I might be a little tired, but I had a really hard time following you.

Avalon's team's engineers were skeptical of competitors power claims. He chose to plan for the worst and hope for the best, and take the competitors at their word, and temporarily assume the competitor's power draw numbers were accurate. Now however, the Avalon Team's opinions have changed.

So this could mean 2 things:
1) Avalon's competitors really have reached a level of efficiency that the Avalon team can't even get in simulations, and now the Avalon Team has chosen to listen to their engineers and ignore their competitors claims.
2) Avalon's engineering team has made drastic improvements in power efficiency, even into the range that their competitors have been advertising. This means that their competitors were right in their estimates, and means the Avalon's engineering team was previously wrong in their criticism. This also means that the Avalon could be getting lower power numbers than initially estimated?

I'm tired, and so confused.

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December 06, 2012, 07:39:23 AM
 #227

i always thought it's the first one.







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December 06, 2012, 07:41:59 AM
 #228

Hmmm..... I think doing business in this region for over 25 years, gives me just a little perspective on the business practices of the Pearl Delta.
But perhaps brush up a little 武經七書... because I got what I needed faster than I expected.


I think you have no sense of humility after doing business for 25 years in these regions that you lost the ability to talk to another person like a regular human being. I had no intention to hide who these people were, I simply uploaded the picture from my phone on-the-go and now had the chance to do a proper follow up, not to mention many of these faces are not new and often seen in public involving bitcoin.

It would be much appreciated in the future, especially when directing questions at me. Brush up on how to be a gentleman, remove any trace of prejudice and cynicism you have obtained from a past that has nothing to do with me.

Please don't try to give lecture about something you know little about,  I'm very well paid and very good at what I do.

When you have had credible death threats from 'respectable' Asian business men  and attempts to kidnap your wife, come talk to me and we can talk all you want about:
 humility/racism/prejudice/cynicism/corruption/slavery/poisoning of babies/adults for profit or anything else you think you are an expert on.





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December 06, 2012, 07:42:23 AM
 #229

crazyates,
Just do your math. Having asic in your hands with current difficulty and any power consumption = ROI 2 weeks top
From the other hand having ASIC when dif is 30x-50x (and constantly increasing) with zero power consumption = ROI months or even years

 

Please help the Led Boy aka Bicknellski to make us a nice Christmas led tree and pay WASP membership fee here:
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December 06, 2012, 07:58:15 AM
 #230

You guys are all excited, but, to me, it sounds like BitSyncom is about to announce a bad news.

"deciding what to say" -> it is only when the news is bad that time is spent deciding how to say it.

"my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them" -> the last "them" refer to his engineering team, IOW the engineering team was correct to be skeptical of the competition's power efficiency claim, IOW the engineering team found out their own efficiency is a lot worse than the competition (which makes sense given that Avalon is 110nm, which should be theoretically 3x worse in terms of power efficiency when compared to 65nm (BFL)).

"what I'm talking about is actually the very opposite" -> he was expecting better results, but the engineering team's number look bad.

Oh indeed, some bad news is coming, but who I wonder.
Did some competitors fab or subcontractor company implode or something?

(starts shinning the ol' crystal ball)


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December 06, 2012, 08:03:17 AM
 #231

BFL is supposedly getting chips from Asia next week.

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December 06, 2012, 08:16:22 AM
 #232

and bASIC chips have been done for a while (https://www.btcfpga.com/forum/index.php?topic=203.msg1445#msg1445)



I have orders from all 3...I just want someone to ship, so that I can stop checking the forums every fucking day!
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December 06, 2012, 08:18:05 AM
 #233

and bASIC chips have been done for a while (https://www.btcfpga.com/forum/index.php?topic=203.msg1445#msg1445)



I have orders from all 3...I just want someone to ship, so that I can stop checking the forums every fucking day!
Amen!

That's what I do every day when I am working. Read and wait.


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December 06, 2012, 08:20:43 AM
 #234

I might be a little tired, but I had a really hard time following you.

I edited my post to make it more clear: https://bitcointalk.org/index.php?topic=120184.msg1381594#msg1381594
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December 06, 2012, 09:04:24 AM
 #235

This update is mainly to address the uncertainty that have been surrounding the ASIC scene recently due to the lackluster performance by our competitors. We will be walking you through our process of getting the ASIC fabricated. Unlike our competitors we are a in-house team and everyone is always on the same page.

Another update will address the actual status of our chips as we have obtained word from TSMC whom will offer us weekly updates on their website. All in all, see our arguments below regarding our competitors and wait for weekly updates directly from TSMC.

Anyhow, any of our numbers, estimates, and shipping date have not changed, just in case somebody got the wrong idea about this update.


First things first. the following Gallery is our contract with TSMC with pricing and other sensitive information removed. http://imgur.com/a/DnUNm


Some background information on ASIC production process, before tape out, 3 day before uploading GDS, we fill out a MT form with TSMC detailing the ASIC specific information so they may understand what we are doing. The gallery is here http://imgur.com/a/YOLez


to put simply, to create the physical ASIC goes something like this.

sign contract -> submit GDS for review -> mask making -> wafer making -> ship to packaging company -> packaging -> shipping.
Only then can the chips be in your hands or placed on PCB for finalization.

This whole process will take 30-50 days depending on the processor node technology used, mainly due to the increasing in layer number as you go down in processor size. for example, we have 29 layers, and since TSMC is one of the big companies in fabrication, each layer take 1.2 ( normal lot ) day per layer. in addition, accordingly to friedcat, their fab is producing 4 layers every week [odd, but I guess it is possible if fab is small].

This also means while you wait for the wafer(chips) fabrication you can not do anything else, it is usually around this time you make sure you have everything else ready.

a few things to note is,

1. while this wafer making process is going, you can't cancel it, or make adjustments, and if you wish to change anything, you will have to re-run this whole work flow all over again ( the large amount of the NRE upwards of 6 digits in USD is paid when you make the MASK). so anytime, BFL mention they are waiting for chips to come e.g. next week, but if they are still making adjustments, then this is physically impossible. In addition, fabrication company don't do chip packaging, if they are expecting the chips to arrive next week that means the production is already finished and they are probably in the chip packaging company (it is usually this time you find out if your chips work or not. which can also take some time since you'll have to test each of the chips for defects.)

2. the whole chip fabrication is very mathematically predictable based on the number of layers your ASIC has and the speed which the fabrication company can produce a layer. There is no such thing as a fabrication company giving a "fuzzy" date when it comes to when the chips will come from the assembly line. The only number that can vary is the shipping time from the fabrication company to the packaging company, but even that is no more than a few days of difference, depending on the shipping method.

3.a if bASIC made an MPW to start (which is the correct way to save money, but not time). the cost to get large amount of chips during this time is astronomical, however the average size is about 50. It is unheard of for somebody to only produce 2 chips to built a prototype and now no longer have any chips left over to build another prototype.

3.b. Even after testing MWP and everything is fine, it'll take the same amount of time to produce a new MASK ( cost and everything ) then make wafers, which will take another 30 - 50 days, which I suppose is consistent with bASIC's new mid-Jan shipping date, ( but this is optimistic estimate, the regular workflow is about 2 month)

3.c. what we think that happened is bASIC has licensed a SHA256 core, the IP company has already produced demo ASICs that utilizes this core, and did some math on how many core you can placed in the chip to obtain the 14GH/s estimated hashrate, while regular SHA256 and Bitcoin's blockchain hashing algorithm is not very different but it is not something you can compare via simulation without making an actual chip, and if they made an actual chip, even if it doesn't perform up to specifications you can still demonstrate it and be world first.

the conclusion is as follows.

1. If BFL really have chips coming, then they are not making any so-to-speak "clock buffer adjustments", either that or they don't have any chips coming and have not tape-out at all, it is also entirely possible that they have not make the MASK yet either. I guess we will find out on the week of the 11th, in this month hopefully.

2. we believe bASIC has no prototype, or have any chips. Also we at Avalon have also explored the possibility of licensing an IP core, but after some in-house comparison, none of the core on the market is superior to our own, thus we eliminated that option.

Questions, Comments are welcome.

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December 06, 2012, 09:32:20 AM
 #236

Oh, TSMC is using 300mm wafers. That is good to know.

Edit: Why does it say under one of the (online forms) that it failed the DRC check? (Design Rule Check)

Is that because you did something unusual with the chip that the DRC would fail the automatic checks?


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December 06, 2012, 09:50:12 AM
 #237

Thank for sharing the info.

However you did not black out the top pixel line of the price digits, so we can still make them out by comparing them with other non-obscured digits in the document (I almost wonder if you did this intentionally):


Pilot / Engineering Wafer Lot Price = either $1x,xxx.xx or $4x,xxx.xx
Production Wafer Unit Price = $4,xxx.xx
Mask Set Price = $2xx,xxx


It is probably possible to make out some of the unknown 'x' digits by counting the spacing between the pixels, but I was too lazy to do it. The most significantly digit is the most important one anyway.

This price quote is a proof to people who don't believe that ASICs are cheap to manufacture, after NRE costs are recovered. A 12-inch wafer costs $4k for Avalon. They will likely make about a thousand chips per wafer assuming a 50 mm² die. Which means each chip technically costs about $4. There is going to be ten chips or so per Avalon device, so $40 of ASIC chips in a device that is sold $1300. That's a profit margin of $1260! (I am simplying here, there are other minor costs: chip packaging, other components, PCB, etc, maybe $100-$200 maximum). Of course this insane profit margin is only valid once NRE costs ($200k+) are recovered. But some/all ASIC vendors will eventually recover them... so expect ASIC prices to eventually drop massively.
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December 06, 2012, 10:05:38 AM
 #238

Thank for sharing the info.

However you did not black out the top pixel line of the price digits, so we can still make them out by comparing them with other non-obscured digits in the document:

Pilot / Engineering Wafer Lot Price = either $1x,xxx.xx or $4x,xxx.xx
Production Wafer Unit Price = $4,xxx.xx
Mask Set Price = $2xx,xxx

It is probably possible to make out some of the unknown 'x' digits by counting the spacing between the pixels, but I was too lazy to do it. The most significantly digit is the most important one anyway.

This price quote is a proof to people who don't believe that ASICs are cheap to manufacture, after NRE costs are recovered. A 12-inch wafer costs $4k for Avalon. They will likely make about a thousand chips per wafer assuming a 50 mm² die. Which means each chip technically costs about $4. There is going to be ten chips or so per Avalon device, so $40 of ASIC chips in a device that is sold $1300. That's a profit margin of $1260! (I am simplying here, there are other minor costs: chip packaging, other components, PCB, etc, maybe $100-$200 maximum). Of course this insane profit margin is only valid once NRE costs ($200k+) are recovered. But some/all ASIC vendors will eventually recover them... so expect ASIC prices to eventually drop massively.

Actually this is very wrong, at this point in time, when we initially made the 300 order limitation, we were right at our break even point, and currently due to fees and other some problems, we are in fact in the red. Also while we can not reveal our chip numbers per unit, but it is much greater than 10 chips. Everyone is simply under the impression that 7GH/s chips are the "norm" due to what I believe to be false advertisement by the competition.

If you can get me those other components you mentioned like PCB, PSU and other stuff for 100-200 dollars maximum, maybe we should hire you to manage our component purchasing! a single good PSU is near $100...

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December 06, 2012, 10:10:15 AM
 #239

Thank for sharing the info.

However you did not black out the top pixel line of the price digits, so we can still make them out by comparing them with other non-obscured digits in the document:

Pilot / Engineering Wafer Lot Price = either $1x,xxx.xx or $4x,xxx.xx
Production Wafer Unit Price = $4,xxx.xx
Mask Set Price = $2xx,xxx

It is probably possible to make out some of the unknown 'x' digits by counting the spacing between the pixels, but I was too lazy to do it. The most significantly digit is the most important one anyway.

This price quote is a proof to people who don't believe that ASICs are cheap to manufacture, after NRE costs are recovered. A 12-inch wafer costs $4k for Avalon. They will likely make about a thousand chips per wafer assuming a 50 mm² die. Which means each chip technically costs about $4. There is going to be ten chips or so per Avalon device, so $40 of ASIC chips in a device that is sold $1300. That's a profit margin of $1260! (I am simplying here, there are other minor costs: chip packaging, other components, PCB, etc, maybe $100-$200 maximum). Of course this insane profit margin is only valid once NRE costs ($200k+) are recovered. But some/all ASIC vendors will eventually recover them... so expect ASIC prices to eventually drop massively.

Actually this is very wrong, at this point in time, when we initially made the 300 order limitation, we were right at our break even point, and currently due to fees and other some problems, we are in fact in the red. Also while we can not reveal our chip numbers per unit, but it is much greater than 10 chips. Everyone is simply under the impression that 7GH/s chips are the "norm".

If you can get me those other components you mentioned like PCB, PSU and other stuff for 100-200 dollars maximum, maybe we should hire you to manage our component purchasing! a single good PSU is near $100...

Of course, I am simplifying and ignoring other costs: human resources (engineers), shipping, assembly, etc. And yes Avalon, as a standalone device, is a more complex/expensive than the competition devices, so add $100-150 to my numbers as I wasn't thinking about it. I have no doubt all ASIC companies are in the red initially. It will take you guys months to start being in the black. But after that point, you do agree with me that it will be mainly profits... (and good for you! or else you would not have started the business venture at all).

(PS: the number of chips per Avalon is mostly irrevelant to these price estimations. I estimate you will have about 500mm² of die area per Avalon device. Whether it is 10 x 50mm² chips or 20 x 25 mm² chips is irrelevant to my numbers. 500mm² of wafer space will cost $40 regardless.)
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December 06, 2012, 10:17:39 AM
 #240



This price quote is a proof to people who don't believe that ASICs are cheap to manufacture, after NRE costs are recovered. A 12-inch wafer costs $4k for Avalon. They will likely make about a thousand chips per wafer assuming a 50 mm² die. Which means each chip technically costs about $4. There is going to be ten chips or so per Avalon device, so $40 of ASIC chips in a device that is sold $1300. That's a profit margin of $1260! (I am simplying here, there are other minor costs: chip packaging, other components, PCB, etc, maybe $100-$200 maximum). Of course this insane profit margin is only valid once NRE costs ($200k+) are recovered. But some/all ASIC vendors will eventually recover them... so expect ASIC prices to eventually drop massively.
I thought they said their chips were 15mm²?

That would be a boatload of chips on a 300mm wafer.


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