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Author Topic: FPGA potential  (Read 1564 times)
Curiousity
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January 22, 2013, 03:31:18 PM
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Hi, I'm looking at what could be done with a serious FPGA,  seems to me there are lots of projects and products out there based on cost effective devices or generic platforms for obvious reasons but what if we had available far more exotic FPGAs, any FPGA gurus out there able to or care to speculate or simulate what could be done with a BIG Virtex2 or big virtex7 -  on sheer scale alone if you can get 200M/H from a 150K Spartan with 2cores you could fit 20 - 25 cores in a 2 million gate Virtex7 or 100 cores in an 8million gate virtex2. Any thoughts? Are we talking 2, 4, 10GH?Huh
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January 22, 2013, 04:36:46 PM
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Hi, I'm looking at what could be done with a serious FPGA,  seems to me there are lots of projects and products out there based on cost effective devices or generic platforms for obvious reasons but what if we had available far more exotic FPGAs, any FPGA gurus out there able to or care to speculate or simulate what could be done with a BIG Virtex2 or big virtex7 -  on sheer scale alone if you can get 200M/H from a 150K Spartan with 2cores you could fit 20 - 25 cores in a 2 million gate Virtex7 or 100 cores in an 8million gate virtex2. Any thoughts? Are we talking 2, 4, 10GH?Huh

We are probably talking in that range, but damn the price of those chips.

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January 22, 2013, 05:18:25 PM
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Understand, but if you happen to have some hanging around doing nothing at zero cost  Shocked Wink
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January 22, 2013, 09:49:42 PM
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Understand, but if you happen to have some hanging around doing nothing at zero cost  Shocked Wink

Well, for the newer Virtex-6 and Virtex-7 chips Xilinx had to release a new tool set, because the number of gates made their existing programming tools intolerably slow and impractical. With the 28nm process used on the latest Virtex-7's there's even a decent chance that they would be capable of competing with the ASICs that are (Avalon) and might be (BFL and post buy out bASIC) shipping.

The catch is though that for these chips we are talking about a $6,000 to $10,000 per chip cost, so there probably aren't too many of these just laying around waiting for people to check them out from work, appropriate them from a university lab, or filtering down into hobbyist hands for quite some time. There's also the matter of how much of a pain in the ass it would be to program these for mining seeing how long it took for simpler FPGAs to get configured for this purpose on any substantial scale.

It would be awesome if someone could so this as a proof of concept though, maybe someday SHA-2 hashing will be a benchmark FPGA manufacturers use to express the relative performance of their products. If this were the case in 2011-2012 the mining landscape would probably be very different, because someone might have seen a business case to run with high end FPGAs over GPUs and even low end FPGAs.

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January 23, 2013, 10:46:45 PM
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Understand, but if you happen to have some hanging around doing nothing at zero cost  Shocked Wink

Well, for the newer Virtex-6 and Virtex-7 chips Xilinx had to release a new tool set, because the number of gates made their existing programming tools intolerably slow and impractical. With the 28nm process used on the latest Virtex-7's there's even a decent chance that they would be capable of competing with the ASICs that are (Avalon) and might be (BFL and post buy out bASIC) shipping.

The catch is though that for these chips we are talking about a $6,000 to $10,000 per chip cost, so there probably aren't too many of these just laying around waiting for people to check them out from work, appropriate them from a university lab, or filtering down into hobbyist hands for quite some time. There's also the matter of how much of a pain in the ass it would be to program these for mining seeing how long it took for simpler FPGAs to get configured for this purpose on any substantial scale.

It would be awesome if someone could so this as a proof of concept though, maybe someday SHA-2 hashing will be a benchmark FPGA manufacturers use to express the relative performance of their products. If this were the case in 2011-2012 the mining landscape would probably be very different, because someone might have seen a business case to run with high end FPGAs over GPUs and even low end FPGAs.

The problem is that Xilinx ALWAYS has had completely GASH tools for their silicon... switching to 'C' is going to solve NOTHING.
Even doing the simplest things on their 14.x toolset is a complete pain in the ass.... plus its java front end is so full of bugs.. that the memory leaks it produces are bigger that the ice-burg that hit the titanic.

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January 23, 2013, 10:52:07 PM
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Understand, but if you happen to have some hanging around doing nothing at zero cost  Shocked Wink

Well, for the newer Virtex-6 and Virtex-7 chips Xilinx had to release a new tool set, because the number of gates made their existing programming tools intolerably slow and impractical. With the 28nm process used on the latest Virtex-7's there's even a decent chance that they would be capable of competing with the ASICs that are (Avalon) and might be (BFL and post buy out bASIC) shipping.

The catch is though that for these chips we are talking about a $6,000 to $10,000 per chip cost, so there probably aren't too many of these just laying around waiting for people to check them out from work, appropriate them from a university lab, or filtering down into hobbyist hands for quite some time. There's also the matter of how much of a pain in the ass it would be to program these for mining seeing how long it took for simpler FPGAs to get configured for this purpose on any substantial scale.

It would be awesome if someone could so this as a proof of concept though, maybe someday SHA-2 hashing will be a benchmark FPGA manufacturers use to express the relative performance of their products. If this were the case in 2011-2012 the mining landscape would probably be very different, because someone might have seen a business case to run with high end FPGAs over GPUs and even low end FPGAs.

The problem is that Xilinx ALWAYS has had completely GASH tools for their silicon... switching to 'C' is going to solve NOTHING.
Even doing the simplest things on their 14.x toolset is a complete pain in the ass.... plus its java front end is so full of bugs.. that the memory leaks it produces are bigger that the ice-burg that hit the titanic.

In Software development the official term is

 Is a good idea but "Its a Totally F*cked"

Or if u are still keen "Good Luck with That"

... Cool

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Curiousity
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January 24, 2013, 05:56:26 PM
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Ok, that changes my outlook on the project, I had read elsewhere that building a "quick and dirty" image should take a couple of days I suppose if thats not the case then I'm not likely to find anyone interested in collaborating with the above mentioned proof of concept then.  Sad. Shame I can't make use of the devices I have access to.....
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