FYI Intel & Altera to Build Next-Generation FPGAs on Intel's 14 nm Tri-Gate Tech

[Sitarow]

"Products are targeted at ultra high-performance systems such as military, wireline communications and cloud networking.

Intel has announced that it has reached an agreement with PLD (Programmable logic device) manufacturer Altera to product FPGAs (Field-programmable gate array) on Intel's 14 nm tri-gate transistor technology. According to the announcement, these next generation products will enable breakthrough levels of performance and power efficiencies not otherwise possible and further the company's ability to deliver on the promise of silicon convergence by delivering a more flexible and economical alternative to traditional ASICs and ASSP."

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[Phinnaeus Gage]

Samsung reveals its first 14nm FinFET test chip, should offer substantial power improvements in future silicon

[polrpaul]

wow.. it's all happening.

[Third Way]

Explain like I'm 5 anyone? How does this help bitcoin mining? Do these serve for mining just as well as "asics"? How do they improve on the structure?

[Sitarow]

Explain like I'm 5 anyone? How does this help bitcoin mining? Do these serve for mining just as well as "asics"? How do they improve on the structure?

"At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. Spartan®-6 and Virtex®-6 FPGAs offer lower power, simpler power systems and PCB complexity, better reliability, and lower system cost. This white paper details how Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex-6 (40 nm) FPGA families, achieving dramatic power reductions over previous generation devices."

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Presently Altera HardCopy V ASICs: Low Risk, Cost, and Power Consumption is at 28 nm 2010 tech
Altera FPGA's at 28 nm 2011 tech.

Source

[Carlton Banks]

Explain like I'm 5 anyone? How does this help bitcoin mining? Do these serve for mining just as well as "asics"? How do they improve on the structure?

Intel are licencing their ultra exclusive (I believe no one else is doing anything smaller than 28nm right now) 22nm manufacturing technology to Altera to make their FPGAs with. Altera FPGAs could be used for Bitcoin mining, but it sounds a little unlikely as a practical proposition, as they'll probably be premium priced initially (think $1500+). The 22nm improvement is more electrically efficient, so you get more GHz per watt of electricity than the people etching their chips at 28nm. It's basically telling you that the manufacturing process for the chip is carving the features out of the silicon at an even finer degree of miniaturisation, and that the practical improvements would be: lower energy consumption, less heat, slightly more physical efficiency as either the chip package will be smaller or there could be more transistors on the chip with the same size package.

I guess that higher clock speeds could also be achieved, as that's been seen with Intel's own 22nm chips. Maybe these future Altera chips might be more sensible for Bitcoin mining than I'm estimating, but the market will decide whether that's viable or not (and some coder will have to develop a representation of the algorithm Bitcoin uses for mining specifically for the Altera, so the first you'll hear of it, someone will already have done it). I find it hard to believe how these can ultimately compete with ASICs though, any possible competitive advantage would be short lived at best. ASIC's are currently at 110nm, which is like 5 years old compared to current technology, but that's not going to stay that way for at all long.

One thing I can see right now thinking about this: ASIC manufacturers are always going to have long periods with no stock on hand, only for it to more or less sell out instantly when they do make some available. This won't be quite the same problem for someone trying to take advantage of 22nm FPGAs, as they'll be more readily available than specialist ASICs, and they'll also not be totally dependent on the stability of the Bitcoin block hashing routine (ASIC chip designs are useless for mining if this is changed, FPGA's are not fixed purpose like this and could be re-used for whatever change the dev team potentially came up with). Maybe FPGAs might make a short lived hashing-shortage based comeback, depends a bit on whether a genuine digital gold rush takes place. For now though, ASICs are still the only game in town (that hasn't quuuuuite convincingly been released to the public. yet.)

edit: Sitarow has pointed out that this refers to 14nm process (Altera made a deal at 22nm too). Similar electrical efficiency improvements occur down at 14nm, but I would of course point out that Intel aren't scheduled to bring 14nm chips out themselves until Q3/4 of this year. Any Altera chips using 14nm won't be available til 2014 earliest, I suspect. Power efficiencies at 22nm weren't quite as impressive as Intel touted, the extent of any improvements at 14nm are yet to be seen. One thing I do know: Intel have started to alter the way they measure their electrical efficiency figures for chips, I think it was arstechnica that exposed them on that one. So don't necessarily take what you see at a glance as reliable, check whether the figures are still measured in TDP

[Magnate]

Correct me if I don't quote this quite correctly

Avalon -> 110Nm
bASIC -> 90Nm (had they launched)
BFL    -> 60Nm
un-named secrete vendor looking for integrators->  28Nm

Avalon are currently at around 10w per Ghs, BFL are looking at 1-1.2w per Ghs, this new prospect on the horizon could be down around .5-.75w per Ghs

Unless a 14Nm FPGA can give a business case of improved watts per Ghs and a decent price per Ghs then why would you bother?

Avalon is likely to fall out of the market with their power usage. Once they have got their ROI maybe they will start using this new vendor. BFL may then have to put their chips on the market as well to help get their volumes up, but they probably get more profit selling complete boards. However that might change for them to do a smaller genII ASIC. They do nice external cased BFL miners, then they sell to somebody who will do something more raw.

[Puppet]

A 14nm FPGA might be competitive with Avalon, but its probably still at least a year out, and it will be competing with 65nm and probably even 28nm asics. There is no chance in hell it will be competitive with those, not in price, not in power efficiency. Rule of thumb, FPGA's are 10x as big and 10x more power hungry than ASICs on the same process node.

[RoadStress]

Quick noob question: what happens when technology reaches  1nm or 0.5 nm? What is next?

[Puppet]

Quick noob question: what happens when technology reaches  1nm or 0.5 nm? What is next?

It stops at some point. You cant get smaller than atomic level, and we are getting really close. At 14nm, a "wire" is only 30 atoms wide.  And before you reach atomic level, you also get all sorts of weird quantum mechanical effects. Transistors no longer work as you would expect them. As of now, 5nm seems doable at some point in the future, probably using carbon nanotubes,  but there is a brick wall looming.

[Soros Shorts]

Quick noob question: what happens when technology reaches  1nm or 0.5 nm? What is next?

The lattice spacing between atoms in silicon is 0.54 nm. It is safe to say that 0.5 nm technology is impossible (at least with silicon).

[RoadStress]

So we are just a few years away from hitting max silicon technology? Is there anything else being developed or we just stop at 5nm?

[Puppet]

carbon nanotubes have the potential to carry us a bit further, but anything smaller than a few nm may never happen; even if it ever becomes technically feasible, its doubtful if it will ever be economically feasible (Intels latest 14nm fab  will cost > $5 billion and costs are increasing exponentially with smaller nodes).

[Carlton Banks]

So we are just a few years away from hitting max silicon technology? Is there anything else being developed or we just stop at 5nm?

Desktop CPUs are apparently moving to stacking multiple cores (16+ I expect) in between on die RAM layers, creating a kind of core/RAM multilayer sandwich. But mining will not benefit from that change, or at least not the RAM from such a sandwich. I think the mentioned substrate changes might be the only way to go past < 10nm, but that's not gonna be a serious issue for a decade or so. Right now, BFL are struggling to get their 65nm part into customer units inside of 12 months, so I don't think worries about hitting the 5nm ceiling are quite on the table (yet)

[Aseras]

The current evolution is to go massively parallel.
The next step will be to go from binary logic to quantum logic.

[mrb]

The next step is making chips comprised of millions of silicon layers, as opposed to just 10 or so. With each "layer" being a few nanometers thick, that leaves us a relatively big margin to improve performance (30 years of Moore's Law).

[Soros Shorts]

The next step is making chips comprised of millions of silicon layers, as opposed to just 10 or so. With each "layer" being a few nanometers thick, that leaves us a relatively big margin to improve performance (30 years of Moore's Law).

No doubt this allows for an increase in density and more efficient 3-dimensional routing. But how much will this help power consumption?

[RoadStress]

@Puppet I don't care about the money. They are not being an important factor. If there are money to be made then there are money to invest.

@Carlton Banks I wasn't referring to bitcoin mining. I was curious for general technology.

Thank you all for answers.

[Carlton Banks]

The next step is making chips comprised of millions of silicon layers, as opposed to just 10 or so. With each "layer" being a few nanometers thick, that leaves us a relatively big margin to improve performance (30 years of Moore's Law).

No doubt this allows for an increase in density and more efficient 3-dimensional routing. But how much will this help power consumption?

and more to the point (as I believe this is the current research engineering challenge with this tech), how do you efficiently cool such a 3D stack? Particularly at clock speeds that we're used to for current 2D chips. No answers to this so far, or at least the last I heard there weren't. Given the trend for closed environments to achieve new technological ends in electronics and computing, I wonder what on earth we may end up with if this is really the avenue that gets commercially exploited. Cube chips in an oil cooled bath? Maybe a processing farm company could make a secondary business in commercial food frying...

[Puppet]

@Puppet I don't care about the money.

You may not, but the companies that need to pay for it, they do. Most fab operators are already struggling to keep pace because of the astronomical costs of todays <45nm technology. The number of leading edge fabs shrinks every year and its basically down to a 2 or 3 horse race now (Intel, GF and TSMC).  If it costs $50B to build a fab for some future tech that offers no more than 2x higher transistor density than existing fabs, at some point it just wont be worth it to anyone.