Disclaimer: I don't know anything that hasn't been posted here in the forum, and I have been too busy to read more than 5-10% of that, I have no inside info, this is just speculation based on past chip design experience, yadda yadda.
It sounds like BFL is having some difficulties with their chips (a) running at ~25% of rated speed and (b) consuming 4-9x more power than they planned. These numbers are vague since the info in the postings I've come across has always been patchy and has been presented very poorly (they'll quote an actual hashrate but decline to say what device it came from, or show a photo of a kill-a-watt but decline to say exactly what's plugged into it, etc). I would welcome a simple and straightforward posting by BFL saying "we have the chips running at X% of advertised speed and consuming Y J/GH".
They've also mentioned that the wafer-probing tests (which I assume ran only a tiny portion of one chip at a time due to the fact that unpackaged chips overheat when run at full speed) produced the power results they expected, but the packaged chips consume way too much power.
I'm going to make a wild guess here and speculate that they ran all their pre-production SPICE simulations using the default 25 degree C temperature.
This is a pretty common mistake. It would also explain everything I've seen so far.
Circuits always simulate ridiculously well if you run SPICE at 25 degrees. The problem is that any circuit doing substantial amounts of computation will generate enough heat to raise the local temperature to at least 100 degrees C. This in turn reduces the power efficiency even further (circuits running hot run slower and burn more power), an effect that feeds on itself. Even the best packaging and heatsinking still leaves 3-4 degrees C per watt, and often those figures neglect to include the thermal resistivity of the CMOS bulk (another few degrees C per watt). Multiply all of that by a 10-20W chip and the junction temperature is going to be a lot closer to 100-110 degrees than 25 degrees in any sort of reasonable ambient temperature.
Repeated disclaimer: this is just a wild guess, I have almost zero information, I have been way too busy with other urgent crap to read most of the forum threads, etc, etc.
Similar to the OP, I have no inside information, only that which has been posted on the public forums. I do have a few points of clarification - based on my limited understanding of BFL's situation.
1) None of the wafers have been wafer-probed and BFL does not have capability to do so. I would hope and expect they will fix this in the future. If the die do yield well (say > 95% good), then it is reasonable to skip wafer probe and do a "blind build". This is what BFL gambled on.
2) Of the first 6 wafers, they choose to "burn" one by skipping the bumping process (because it was causing delays) and use wire bonding to a bare minimum number of the bump pads. These test die could not be fully tested or run at full speed for the obvious reason that only a few of the power / ground pads were connected. These die from wafer 1 had good power - at least within the expected range. They did this while waiting for the other wafers to get bumped so they could verify functionality of the design.
3) Wafer 2 was bumped and packaged. (Note that wafers 3 to 6 were bumped but NOT packaged at this time. They should be packaged by now though.) These are the chips that have been mounted to test boards and exhibit the high power levels.
4) I have seen nothing posted about the current status of wafers 3 to 6. It is
POSSIBLE that BFL's power issues
COULD be limited to wafer 2 and wafers 3 to 6 will have "good" power. It is well know in the chip business that there can be (and often IS) a variation from wafer to wafer on parameters such as frequency and power. Of course, the fab tries to minimize these variations, but they do occur. Especially for the first wafers out.
5) In addition, there is a variation of different die on the same wafer. If BFL happened to pick poor die for their test boards, then other die from wafer 2 might be lower power. However, I do not think this is likely in this instance.
6) BFL has said they will underclock devices to meet a reasonable power envelope and then ship more units to each customer so that they will still receive the GH/s that they ordered. So if the SC Singles need to run at half speed (30GH/s) to not overload the power circuitry, then a customer that ordered one will actually receive two. I do not expect there to be a fire problem.
7) BFL has said they are re-designing the boards to improve the power situation. To me this is unclear what they are doing. I think Josh said something about using 2 regulators instead of 1 - but I could have that wrong.
The above is true to the best of my understanding but of course could be partly (or completely) wrong since I can only interpret what I've seen on the forums.
Additional disclaimer: As stated earlier on this forum, I have ordered an SC Single. Yes, I am biased but I try to minimize that bias in all my posts and state as much factual information as possible and remove my opinion from it.
