I know that technical details are important, but what we don't know is what will be the hashing power and energy usage.

---SNIP---

Disclaimer:

My calculations below are just guestimations and speculation based on limited experience and sample size.

I would not be suprised if flaws in my reasoning are found.

Also note W/Gh is a manufacturer term for power usage @ ASIC.

I'm currently consumnig another 21% @ the wall (120VAC 90+ supplies).

What KnCMiner has said publicly.

(initially)

43% power reduction.

1440 core per ASIC.

(updated)

Additional 11% power savings spent on more core per ASIC

~1600 core per ASIC

(I subtracted the 11% from the already calculated -43% figure for ~50% total improvement NOT 54%)

currently 28nm 1w/Gh

estimated 20nm 0.5073W/Gh

1600 cores @ current default Oct. 28nm core speed of 750Mhz

3 ASIC, 1200Gh/s each ASIC consuming 608.76 WATTS each.

(that would be like pulling an Elephant out of the hat IMneverHO)

3.6T stock clock

1600 cores @ 500Mhz

4 ASIC, 800Gh/s each ASIC @ 405W

3.2T stock clock

This is doable with heat management on both sides of the chip/PCB.

(based on knowing many 28nm ASIC currently pulling close to 200W 24/7)

They will have to keep adding ASIC till power is managable.

They may add ASIC for other reasons.

IMneverHO it will boil down to how much heat they can pump thru the heatspreader.

Currently the 28nm part has 16cm^2 (40x40mm raised area on 50x50 chip)

A different heatspreader and 25cm^2 is available.

(did they mention a 55x55mm package?)

I'm guessing total @ wall a bit above 2kW

Definately need 200+ VAC circuit for most situations.

A 15A 220VAC(ASSuMEd USA power std.) circuit would be minimum I'd consider for a single Neptune.

YMMV